VirtualBox

source: vbox/trunk/src/VBox/Additions/x11/x11include/XFree86-4.3/Xserver/xf86Pci.h@ 97956

最後變更 在這個檔案從97956是 69098,由 vboxsync 提交於 7 年 前

Clean up XFree86 driver header files.
bugref:3810: X11 Guest Additions maintenance
Over the years we have cleaned up the layout in the tree of the X.Org
header files we use to build drivers. The XFree86 ones were still in their
original, rather sub-optimal layout. This change fixes that.
  • 屬性 svn:eol-style 設為 native
檔案大小: 26.5 KB
行 
1/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/xf86Pci.h,v 1.36 2003/02/18 15:42:12 tsi Exp $ */
2/*
3 * Copyright 1998 by Concurrent Computer Corporation
4 *
5 * Permission to use, copy, modify, distribute, and sell this software
6 * and its documentation for any purpose is hereby granted without fee,
7 * provided that the above copyright notice appear in all copies and that
8 * both that copyright notice and this permission notice appear in
9 * supporting documentation, and that the name of Concurrent Computer
10 * Corporation not be used in advertising or publicity pertaining to
11 * distribution of the software without specific, written prior
12 * permission. Concurrent Computer Corporation makes no representations
13 * about the suitability of this software for any purpose. It is
14 * provided "as is" without express or implied warranty.
15 *
16 * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
17 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
18 * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
19 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
20 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
21 * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
22 * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
23 * SOFTWARE.
24 *
25 * Copyright 1998 by Metro Link Incorporated
26 *
27 * Permission to use, copy, modify, distribute, and sell this software
28 * and its documentation for any purpose is hereby granted without fee,
29 * provided that the above copyright notice appear in all copies and that
30 * both that copyright notice and this permission notice appear in
31 * supporting documentation, and that the name of Metro Link
32 * Incorporated not be used in advertising or publicity pertaining to
33 * distribution of the software without specific, written prior
34 * permission. Metro Link Incorporated makes no representations
35 * about the suitability of this software for any purpose. It is
36 * provided "as is" without express or implied warranty.
37 *
38 * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
39 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
40 * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
41 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
42 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
43 * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
44 * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
45 * SOFTWARE.
46 *
47 * This file is derived in part from the original xf86_PCI.h that included
48 * following copyright message:
49 *
50 * Copyright 1995 by Robin Cutshaw <[email protected]>
51 *
52 * Permission to use, copy, modify, distribute, and sell this software and its
53 * documentation for any purpose is hereby granted without fee, provided that
54 * the above copyright notice appear in all copies and that both that
55 * copyright notice and this permission notice appear in supporting
56 * documentation, and that the names of the above listed copyright holder(s)
57 * not be used in advertising or publicity pertaining to distribution of
58 * the software without specific, written prior permission. The above listed
59 * copyright holder(s) make(s) no representations about the suitability of this
60 * software for any purpose. It is provided "as is" without express or
61 * implied warranty.
62 *
63 * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
64 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
65 * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
66 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
67 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
68 * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
69 * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
70 *
71 */
72
73/*
74 * This file contains just the public interface to the PCI code.
75 * Drivers should use this file rather than Pci.h.
76 */
77
78#ifndef _XF86PCI_H
79#define _XF86PCI_H 1
80#include "Xarch.h"
81#include "Xfuncproto.h"
82#include "misc.h"
83
84/*
85 * PCI cfg space definitions (e.g. stuff right out of the PCI spec)
86 */
87
88/* Device identification register */
89#define PCI_ID_REG 0x00
90
91/* Command and status register */
92#define PCI_CMD_STAT_REG 0x04
93#define PCI_CMD_BASE_REG 0x10
94#define PCI_CMD_BIOS_REG 0x30
95#define PCI_CMD_MASK 0xffff
96#define PCI_CMD_IO_ENABLE 0x01
97#define PCI_CMD_MEM_ENABLE 0x02
98#define PCI_CMD_MASTER_ENABLE 0x04
99#define PCI_CMD_SPECIAL_ENABLE 0x08
100#define PCI_CMD_INVALIDATE_ENABLE 0x10
101#define PCI_CMD_PALETTE_ENABLE 0x20
102#define PCI_CMD_PARITY_ENABLE 0x40
103#define PCI_CMD_STEPPING_ENABLE 0x80
104#define PCI_CMD_SERR_ENABLE 0x100
105#define PCI_CMD_BACKTOBACK_ENABLE 0x200
106#define PCI_CMD_BIOS_ENABLE 0x01
107
108/* base class */
109#define PCI_CLASS_REG 0x08
110#define PCI_CLASS_MASK 0xff000000
111#define PCI_CLASS_SHIFT 24
112#define PCI_CLASS_EXTRACT(x) \
113 (((x) & PCI_CLASS_MASK) >> PCI_CLASS_SHIFT)
114
115/* base class values */
116#define PCI_CLASS_PREHISTORIC 0x00
117#define PCI_CLASS_MASS_STORAGE 0x01
118#define PCI_CLASS_NETWORK 0x02
119#define PCI_CLASS_DISPLAY 0x03
120#define PCI_CLASS_MULTIMEDIA 0x04
121#define PCI_CLASS_MEMORY 0x05
122#define PCI_CLASS_BRIDGE 0x06
123#define PCI_CLASS_COMMUNICATIONS 0x07
124#define PCI_CLASS_SYSPERIPH 0x08
125#define PCI_CLASS_INPUT 0x09
126#define PCI_CLASS_DOCKING 0x0a
127#define PCI_CLASS_PROCESSOR 0x0b
128#define PCI_CLASS_SERIALBUS 0x0c
129#define PCI_CLASS_WIRELESS 0x0d
130#define PCI_CLASS_I2O 0x0e
131#define PCI_CLASS_SATELLITE 0x0f
132#define PCI_CLASS_CRYPT 0x10
133#define PCI_CLASS_DATA_ACQUISTION 0x11
134#define PCI_CLASS_UNDEFINED 0xff
135
136/* sub class */
137#define PCI_SUBCLASS_MASK 0x00ff0000
138#define PCI_SUBCLASS_SHIFT 16
139#define PCI_SUBCLASS_EXTRACT(x) \
140 (((x) & PCI_SUBCLASS_MASK) >> PCI_SUBCLASS_SHIFT)
141
142/* Sub class values */
143/* 0x00 prehistoric subclasses */
144#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
145#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
146
147/* 0x01 mass storage subclasses */
148#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
149#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
150#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
151#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
152#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
153
154/* 0x02 network subclasses */
155#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
156#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
157#define PCI_SUBCLASS_NETWORK_FDDI 0x02
158#define PCI_SUBCLASS_NETWORK_MISC 0x80
159
160/* 0x03 display subclasses */
161#define PCI_SUBCLASS_DISPLAY_VGA 0x00
162#define PCI_SUBCLASS_DISPLAY_XGA 0x01
163#define PCI_SUBCLASS_DISPLAY_MISC 0x80
164
165/* 0x04 multimedia subclasses */
166#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
167#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
168#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
169
170/* 0x05 memory subclasses */
171#define PCI_SUBCLASS_MEMORY_RAM 0x00
172#define PCI_SUBCLASS_MEMORY_FLASH 0x01
173#define PCI_SUBCLASS_MEMORY_MISC 0x80
174
175/* 0x06 bridge subclasses */
176#define PCI_SUBCLASS_BRIDGE_HOST 0x00
177#define PCI_SUBCLASS_BRIDGE_ISA 0x01
178#define PCI_SUBCLASS_BRIDGE_EISA 0x02
179#define PCI_SUBCLASS_BRIDGE_MC 0x03
180#define PCI_SUBCLASS_BRIDGE_PCI 0x04
181#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
182#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
183#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
184#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
185#define PCI_SUBCLASS_BRIDGE_MISC 0x80
186#define PCI_IF_BRIDGE_PCI_SUBTRACTIVE 0x01
187
188/* 0x07 communications controller subclasses */
189#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
190#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
191#define PCI_SUBCLASS_COMMUNICATIONS_MULTISERIAL 0x02
192#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
193#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
194
195/* 0x08 generic system peripherals subclasses */
196#define PCI_SUBCLASS_SYSPERIPH_PIC 0x00
197#define PCI_SUBCLASS_SYSPERIPH_DMA 0x01
198#define PCI_SUBCLASS_SYSPERIPH_TIMER 0x02
199#define PCI_SUBCLASS_SYSPERIPH_RTC 0x03
200#define PCI_SUBCLASS_SYSPERIPH_HOTPCI 0x04
201#define PCI_SUBCLASS_SYSPERIPH_MISC 0x80
202
203/* 0x09 input device subclasses */
204#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
205#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
206#define PCI_SUBCLASS_INPUT_MOUSE 0x02
207#define PCI_SUBCLASS_INPUT_SCANNER 0x03
208#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
209#define PCI_SUBCLASS_INPUT_MISC 0x80
210
211/* 0x0a docking station subclasses */
212#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
213#define PCI_SUBCLASS_DOCKING_MISC 0x80
214
215/* 0x0b processor subclasses */
216#define PCI_SUBCLASS_PROCESSOR_386 0x00
217#define PCI_SUBCLASS_PROCESSOR_486 0x01
218#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
219#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
220#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
221#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
222#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
223
224/* 0x0c serial bus controller subclasses */
225#define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00
226#define PCI_SUBCLASS_SERIAL_ACCESS 0x01
227#define PCI_SUBCLASS_SERIAL_SSA 0x02
228#define PCI_SUBCLASS_SERIAL_USB 0x03
229#define PCI_SUBCLASS_SERIAL_FIBRECHANNEL 0x04
230#define PCI_SUBCLASS_SERIAL_SMBUS 0x05
231
232/* 0x0d wireless controller subclasses */
233#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
234#define PCI_SUBCLASS_WIRELESS_CONSUMER_IR 0x01
235#define PCI_SUBCLASS_WIRELESS_RF 0x02
236#define PCI_SUBCLASS_WIRELESS_MISC 0x80
237
238/* 0x0e intelligent I/O controller subclasses */
239#define PCI_SUBCLASS_I2O_I2O 0x00
240
241/* 0x0f satellite communications controller subclasses */
242#define PCI_SUBCLASS_SATELLITE_TV 0x01
243#define PCI_SUBCLASS_SATELLITE_AUDIO 0x02
244#define PCI_SUBCLASS_SATELLITE_VOICE 0x03
245#define PCI_SUBCLASS_SATELLITE_DATA 0x04
246
247/* 0x10 encryption/decryption controller subclasses */
248#define PCI_SUBCLASS_CRYPT_NET_COMPUTING 0x00
249#define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x10
250#define PCI_SUBCLASS_CRYPT_MISC 0x80
251
252/* 0x11 data acquisition and signal processing controller subclasses */
253#define PCI_SUBCLASS_DATAACQ_DPIO 0x00
254#define PCI_SUBCLASS_DATAACQ_MISC 0x80
255
256
257/* Header */
258#define PCI_HEADER_MISC 0x0c
259#define PCI_HEADER_MULTIFUNCTION 0x00800000
260
261/* Interrupt configration register */
262#define PCI_INTERRUPT_REG 0x3c
263#define PCI_INTERRUPT_PIN_MASK 0x0000ff00
264#define PCI_INTERRUPT_PIN_EXTRACT(x) \
265 ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff)
266#define PCI_INTERRUPT_PIN_NONE 0x00
267#define PCI_INTERRUPT_PIN_A 0x01
268#define PCI_INTERRUPT_PIN_B 0x02
269#define PCI_INTERRUPT_PIN_C 0x03
270#define PCI_INTERRUPT_PIN_D 0x04
271
272#define PCI_INTERRUPT_LINE_MASK 0x000000ff
273#define PCI_INTERRUPT_LINE_EXTRACT(x) \
274 ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff)
275#define PCI_INTERRUPT_LINE_INSERT(x,v) \
276 (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0))
277
278/* Base registers */
279#define PCI_MAP_REG_START 0x10
280#define PCI_MAP_REG_END 0x28
281#define PCI_MAP_ROM_REG 0x30
282
283#define PCI_MAP_MEMORY 0x00000000
284#define PCI_MAP_IO 0x00000001
285
286#define PCI_MAP_MEMORY_TYPE 0x00000007
287#define PCI_MAP_IO_TYPE 0x00000003
288
289#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
290#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
291#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
292#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
293#define PCI_MAP_MEMORY_CACHABLE 0x00000008
294#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e
295#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
296
297#define PCI_MAP_IO_ATTR_MASK 0x00000003
298
299#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)
300#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))
301
302#define PCI_MAP_IS64BITMEM(b) \
303 (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
304
305#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
306#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1))
307#define PCIGETMEMORY64(b) \
308 (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
309
310#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
311
312#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)
313
314#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001
315#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800
316
317#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)
318
319/* PCI-PCI bridge mapping registers */
320#define PCI_PCI_BRIDGE_BUS_REG 0x18
321#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000
322#define PCI_SECONDARY_BUS_MASK 0x0000ff00
323#define PCI_PRIMARY_BUS_MASK 0x000000ff
324
325#define PCI_PCI_BRIDGE_IO_REG 0x1c
326#define PCI_PCI_BRIDGE_MEM_REG 0x20
327#define PCI_PCI_BRIDGE_PMEM_REG 0x24
328
329#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00)
330#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00)
331
332#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000)
333#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000)
334
335#define PCI_PCI_BRIDGE_CONTROL_REG 0x3E
336#define PCI_PCI_BRIDGE_PARITY_EN 0x01
337#define PCI_PCI_BRIDGE_SERR_EN 0x02
338#define PCI_PCI_BRIDGE_ISA_EN 0x04
339#define PCI_PCI_BRIDGE_VGA_EN 0x08
340#define PCI_PCI_BRIDGE_MASTER_ABORT_EN 0x20
341#define PCI_PCI_BRIDGE_SECONDARY_RESET 0x40
342#define PCI_PCI_BRIDGE_FAST_B2B_EN 0x80
343/* header type 2 extensions */
344#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
345#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
346#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
347#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
348#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
349
350#define PCI_CB_SEC_STATUS_REG 0x16 /* Secondary status */
351#define PCI_CB_PRIMARY_BUS_REG 0x18 /* PCI bus number */
352#define PCI_CB_CARD_BUS_REG 0x19 /* CardBus bus number */
353#define PCI_CB_SUBORDINATE_BUS_REG 0x1a /* Subordinate bus number */
354#define PCI_CB_LATENCY_TIMER_REG 0x1b /* CardBus latency timer */
355#define PCI_CB_MEM_BASE_0_REG 0x1c
356#define PCI_CB_MEM_LIMIT_0_REG 0x20
357#define PCI_CB_MEM_BASE_1_REG 0x24
358#define PCI_CB_MEM_LIMIT_1_REG 0x28
359#define PCI_CB_IO_BASE_0_REG 0x2c
360#define PCI_CB_IO_LIMIT_0_REG 0x30
361#define PCI_CB_IO_BASE_1_REG 0x34
362#define PCI_CB_IO_LIMIT_1_REG 0x38
363#define PCI_CB_BRIDGE_CONTROL_REG 0x3E
364
365#define PCI_CB_IO_RANGE_MASK ~0x03
366#define PCI_CB_IOBASE(x) (x & PCI_CB_IO_RANGE_MASK)
367#define PCI_CB_IOLIMIT(x) ((x & PCI_CB_IO_RANGE_MASK) + 3)
368
369/* Subsystem identification register */
370#define PCI_SUBSYSTEM_ID_REG 0x2c
371
372/* User defined cfg space regs */
373#define PCI_REG_USERCONFIG 0x40
374#define PCI_OPTION_REG 0x40
375
376/*
377 * Typedefs, etc...
378 */
379
380/* Primitive Types */
381typedef unsigned long ADDRESS; /* Memory/PCI address */
382typedef unsigned long IOADDRESS; /* Must be large enough for a pointer */
383typedef unsigned long PCITAG;
384
385/*
386 * PCI configuration space
387 */
388typedef struct pci_cfg_regs {
389 /* start of official PCI config space header */
390 union { /* Offset 0x0 - 0x3 */
391 CARD32 device_vendor;
392 struct {
393#if X_BYTE_ORDER == X_BIG_ENDIAN
394 CARD16 device;
395 CARD16 vendor;
396#else
397 CARD16 vendor;
398 CARD16 device;
399#endif
400 } dv;
401 } dv_id;
402
403 union { /* Offset 0x4 - 0x8 */
404 CARD32 status_command;
405 struct {
406#if X_BYTE_ORDER == X_BIG_ENDIAN
407 CARD16 status;
408 CARD16 command;
409#else
410 CARD16 command;
411 CARD16 status;
412#endif
413 } sc;
414 } stat_cmd;
415
416 union { /* Offset 0x8 - 0xb */
417 CARD32 class_revision;
418 struct {
419#if X_BYTE_ORDER == X_BIG_ENDIAN
420 CARD8 base_class;
421 CARD8 sub_class;
422 CARD8 prog_if;
423 CARD8 rev_id;
424#else
425 CARD8 rev_id;
426 CARD8 prog_if;
427 CARD8 sub_class;
428 CARD8 base_class;
429#endif
430 } cr;
431 } class_rev;
432
433 union { /* Offset 0xc - 0xf */
434 CARD32 bist_header_latency_cache;
435 struct {
436#if X_BYTE_ORDER == X_BIG_ENDIAN
437 CARD8 bist;
438 CARD8 header_type;
439 CARD8 latency_timer;
440 CARD8 cache_line_size;
441#else
442 CARD8 cache_line_size;
443 CARD8 latency_timer;
444 CARD8 header_type;
445 CARD8 bist;
446#endif
447 } bhlc;
448 } bhlc;
449 union { /* Offset 0x10 - 0x3b */
450 struct { /* header type 2 */
451 CARD32 cg_rsrvd1; /* 0x10 */
452#if X_BYTE_ORDER == X_BIG_ENDIAN
453 CARD16 secondary_status; /* 0x16 */
454 CARD16 cg_rsrvd2; /* 0x14 */
455
456 union {
457 CARD32 cg_bus_reg;
458 struct {
459 CARD8 latency_timer; /* 0x1b */
460 CARD8 subordinate_bus_number; /* 0x1a */
461 CARD8 cardbus_bus_number; /* 0x19 */
462 CARD8 primary_bus_number; /* 0x18 */
463 } cgbr;
464 } cgbr;
465#else
466 CARD16 cg_rsrvd2; /* 0x14 */
467 CARD16 secondary_status; /* 0x16 */
468
469 union {
470 CARD32 cg_bus_reg;
471 struct {
472 CARD8 primary_bus_number; /* 0x18 */
473 CARD8 cardbus_bus_number; /* 0x19 */
474 CARD8 subordinate_bus_number; /* 0x1a */
475 CARD8 latency_timer; /* 0x1b */
476 } cgbr;
477 } cgbr;
478#endif
479 CARD32 mem_base0; /* 0x1c */
480 CARD32 mem_limit0; /* 0x20 */
481 CARD32 mem_base1; /* 0x24 */
482 CARD32 mem_limit1; /* 0x28 */
483 CARD32 io_base0; /* 0x2c */
484 CARD32 io_limit0; /* 0x30 */
485 CARD32 io_base1; /* 0x34 */
486 CARD32 io_limit1; /* 0x38 */
487 } cg;
488 struct {
489 union { /* Offset 0x10 - 0x27 */
490 struct { /* header type 0 */
491 CARD32 dv_base0;
492 CARD32 dv_base1;
493 CARD32 dv_base2;
494 CARD32 dv_base3;
495 CARD32 dv_base4;
496 CARD32 dv_base5;
497 } dv;
498 struct { /* header type 1 */
499 CARD32 bg_rsrvd[2];
500#if X_BYTE_ORDER == X_BIG_ENDIAN
501 union {
502 CARD32 pp_bus_reg;
503 struct {
504 CARD8 secondary_latency_timer;
505 CARD8 subordinate_bus_number;
506 CARD8 secondary_bus_number;
507 CARD8 primary_bus_number;
508 } ppbr;
509 } ppbr;
510
511 CARD16 secondary_status;
512 CARD8 io_limit;
513 CARD8 io_base;
514
515 CARD16 mem_limit;
516 CARD16 mem_base;
517
518 CARD16 prefetch_mem_limit;
519 CARD16 prefetch_mem_base;
520#else
521 union {
522 CARD32 pp_bus_reg;
523 struct {
524 CARD8 primary_bus_number;
525 CARD8 secondary_bus_number;
526 CARD8 subordinate_bus_number;
527 CARD8 secondary_latency_timer;
528 } ppbr;
529 } ppbr;
530
531 CARD8 io_base;
532 CARD8 io_limit;
533 CARD16 secondary_status;
534
535 CARD16 mem_base;
536 CARD16 mem_limit;
537
538 CARD16 prefetch_mem_base;
539 CARD16 prefetch_mem_limit;
540#endif
541 } bg;
542 } bc;
543 union { /* Offset 0x28 - 0x2b */
544 CARD32 rsvd1;
545 CARD32 pftch_umem_base;
546 CARD32 cardbus_cis_ptr;
547 } um_c_cis;
548 union { /* Offset 0x2c - 0x2f */
549 CARD32 subsys_card_vendor;
550 CARD32 pftch_umem_limit;
551 CARD32 rsvd2;
552 struct {
553#if X_BYTE_ORDER == X_BIG_ENDIAN
554 CARD16 subsys_card;
555 CARD16 subsys_vendor;
556#else
557 CARD16 subsys_vendor;
558 CARD16 subsys_card;
559#endif
560 } ssys;
561 } um_ssys_id;
562 union { /* Offset 0x30 - 0x33 */
563 CARD32 baserom;
564 struct {
565#if X_BYTE_ORDER == X_BIG_ENDIAN
566 CARD16 io_ulimit;
567 CARD16 io_ubase;
568#else
569 CARD16 io_ubase;
570 CARD16 io_ulimit;
571#endif
572 } b_u_io;
573 } uio_rom;
574 struct {
575 CARD32 rsvd3; /* Offset 0x34 - 0x37 */
576 CARD32 rsvd4; /* Offset 0x38 - 0x3b */
577 } rsvd;
578 } cd;
579 } cx;
580 union { /* Offset 0x3c - 0x3f */
581 union { /* header type 0 */
582 CARD32 max_min_ipin_iline;
583 struct {
584#if X_BYTE_ORDER == X_BIG_ENDIAN
585 CARD8 max_lat;
586 CARD8 min_gnt;
587 CARD8 int_pin;
588 CARD8 int_line;
589#else
590 CARD8 int_line;
591 CARD8 int_pin;
592 CARD8 min_gnt;
593 CARD8 max_lat;
594#endif
595 } mmii;
596 } mmii;
597 struct { /* header type 1 */
598#if X_BYTE_ORDER == X_BIG_ENDIAN
599 CARD16 bridge_control; /* upper 8 bits reserved */
600 CARD8 rsvd2;
601 CARD8 rsvd1;
602#else
603 CARD8 rsvd1;
604 CARD8 rsvd2;
605 CARD16 bridge_control; /* upper 8 bits reserved */
606#endif
607 } bctrl;
608 } bm;
609 union { /* Offset 0x40 - 0xff */
610 CARD32 dwords[48];
611 CARD8 bytes[192];
612 } devspf;
613} pciCfgRegs;
614
615typedef union pci_cfg_spc {
616 pciCfgRegs regs;
617 CARD32 dwords[256/sizeof(CARD32)];
618 CARD8 bytes[256/sizeof(CARD8)];
619} pciCfgSpc;
620
621/*
622 * Data structure returned by xf86scanpci including contents of
623 * PCI config space header
624 */
625typedef struct pci_device {
626 PCITAG tag;
627 int busnum;
628 int devnum;
629 int funcnum;
630 pciCfgSpc cfgspc;
631 int basesize[7]; /* number of bits in base addr allocations */
632 Bool minBasesize;
633 CARD32 listed_class;
634 pointer businfo; /* pointer to secondary's bus info structure */
635 Bool fakeDevice; /* Device added by system chipset support */
636} pciDevice, *pciConfigPtr;
637
638typedef enum {
639 WRITE,
640 READ,
641 SET_BITS
642} pciFunc;
643
644typedef enum {
645 PCI_MEM,
646 PCI_MEM_SIZE,
647 PCI_MEM_SPARSE_BASE,
648 PCI_MEM_SPARSE_MASK,
649 PCI_IO,
650 PCI_IO_SIZE,
651 PCI_IO_SPARSE_BASE,
652 PCI_IO_SPARSE_MASK
653} PciAddrType;
654
655#define pci_device_vendor cfgspc.regs.dv_id.device_vendor
656#define pci_vendor cfgspc.regs.dv_id.dv.vendor
657#define pci_device cfgspc.regs.dv_id.dv.device
658#define pci_status_command cfgspc.regs.stat_cmd.status_command
659#define pci_command cfgspc.regs.stat_cmd.sc.command
660#define pci_status cfgspc.regs.stat_cmd.sc.status
661#define pci_class_revision cfgspc.regs.class_rev.class_revision
662#define pci_rev_id cfgspc.regs.class_rev.cr.rev_id
663#define pci_prog_if cfgspc.regs.class_rev.cr.prog_if
664#define pci_sub_class cfgspc.regs.class_rev.cr.sub_class
665#define pci_base_class cfgspc.regs.class_rev.cr.base_class
666#define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache
667#define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size
668#define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer
669#define pci_header_type cfgspc.regs.bhlc.bhlc.header_type
670#define pci_bist cfgspc.regs.bhlc.bhlc.bist
671#define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status
672#define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg
673#define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number
674#define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number
675#define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number
676#define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer
677#define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0
678#define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0
679#define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1
680#define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1
681#define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0
682#define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0
683#define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1
684#define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1
685#define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0
686#define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1
687#define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2
688#define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3
689#define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4
690#define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5
691#define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr
692#define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor
693#define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor
694#define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card
695#define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom
696#define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg
697#define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number
698#define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number
699#define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number
700#define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer
701#define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base
702#define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit
703#define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status
704#define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base
705#define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit
706#define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base
707#define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit
708#define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1
709#define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2
710#define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base
711#define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit
712#define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase
713#define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit
714#define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line
715#define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin
716#define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt
717#define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat
718#define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline
719#define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control
720#define pci_user_config cfgspc.regs.devspf.dwords[0]
721#define pci_user_config_0 cfgspc.regs.devspf.bytes[0]
722#define pci_user_config_1 cfgspc.regs.devspf.bytes[1]
723#define pci_user_config_2 cfgspc.regs.devspf.bytes[2]
724#define pci_user_config_3 cfgspc.regs.devspf.bytes[3]
725
726typedef enum {
727 PCI_BIOS_PC = 0,
728 PCI_BIOS_OPEN_FIRMARE,
729 PCI_BIOS_HP_PA_RISC,
730 PCI_BIOS_OTHER
731} PciBiosType;
732
733/* Public PCI access functions */
734void pciInit(void);
735PCITAG pciFindFirst(CARD32 id, CARD32 mask);
736PCITAG pciFindNext(void);
737CARD32 pciReadLong(PCITAG tag, int offset);
738CARD16 pciReadWord(PCITAG tag, int offset);
739CARD8 pciReadByte(PCITAG tag, int offset);
740void pciWriteLong(PCITAG tag, int offset, CARD32 val);
741void pciWriteWord(PCITAG tag, int offset, CARD16 val);
742void pciWriteByte(PCITAG tag, int offset, CARD8 val);
743void pciSetBitsLong(PCITAG tag, int offset, CARD32 mask, CARD32 val);
744void pciSetBitsByte(PCITAG tag, int offset, CARD8 mask, CARD8 val);
745pointer pciLongFunc(PCITAG tag, pciFunc func);
746ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
747ADDRESS pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
748PCITAG pciTag(int busnum, int devnum, int funcnum);
749int pciGetBaseSize(PCITAG tag, int indx, Bool destructive, Bool *min);
750CARD32 pciCheckForBrokenBase(PCITAG tag,int basereg);
751pointer xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag,
752 ADDRESS Base, unsigned long Size);
753int xf86ReadPciBIOS(unsigned long Offset, PCITAG Tag, int basereg,
754 unsigned char *Buf, int Len);
755int xf86ReadPciBIOSByType(unsigned long Offset, PCITAG Tag,
756 int basereg, unsigned char *Buf,
757 int Len, PciBiosType Type);
758int xf86GetAvailablePciBIOSTypes(PCITAG Tag, int basereg,
759 PciBiosType *Buf);
760pciConfigPtr *xf86scanpci(int flags);
761
762extern int pciNumBuses;
763
764/* Domain access functions. Some of these probably shouldn't be public */
765int xf86GetPciDomain(PCITAG tag);
766pointer xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag,
767 ADDRESS Base, unsigned long Size);
768IOADDRESS xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag,
769 IOADDRESS Base, unsigned long Size);
770int xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len,
771 unsigned char *Buf);
772
773typedef enum {
774 ROM_BASE_PRESET = -2,
775 ROM_BASE_BIOS,
776 ROM_BASE_MEM0 = 0,
777 ROM_BASE_MEM1,
778 ROM_BASE_MEM2,
779 ROM_BASE_MEM3,
780 ROM_BASE_MEM4,
781 ROM_BASE_MEM5,
782 ROM_BASE_FIND
783} romBaseSource;
784
785#endif /* _XF86PCI_H */
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