x86.h@ 81404

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2019 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.alldomusa.eu.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef IPRT_INCLUDED_x86_h
29	#define IPRT_INCLUDED_x86_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <iprt/types.h>
36	# include <iprt/assert.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	#endif
40
41	/* Workaround for Solaris sys/regset.h defining CS, DS */
42	#ifdef RT_OS_SOLARIS
43	# undef CS
44	# undef DS
45	#endif
46
47	/** @defgroup grp_rt_x86 x86 Types and Definitions
48	* @ingroup grp_rt
49	* @{
50	*/
51
52	#ifndef VBOX_FOR_DTRACE_LIB
53	/**
54	* EFLAGS Bits.
55	*/
56	typedef struct X86EFLAGSBITS
57	{
58	/** Bit 0 - CF - Carry flag - Status flag. */
59	unsigned u1CF : 1;
60	/** Bit 1 - 1 - Reserved flag. */
61	unsigned u1Reserved0 : 1;
62	/** Bit 2 - PF - Parity flag - Status flag. */
63	unsigned u1PF : 1;
64	/** Bit 3 - 0 - Reserved flag. */
65	unsigned u1Reserved1 : 1;
66	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67	unsigned u1AF : 1;
68	/** Bit 5 - 0 - Reserved flag. */
69	unsigned u1Reserved2 : 1;
70	/** Bit 6 - ZF - Zero flag - Status flag. */
71	unsigned u1ZF : 1;
72	/** Bit 7 - SF - Signed flag - Status flag. */
73	unsigned u1SF : 1;
74	/** Bit 8 - TF - Trap flag - System flag. */
75	unsigned u1TF : 1;
76	/** Bit 9 - IF - Interrupt flag - System flag. */
77	unsigned u1IF : 1;
78	/** Bit 10 - DF - Direction flag - Control flag. */
79	unsigned u1DF : 1;
80	/** Bit 11 - OF - Overflow flag - Status flag. */
81	unsigned u1OF : 1;
82	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83	unsigned u2IOPL : 2;
84	/** Bit 14 - NT - Nested task flag - System flag. */
85	unsigned u1NT : 1;
86	/** Bit 15 - 0 - Reserved flag. */
87	unsigned u1Reserved3 : 1;
88	/** Bit 16 - RF - Resume flag - System flag. */
89	unsigned u1RF : 1;
90	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
91	unsigned u1VM : 1;
92	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93	unsigned u1AC : 1;
94	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95	unsigned u1VIF : 1;
96	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97	unsigned u1VIP : 1;
98	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99	unsigned u1ID : 1;
100	/** Bit 22-31 - 0 - Reserved flag. */
101	unsigned u10Reserved4 : 10;
102	} X86EFLAGSBITS;
103	/** Pointer to EFLAGS bits. */
104	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105	/** Pointer to const EFLAGS bits. */
106	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107	#endif /* !VBOX_FOR_DTRACE_LIB */
108
109	/**
110	* EFLAGS.
111	*/
112	typedef union X86EFLAGS
113	{
114	/** The plain unsigned view. */
115	uint32_t u;
116	#ifndef VBOX_FOR_DTRACE_LIB
117	/** The bitfield view. */
118	X86EFLAGSBITS Bits;
119	#endif
120	/** The 8-bit view. */
121	uint8_t au8[4];
122	/** The 16-bit view. */
123	uint16_t au16[2];
124	/** The 32-bit view. */
125	uint32_t au32[1];
126	/** The 32-bit view. */
127	uint32_t u32;
128	} X86EFLAGS;
129	/** Pointer to EFLAGS. */
130	typedef X86EFLAGS *PX86EFLAGS;
131	/** Pointer to const EFLAGS. */
132	typedef const X86EFLAGS *PCX86EFLAGS;
133
134	/**
135	* RFLAGS (32 upper bits are reserved).
136	*/
137	typedef union X86RFLAGS
138	{
139	/** The plain unsigned view. */
140	uint64_t u;
141	#ifndef VBOX_FOR_DTRACE_LIB
142	/** The bitfield view. */
143	X86EFLAGSBITS Bits;
144	#endif
145	/** The 8-bit view. */
146	uint8_t au8[8];
147	/** The 16-bit view. */
148	uint16_t au16[4];
149	/** The 32-bit view. */
150	uint32_t au32[2];
151	/** The 64-bit view. */
152	uint64_t au64[1];
153	/** The 64-bit view. */
154	uint64_t u64;
155	} X86RFLAGS;
156	/** Pointer to RFLAGS. */
157	typedef X86RFLAGS *PX86RFLAGS;
158	/** Pointer to const RFLAGS. */
159	typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162	/** @name EFLAGS
163	* @{
164	*/
165	/** Bit 0 - CF - Carry flag - Status flag. */
166	#define X86_EFL_CF RT_BIT_32(0)
167	#define X86_EFL_CF_BIT 0
168	/** Bit 1 - Reserved, reads as 1. */
169	#define X86_EFL_1 RT_BIT_32(1)
170	/** Bit 2 - PF - Parity flag - Status flag. */
171	#define X86_EFL_PF RT_BIT_32(2)
172	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173	#define X86_EFL_AF RT_BIT_32(4)
174	#define X86_EFL_AF_BIT 4
175	/** Bit 6 - ZF - Zero flag - Status flag. */
176	#define X86_EFL_ZF RT_BIT_32(6)
177	#define X86_EFL_ZF_BIT 6
178	/** Bit 7 - SF - Signed flag - Status flag. */
179	#define X86_EFL_SF RT_BIT_32(7)
180	#define X86_EFL_SF_BIT 7
181	/** Bit 8 - TF - Trap flag - System flag. */
182	#define X86_EFL_TF RT_BIT_32(8)
183	/** Bit 9 - IF - Interrupt flag - System flag. */
184	#define X86_EFL_IF RT_BIT_32(9)
185	/** Bit 10 - DF - Direction flag - Control flag. */
186	#define X86_EFL_DF RT_BIT_32(10)
187	/** Bit 11 - OF - Overflow flag - Status flag. */
188	#define X86_EFL_OF RT_BIT_32(11)
189	#define X86_EFL_OF_BIT 11
190	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
192	/** Bit 14 - NT - Nested task flag - System flag. */
193	#define X86_EFL_NT RT_BIT_32(14)
194	/** Bit 16 - RF - Resume flag - System flag. */
195	#define X86_EFL_RF RT_BIT_32(16)
196	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197	#define X86_EFL_VM RT_BIT_32(17)
198	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199	#define X86_EFL_AC RT_BIT_32(18)
200	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201	#define X86_EFL_VIF RT_BIT_32(19)
202	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203	#define X86_EFL_VIP RT_BIT_32(20)
204	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205	#define X86_EFL_ID RT_BIT_32(21)
206	/** All live bits. */
207	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208	/** Read as 1 bits. */
209	#define X86_EFL_RA1_MASK RT_BIT_32(1)
210	/** IOPL shift. */
211	#define X86_EFL_IOPL_SHIFT 12
212	/** The IOPL level from the flags. */
213	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214	/** Bits restored by popf */
215	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
216	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
217	/** Bits restored by popf */
218	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
219	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
220	/** The status bits commonly updated by arithmetic instructions. */
221	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
222	/** @} */
223
224
225	/** CPUID Feature information - ECX.
226	* CPUID query with EAX=1.
227	*/
228	#ifndef VBOX_FOR_DTRACE_LIB
229	typedef struct X86CPUIDFEATECX
230	{
231	/** Bit 0 - SSE3 - Supports SSE3 or not. */
232	unsigned u1SSE3 : 1;
233	/** Bit 1 - PCLMULQDQ. */
234	unsigned u1PCLMULQDQ : 1;
235	/** Bit 2 - DS Area 64-bit layout. */
236	unsigned u1DTE64 : 1;
237	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238	unsigned u1Monitor : 1;
239	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240	unsigned u1CPLDS : 1;
241	/** Bit 5 - VMX - Virtual Machine Technology. */
242	unsigned u1VMX : 1;
243	/** Bit 6 - SMX: Safer Mode Extensions. */
244	unsigned u1SMX : 1;
245	/** Bit 7 - EST - Enh. SpeedStep Tech. */
246	unsigned u1EST : 1;
247	/** Bit 8 - TM2 - Terminal Monitor 2. */
248	unsigned u1TM2 : 1;
249	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250	unsigned u1SSSE3 : 1;
251	/** Bit 10 - CNTX-ID - L1 Context ID. */
252	unsigned u1CNTXID : 1;
253	/** Bit 11 - Reserved. */
254	unsigned u1Reserved1 : 1;
255	/** Bit 12 - FMA. */
256	unsigned u1FMA : 1;
257	/** Bit 13 - CX16 - CMPXCHG16B. */
258	unsigned u1CX16 : 1;
259	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260	unsigned u1TPRUpdate : 1;
261	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262	unsigned u1PDCM : 1;
263	/** Bit 16 - Reserved. */
264	unsigned u1Reserved2 : 1;
265	/** Bit 17 - PCID - Process-context identifiers. */
266	unsigned u1PCID : 1;
267	/** Bit 18 - Direct Cache Access. */
268	unsigned u1DCA : 1;
269	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270	unsigned u1SSE4_1 : 1;
271	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272	unsigned u1SSE4_2 : 1;
273	/** Bit 21 - x2APIC. */
274	unsigned u1x2APIC : 1;
275	/** Bit 22 - MOVBE - Supports MOVBE. */
276	unsigned u1MOVBE : 1;
277	/** Bit 23 - POPCNT - Supports POPCNT. */
278	unsigned u1POPCNT : 1;
279	/** Bit 24 - TSC-Deadline. */
280	unsigned u1TSCDEADLINE : 1;
281	/** Bit 25 - AES. */
282	unsigned u1AES : 1;
283	/** Bit 26 - XSAVE - Supports XSAVE. */
284	unsigned u1XSAVE : 1;
285	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286	unsigned u1OSXSAVE : 1;
287	/** Bit 28 - AVX - Supports AVX instruction extensions. */
288	unsigned u1AVX : 1;
289	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290	unsigned u1F16C : 1;
291	/** Bit 30 - RDRAND - Supports RDRAND. */
292	unsigned u1RDRAND : 1;
293	/** Bit 31 - Hypervisor present (we're a guest). */
294	unsigned u1HVP : 1;
295	} X86CPUIDFEATECX;
296	#else /* VBOX_FOR_DTRACE_LIB */
297	typedef uint32_t X86CPUIDFEATECX;
298	#endif /* VBOX_FOR_DTRACE_LIB */
299	/** Pointer to CPUID Feature Information - ECX. */
300	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301	/** Pointer to const CPUID Feature Information - ECX. */
302	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305	/** CPUID Feature Information - EDX.
306	* CPUID query with EAX=1.
307	*/
308	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309	typedef struct X86CPUIDFEATEDX
310	{
311	/** Bit 0 - FPU - x87 FPU on Chip. */
312	unsigned u1FPU : 1;
313	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314	unsigned u1VME : 1;
315	/** Bit 2 - DE - Debugging extensions. */
316	unsigned u1DE : 1;
317	/** Bit 3 - PSE - Page Size Extension. */
318	unsigned u1PSE : 1;
319	/** Bit 4 - TSC - Time Stamp Counter. */
320	unsigned u1TSC : 1;
321	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322	unsigned u1MSR : 1;
323	/** Bit 6 - PAE - Physical Address Extension. */
324	unsigned u1PAE : 1;
325	/** Bit 7 - MCE - Machine Check Exception. */
326	unsigned u1MCE : 1;
327	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
328	unsigned u1CX8 : 1;
329	/** Bit 9 - APIC - APIC On-Chip. */
330	unsigned u1APIC : 1;
331	/** Bit 10 - Reserved. */
332	unsigned u1Reserved1 : 1;
333	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334	unsigned u1SEP : 1;
335	/** Bit 12 - MTRR - Memory Type Range Registers. */
336	unsigned u1MTRR : 1;
337	/** Bit 13 - PGE - PTE Global Bit. */
338	unsigned u1PGE : 1;
339	/** Bit 14 - MCA - Machine Check Architecture. */
340	unsigned u1MCA : 1;
341	/** Bit 15 - CMOV - Conditional Move Instructions. */
342	unsigned u1CMOV : 1;
343	/** Bit 16 - PAT - Page Attribute Table. */
344	unsigned u1PAT : 1;
345	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346	unsigned u1PSE36 : 1;
347	/** Bit 18 - PSN - Processor Serial Number. */
348	unsigned u1PSN : 1;
349	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
350	unsigned u1CLFSH : 1;
351	/** Bit 20 - Reserved. */
352	unsigned u1Reserved2 : 1;
353	/** Bit 21 - DS - Debug Store. */
354	unsigned u1DS : 1;
355	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356	unsigned u1ACPI : 1;
357	/** Bit 23 - MMX - Intel MMX 'Technology'. */
358	unsigned u1MMX : 1;
359	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360	unsigned u1FXSR : 1;
361	/** Bit 25 - SSE - SSE Support. */
362	unsigned u1SSE : 1;
363	/** Bit 26 - SSE2 - SSE2 Support. */
364	unsigned u1SSE2 : 1;
365	/** Bit 27 - SS - Self Snoop. */
366	unsigned u1SS : 1;
367	/** Bit 28 - HTT - Hyper-Threading Technology. */
368	unsigned u1HTT : 1;
369	/** Bit 29 - TM - Thermal Monitor. */
370	unsigned u1TM : 1;
371	/** Bit 30 - Reserved - . */
372	unsigned u1Reserved3 : 1;
373	/** Bit 31 - PBE - Pending Break Enabled. */
374	unsigned u1PBE : 1;
375	} X86CPUIDFEATEDX;
376	#else /* VBOX_FOR_DTRACE_LIB */
377	typedef uint32_t X86CPUIDFEATEDX;
378	#endif /* VBOX_FOR_DTRACE_LIB */
379	/** Pointer to CPUID Feature Information - EDX. */
380	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381	/** Pointer to const CPUID Feature Information - EDX. */
382	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384	/** @name CPUID Vendor information.
385	* CPUID query with EAX=0.
386	* @{
387	*/
388	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403	/** @} */
404
405
406	/** @name CPUID Feature information.
407	* CPUID query with EAX=1.
408	* @{
409	*/
410	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
411	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
412	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
413	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
414	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
415	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
416	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
417	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
418	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
419	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
420	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
421	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
422	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
423	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
424	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
425	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
426	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
427	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
428	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
429	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
430	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
431	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
432	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
433	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
434	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
435	/** ECX Bit 12 - FMA. */
436	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
437	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
438	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
439	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
440	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
441	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
442	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
443	/** ECX Bit 17 - PCID - Process-context identifiers. */
444	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
445	/** ECX Bit 18 - DCA - Direct Cache Access. */
446	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
447	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
448	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
449	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
450	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
451	/** ECX Bit 21 - x2APIC support. */
452	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
453	/** ECX Bit 22 - MOVBE instruction. */
454	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
455	/** ECX Bit 23 - POPCNT instruction. */
456	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
457	/** ECX Bir 24 - TSC-Deadline. */
458	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
459	/** ECX Bit 25 - AES instructions. */
460	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
461	/** ECX Bit 26 - XSAVE instruction. */
462	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
463	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
464	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
465	/** ECX Bit 28 - AVX. */
466	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
467	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
468	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
469	/** ECX Bit 30 - RDRAND instruction. */
470	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
471	/** ECX Bit 31 - Hypervisor Present (software only). */
472	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
473
474
475	/** Bit 0 - FPU - x87 FPU on Chip. */
476	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
477	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
478	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
479	/** Bit 2 - DE - Debugging extensions. */
480	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
481	/** Bit 3 - PSE - Page Size Extension. */
482	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
483	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
484	/** Bit 4 - TSC - Time Stamp Counter. */
485	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
486	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
487	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
488	/** Bit 6 - PAE - Physical Address Extension. */
489	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
490	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
491	/** Bit 7 - MCE - Machine Check Exception. */
492	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
493	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
494	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
495	/** Bit 9 - APIC - APIC On-Chip. */
496	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
497	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
498	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
499	/** Bit 12 - MTRR - Memory Type Range Registers. */
500	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
501	/** Bit 13 - PGE - PTE Global Bit. */
502	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
503	/** Bit 14 - MCA - Machine Check Architecture. */
504	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
505	/** Bit 15 - CMOV - Conditional Move Instructions. */
506	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
507	/** Bit 16 - PAT - Page Attribute Table. */
508	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
509	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
510	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
511	/** Bit 18 - PSN - Processor Serial Number. */
512	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
513	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
514	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
515	/** Bit 21 - DS - Debug Store. */
516	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
517	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
518	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
519	/** Bit 23 - MMX - Intel MMX Technology. */
520	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
521	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
522	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
523	/** Bit 25 - SSE - SSE Support. */
524	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
525	/** Bit 26 - SSE2 - SSE2 Support. */
526	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
527	/** Bit 27 - SS - Self Snoop. */
528	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
529	/** Bit 28 - HTT - Hyper-Threading Technology. */
530	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
531	/** Bit 29 - TM - Therm. Monitor. */
532	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
533	/** Bit 31 - PBE - Pending Break Enabled. */
534	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
535	/** @} */
536
537	/** @name CPUID mwait/monitor information.
538	* CPUID query with EAX=5.
539	* @{
540	*/
541	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
542	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
543	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
544	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
545	/** @} */
546
547
548	/** @name CPUID Structured Extended Feature information.
549	* CPUID query with EAX=7.
550	* @{
551	*/
552	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
553	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
554	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
555	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
556	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
557	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
558	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
559	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
560	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
561	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
562	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
563	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
564	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
565	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
566	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
567	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
568	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
569	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
570	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
571	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
572	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
573	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
574	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
575	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
576	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
577	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
578	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
579	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
580	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
581	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
582	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
583	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
584	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
585	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
586	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
588	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
589	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
590	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
591	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
592	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
593	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
594	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
596	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
597	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
598	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
599	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
600	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
601	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
602	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
603	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
604
605	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
606	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
607	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
608	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
609	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
610	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
611	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
612	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
613	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
614	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
615	/** ECX Bit 22 - RDPID - Support pread process ID. */
616	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
617	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
618	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
619
620	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
621	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
622	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
623	* IBPB command in IA32_PRED_CMD. */
624	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
625	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
626	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
627	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
628	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
629	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
630	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
631
632	/** @} */
633
634
635	/** @name CPUID Extended Feature information.
636	* CPUID query with EAX=0x80000001.
637	* @{
638	*/
639	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
640	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
641
642	/** EDX Bit 11 - SYSCALL/SYSRET. */
643	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
644	/** EDX Bit 20 - No-Execute/Execute-Disable. */
645	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
646	/** EDX Bit 26 - 1 GB large page. */
647	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
648	/** EDX Bit 27 - RDTSCP. */
649	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
650	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
651	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
652	/** @}*/
653
654	/** @name CPUID AMD Feature information.
655	* CPUID query with EAX=0x80000001.
656	* @{
657	*/
658	/** Bit 0 - FPU - x87 FPU on Chip. */
659	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
660	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
661	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
662	/** Bit 2 - DE - Debugging extensions. */
663	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
664	/** Bit 3 - PSE - Page Size Extension. */
665	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
666	/** Bit 4 - TSC - Time Stamp Counter. */
667	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
668	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
669	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
670	/** Bit 6 - PAE - Physical Address Extension. */
671	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
672	/** Bit 7 - MCE - Machine Check Exception. */
673	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
674	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
675	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
676	/** Bit 9 - APIC - APIC On-Chip. */
677	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
678	/** Bit 12 - MTRR - Memory Type Range Registers. */
679	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
680	/** Bit 13 - PGE - PTE Global Bit. */
681	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
682	/** Bit 14 - MCA - Machine Check Architecture. */
683	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
684	/** Bit 15 - CMOV - Conditional Move Instructions. */
685	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
686	/** Bit 16 - PAT - Page Attribute Table. */
687	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
688	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
689	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
690	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
691	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
692	/** Bit 23 - MMX - Intel MMX Technology. */
693	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
694	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
695	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
696	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
697	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
698	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
699	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
700	/** Bit 31 - 3DNOW - AMD 3DNow. */
701	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
702
703	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
704	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
705	/** Bit 2 - SVM - AMD VM extensions. */
706	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
707	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
708	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
709	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
710	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
711	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
712	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
713	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
714	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
715	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
716	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
717	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
718	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
719	/** Bit 9 - OSVW - AMD OS visible workaround. */
720	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
721	/** Bit 10 - IBS - Instruct based sampling. */
722	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
723	/** Bit 11 - XOP - Extended operation support (see APM6). */
724	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
725	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
726	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
727	/** Bit 13 - WDT - AMD Watchdog timer support. */
728	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
729	/** Bit 15 - LWP - Lightweight profiling support. */
730	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
731	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
732	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
733	/** Bit 19 - NodeId - Indicates support for
734	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
735	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
736	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
737	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
738	/** Bit 22 - TopologyExtensions - . */
739	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
740	/** @} */
741
742
743	/** @name CPUID AMD Feature information.
744	* CPUID query with EAX=0x80000007.
745	* @{
746	*/
747	/** Bit 0 - TS - Temperature Sensor. */
748	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
749	/** Bit 1 - FID - Frequency ID Control. */
750	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
751	/** Bit 2 - VID - Voltage ID Control. */
752	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
753	/** Bit 3 - TTP - THERMTRIP. */
754	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
755	/** Bit 4 - TM - Hardware Thermal Control. */
756	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
757	/** Bit 5 - STC - Software Thermal Control. */
758	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
759	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
760	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
761	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
762	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
763	/** Bit 8 - TSCINVAR - TSC Invariant. */
764	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
765	/** Bit 9 - CPB - TSC Invariant. */
766	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
767	/** Bit 10 - EffFreqRO - MPERF/APERF. */
768	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
769	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
770	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
771	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
772	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
773	/** @} */
774
775
776	/** @name CPUID AMD extended feature extensions ID (EBX).
777	* CPUID query with EAX=0x80000008.
778	* @{
779	*/
780	/** Bit 0 - CLZERO - Clear zero instruction. */
781	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
782	/** Bit 1 - IRPerf - Instructions retired count support. */
783	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
784	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
785	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
786	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
787	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
788	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
789	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
790	/* AMD pipeline length: 9 feature bits ;-) */
791	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
792	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
793	/** @} */
794
795
796	/** @name CPUID AMD SVM Feature information.
797	* CPUID query with EAX=0x8000000a.
798	* @{
799	*/
800	/** Bit 0 - NP - Nested Paging supported. */
801	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
802	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
803	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
804	/** Bit 2 - SVML - SVM locking bit supported. */
805	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
806	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
807	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
808	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
809	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
810	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
811	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
812	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
813	* VMCB.TLB_Control is supported. */
814	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
815	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
816	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
817	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
818	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
819	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
820	* intercept filter cycle count threshold. */
821	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
822	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
823	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
824	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
825	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
826	/** Bit 16 - VGIF - Supports virtualized GIF. */
827	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
828	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
829	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
830
831	/** @} */
832
833
834	/** @name CR0
835	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
836	* reserved flags.
837	* @{ */
838	/** Bit 0 - PE - Protection Enabled */
839	#define X86_CR0_PE RT_BIT_32(0)
840	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
841	/** Bit 1 - MP - Monitor Coprocessor */
842	#define X86_CR0_MP RT_BIT_32(1)
843	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
844	/** Bit 2 - EM - Emulation. */
845	#define X86_CR0_EM RT_BIT_32(2)
846	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
847	/** Bit 3 - TS - Task Switch. */
848	#define X86_CR0_TS RT_BIT_32(3)
849	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
850	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
851	#define X86_CR0_ET RT_BIT_32(4)
852	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
853	/** Bit 5 - NE - Numeric error (486+). */
854	#define X86_CR0_NE RT_BIT_32(5)
855	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
856	/** Bit 16 - WP - Write Protect (486+). */
857	#define X86_CR0_WP RT_BIT_32(16)
858	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
859	/** Bit 18 - AM - Alignment Mask (486+). */
860	#define X86_CR0_AM RT_BIT_32(18)
861	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
862	/** Bit 29 - NW - Not Write-though (486+). */
863	#define X86_CR0_NW RT_BIT_32(29)
864	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
865	/** Bit 30 - WP - Cache Disable (486+). */
866	#define X86_CR0_CD RT_BIT_32(30)
867	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
868	/** Bit 31 - PG - Paging. */
869	#define X86_CR0_PG RT_BIT_32(31)
870	#define X86_CR0_PAGING RT_BIT_32(31)
871	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
872	/** @} */
873
874
875	/** @name CR3
876	* @{ */
877	/** Bit 3 - PWT - Page-level Writes Transparent. */
878	#define X86_CR3_PWT RT_BIT_32(3)
879	/** Bit 4 - PCD - Page-level Cache Disable. */
880	#define X86_CR3_PCD RT_BIT_32(4)
881	/** Bits 12-31 - - Page directory page number. */
882	#define X86_CR3_PAGE_MASK (0xfffff000)
883	/** Bits 5-31 - - PAE Page directory page number. */
884	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
885	/** Bits 12-51 - - AMD64 Page directory page number. */
886	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
887	/** @} */
888
889
890	/** @name CR4
891	* @{ */
892	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
893	#define X86_CR4_VME RT_BIT_32(0)
894	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
895	#define X86_CR4_PVI RT_BIT_32(1)
896	/** Bit 2 - TSD - Time Stamp Disable. */
897	#define X86_CR4_TSD RT_BIT_32(2)
898	/** Bit 3 - DE - Debugging Extensions. */
899	#define X86_CR4_DE RT_BIT_32(3)
900	/** Bit 4 - PSE - Page Size Extension. */
901	#define X86_CR4_PSE RT_BIT_32(4)
902	/** Bit 5 - PAE - Physical Address Extension. */
903	#define X86_CR4_PAE RT_BIT_32(5)
904	/** Bit 6 - MCE - Machine-Check Enable. */
905	#define X86_CR4_MCE RT_BIT_32(6)
906	/** Bit 7 - PGE - Page Global Enable. */
907	#define X86_CR4_PGE RT_BIT_32(7)
908	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
909	#define X86_CR4_PCE RT_BIT_32(8)
910	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
911	#define X86_CR4_OSFXSR RT_BIT_32(9)
912	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
913	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
914	/** Bit 13 - VMXE - VMX mode is enabled. */
915	#define X86_CR4_VMXE RT_BIT_32(13)
916	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
917	#define X86_CR4_SMXE RT_BIT_32(14)
918	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
919	#define X86_CR4_FSGSBASE RT_BIT_32(16)
920	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
921	#define X86_CR4_PCIDE RT_BIT_32(17)
922	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
923	* extended states. */
924	#define X86_CR4_OSXSAVE RT_BIT_32(18)
925	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
926	#define X86_CR4_SMEP RT_BIT_32(20)
927	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
928	#define X86_CR4_SMAP RT_BIT_32(21)
929	/** Bit 22 - PKE - Protection Key Enable. */
930	#define X86_CR4_PKE RT_BIT_32(22)
931	/** @} */
932
933
934	/** @name DR6
935	* @{ */
936	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
937	#define X86_DR6_B0 RT_BIT_32(0)
938	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
939	#define X86_DR6_B1 RT_BIT_32(1)
940	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
941	#define X86_DR6_B2 RT_BIT_32(2)
942	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
943	#define X86_DR6_B3 RT_BIT_32(3)
944	/** Mask of all the Bx bits. */
945	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
946	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
947	#define X86_DR6_BD RT_BIT_32(13)
948	/** Bit 14 - BS - Single step */
949	#define X86_DR6_BS RT_BIT_32(14)
950	/** Bit 15 - BT - Task switch. (TSS T bit.) */
951	#define X86_DR6_BT RT_BIT_32(15)
952	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
953	#define X86_DR6_RTM RT_BIT_32(16)
954	/** Value of DR6 after powerup/reset. */
955	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
956	/** Bits which must be 1s in DR6. */
957	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
958	/** Bits which must be 1s in DR6, when RTM is supported. */
959	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
960	/** Bits which must be 0s in DR6. */
961	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
962	/** Bits which must be 0s on writes to DR6. */
963	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
964	/** @} */
965
966	/** Get the DR6.Bx bit for a the given breakpoint. */
967	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
968
969
970	/** @name DR7
971	* @{ */
972	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
973	#define X86_DR7_L0 RT_BIT_32(0)
974	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
975	#define X86_DR7_G0 RT_BIT_32(1)
976	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
977	#define X86_DR7_L1 RT_BIT_32(2)
978	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
979	#define X86_DR7_G1 RT_BIT_32(3)
980	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
981	#define X86_DR7_L2 RT_BIT_32(4)
982	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
983	#define X86_DR7_G2 RT_BIT_32(5)
984	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
985	#define X86_DR7_L3 RT_BIT_32(6)
986	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
987	#define X86_DR7_G3 RT_BIT_32(7)
988	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
989	#define X86_DR7_LE RT_BIT_32(8)
990	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
991	#define X86_DR7_GE RT_BIT_32(9)
992
993	/** L0, L1, L2, and L3. */
994	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
995	/** L0, L1, L2, and L3. */
996	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
997
998	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
999	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1000	#define X86_DR7_RTM RT_BIT_32(11)
1001	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1002	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1003	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1004	* instruction is executed.
1005	* @see http://www.rcollins.org/secrets/DR7.html */
1006	#define X86_DR7_ICE_IR RT_BIT_32(12)
1007	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1008	* any DR register is accessed. */
1009	#define X86_DR7_GD RT_BIT_32(13)
1010	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1011	* Pentium. */
1012	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1013	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1014	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1015	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1016	#define X86_DR7_RW0_MASK (3 << 16)
1017	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1018	#define X86_DR7_LEN0_MASK (3 << 18)
1019	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1020	#define X86_DR7_RW1_MASK (3 << 20)
1021	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1022	#define X86_DR7_LEN1_MASK (3 << 22)
1023	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1024	#define X86_DR7_RW2_MASK (3 << 24)
1025	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1026	#define X86_DR7_LEN2_MASK (3 << 26)
1027	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1028	#define X86_DR7_RW3_MASK (3 << 28)
1029	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1030	#define X86_DR7_LEN3_MASK (3 << 30)
1031
1032	/** Bits which reads as 1s. */
1033	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1034	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1035	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1036	/** Bits which must be 0s when writing to DR7. */
1037	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1038
1039	/** Calcs the L bit of Nth breakpoint.
1040	* @param iBp The breakpoint number [0..3].
1041	*/
1042	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1043
1044	/** Calcs the G bit of Nth breakpoint.
1045	* @param iBp The breakpoint number [0..3].
1046	*/
1047	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1048
1049	/** Calcs the L and G bits of Nth breakpoint.
1050	* @param iBp The breakpoint number [0..3].
1051	*/
1052	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1053
1054	/** @name Read/Write values.
1055	* @{ */
1056	/** Break on instruction fetch only. */
1057	#define X86_DR7_RW_EO UINT32_C(0)
1058	/** Break on write only. */
1059	#define X86_DR7_RW_WO UINT32_C(1)
1060	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1061	#define X86_DR7_RW_IO UINT32_C(2)
1062	/** Break on read or write (but not instruction fetches). */
1063	#define X86_DR7_RW_RW UINT32_C(3)
1064	/** @} */
1065
1066	/** Shifts a X86_DR7_RW_* value to its right place.
1067	* @param iBp The breakpoint number [0..3].
1068	* @param fRw One of the X86_DR7_RW_* value.
1069	*/
1070	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1071
1072	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1073	* one of the X86_DR7_RW_XXX constants).
1074	*
1075	* @returns X86_DR7_RW_XXX
1076	* @param uDR7 DR7 value
1077	* @param iBp The breakpoint number [0..3].
1078	*/
1079	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1080
1081	/** R/W0, R/W1, R/W2, and R/W3. */
1082	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1083
1084	#ifndef VBOX_FOR_DTRACE_LIB
1085	/** Checks if there are any I/O breakpoint types configured in the RW
1086	* registers. Does NOT check if these are enabled, sorry. */
1087	# define X86_DR7_ANY_RW_IO(uDR7) \
1088	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1089	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1090	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1091	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1092	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1093	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1094	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1095	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1096	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1097	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1098	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1099	#endif /* !VBOX_FOR_DTRACE_LIB */
1100
1101	/** @name Length values.
1102	* @{ */
1103	#define X86_DR7_LEN_BYTE UINT32_C(0)
1104	#define X86_DR7_LEN_WORD UINT32_C(1)
1105	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1106	#define X86_DR7_LEN_DWORD UINT32_C(3)
1107	/** @} */
1108
1109	/** Shifts a X86_DR7_LEN_* value to its right place.
1110	* @param iBp The breakpoint number [0..3].
1111	* @param cb One of the X86_DR7_LEN_* values.
1112	*/
1113	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1114
1115	/** Fetch the breakpoint length bits from the DR7 value.
1116	* @param uDR7 DR7 value
1117	* @param iBp The breakpoint number [0..3].
1118	*/
1119	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1120
1121	/** Mask used to check if any breakpoints are enabled. */
1122	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1123
1124	/** LEN0, LEN1, LEN2, and LEN3. */
1125	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1126	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1127	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1128
1129	/** Value of DR7 after powerup/reset. */
1130	#define X86_DR7_INIT_VAL 0x400
1131	/** @} */
1132
1133
1134	/** @name Machine Specific Registers
1135	* @{
1136	*/
1137	/** Machine check address register (P5). */
1138	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1139	/** Machine check type register (P5). */
1140	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1141	/** Time Stamp Counter. */
1142	#define MSR_IA32_TSC 0x10
1143	#define MSR_IA32_CESR UINT32_C(0x00000011)
1144	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1145	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1146
1147	#define MSR_IA32_PLATFORM_ID 0x17
1148
1149	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1150	# define MSR_IA32_APICBASE 0x1b
1151	/** Local APIC enabled. */
1152	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1153	/** X2APIC enabled (requires the EN bit to be set). */
1154	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1155	/** The processor is the boot strap processor (BSP). */
1156	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1157	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1158	* width. */
1159	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1160	/** The default physical base address of the APIC. */
1161	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1162	/** Gets the physical base address from the MSR. */
1163	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1164	#endif
1165
1166	/** Undocumented intel MSR for reporting thread and core counts.
1167	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1168	* first 16 bits is the thread count. The next 16 bits the core count, except
1169	* on Westmere where it seems it's only the next 4 bits for some reason. */
1170	#define MSR_CORE_THREAD_COUNT 0x35
1171
1172	/** CPU Feature control. */
1173	#define MSR_IA32_FEATURE_CONTROL 0x3A
1174	/** Feature control - Lock MSR from writes (R/W0). */
1175	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1176	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1177	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1178	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1179	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1180	/** Feature control - SENTER local functions enable (R/WL). */
1181	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1182	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1183	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1184	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1185	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1186	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1187	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1188	/** Feature control - SENTER global enable (R/WL). */
1189	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1190	/** Feature control - SGX launch control enable (R/WL). */
1191	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1192	/** Feature control - SGX global enable (R/WL). */
1193	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1194	/** Feature control - LMCE on (R/WL). */
1195	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1196
1197	/** Per-processor TSC adjust MSR. */
1198	#define MSR_IA32_TSC_ADJUST 0x3B
1199
1200	/** Spectre control register.
1201	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1202	#define MSR_IA32_SPEC_CTRL 0x48
1203	/** IBRS - Indirect branch restricted speculation. */
1204	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1205	/** STIBP - Single thread indirect branch predictors. */
1206	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1207
1208	/** Prediction command register.
1209	* Write only, logical processor scope, no state since write only. */
1210	#define MSR_IA32_PRED_CMD 0x49
1211	/** IBPB - Indirect branch prediction barrie when written as 1. */
1212	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1213
1214	/** BIOS update trigger (microcode update). */
1215	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1216
1217	/** BIOS update signature (microcode). */
1218	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1219
1220	/** SMM monitor control. */
1221	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1222	/** SMM control - Valid. */
1223	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1224	/** SMM control - VMXOFF unblocks SMI. */
1225	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1226	/** SMM control - MSEG base physical address. */
1227	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1228
1229	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1230	#define MSR_IA32_SMBASE 0x9E
1231
1232	/** General performance counter no. 0. */
1233	#define MSR_IA32_PMC0 0xC1
1234	/** General performance counter no. 1. */
1235	#define MSR_IA32_PMC1 0xC2
1236	/** General performance counter no. 2. */
1237	#define MSR_IA32_PMC2 0xC3
1238	/** General performance counter no. 3. */
1239	#define MSR_IA32_PMC3 0xC4
1240
1241	/** Nehalem power control. */
1242	#define MSR_IA32_PLATFORM_INFO 0xCE
1243
1244	/** Get FSB clock status (Intel-specific). */
1245	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1246
1247	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1248	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1249
1250	/** C0 Maximum Frequency Clock Count */
1251	#define MSR_IA32_MPERF 0xE7
1252	/** C0 Actual Frequency Clock Count */
1253	#define MSR_IA32_APERF 0xE8
1254
1255	/** MTRR Capabilities. */
1256	#define MSR_IA32_MTRR_CAP 0xFE
1257
1258	/** Architecture capabilities (bugfixes). */
1259	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1260	/** CPU is no subject to meltdown problems. */
1261	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1262	/** CPU has better IBRS and you can leave it on all the time. */
1263	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1264	/** CPU has return stack buffer (RSB) override. */
1265	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1266	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1267	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1268	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1269	/** CPU does not suffer from MDS issues. */
1270	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1271
1272	/** Flush command register. */
1273	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1274	/** Flush the level 1 data cache when this bit is written. */
1275	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1276
1277	/** Cache control/info. */
1278	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1279
1280	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1281	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1282	* R0 SS == CS + 8
1283	* R3 CS == CS + 16
1284	* R3 SS == CS + 24
1285	*/
1286	#define MSR_IA32_SYSENTER_CS 0x174
1287	/** SYSENTER_ESP - the R0 ESP. */
1288	#define MSR_IA32_SYSENTER_ESP 0x175
1289	/** SYSENTER_EIP - the R0 EIP. */
1290	#define MSR_IA32_SYSENTER_EIP 0x176
1291	#endif
1292
1293	/** Machine Check Global Capabilities Register. */
1294	#define MSR_IA32_MCG_CAP 0x179
1295	/** Machine Check Global Status Register. */
1296	#define MSR_IA32_MCG_STATUS 0x17A
1297	/** Machine Check Global Control Register. */
1298	#define MSR_IA32_MCG_CTRL 0x17B
1299
1300	/** Page Attribute Table. */
1301	#define MSR_IA32_CR_PAT 0x277
1302	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1303	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1304	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1305
1306	/** Performance counter MSRs. (Intel only) */
1307	#define MSR_IA32_PERFEVTSEL0 0x186
1308	#define MSR_IA32_PERFEVTSEL1 0x187
1309	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1310	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1311	* holds a ratio that Apple takes for TSC granularity.
1312	*
1313	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1314	#define MSR_FLEX_RATIO 0x194
1315	/** Performance state value and starting with Intel core more.
1316	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1317	#define MSR_IA32_PERF_STATUS 0x198
1318	#define MSR_IA32_PERF_CTL 0x199
1319	#define MSR_IA32_THERM_STATUS 0x19c
1320
1321	/** Enable misc. processor features (R/W). */
1322	#define MSR_IA32_MISC_ENABLE 0x1A0
1323	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1324	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1325	/** Automatic Thermal Control Circuit Enable (R/W). */
1326	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1327	/** Performance Monitoring Available (R). */
1328	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1329	/** Branch Trace Storage Unavailable (R/O). */
1330	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1331	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1332	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1333	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1334	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1335	/** If MONITOR/MWAIT is supported (R/W). */
1336	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1337	/** Limit CPUID Maxval to 3 leafs (R/W). */
1338	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1339	/** When set to 1, xTPR messages are disabled (R/W). */
1340	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1341	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1342	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1343
1344	/** Trace/Profile Resource Control (R/W) */
1345	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1346	/** Last branch record. */
1347	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1348	/** Branch trace flag (single step on branches). */
1349	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1350	/** Performance monitoring pin control (AMD only). */
1351	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1352	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1353	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1354	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1355	/** Trace message enable (Intel only). */
1356	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1357	/** Branch trace store (Intel only). */
1358	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1359	/** Branch trace interrupt (Intel only). */
1360	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1361	/** Branch trace off in privileged code (Intel only). */
1362	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1363	/** Branch trace off in user code (Intel only). */
1364	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1365	/** Freeze LBR on PMI flag (Intel only). */
1366	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1367	/** Freeze PERFMON on PMI flag (Intel only). */
1368	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1369	/** Freeze while SMM enabled (Intel only). */
1370	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1371	/** Advanced debugging of RTM regions (Intel only). */
1372	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1373	/** Debug control MSR valid bits (Intel only). */
1374	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1375	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1376	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1377	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1378	\| MSR_IA32_DEBUGCTL_RTM)
1379
1380	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1381	* related Xeons. */
1382	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1383	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1384	* @{ */
1385	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1386	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1387	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1388	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1389	/** @} */
1390
1391
1392	#define IA32_MTRR_PHYSBASE0 0x200
1393	#define IA32_MTRR_PHYSMASK0 0x201
1394	#define IA32_MTRR_PHYSBASE1 0x202
1395	#define IA32_MTRR_PHYSMASK1 0x203
1396	#define IA32_MTRR_PHYSBASE2 0x204
1397	#define IA32_MTRR_PHYSMASK2 0x205
1398	#define IA32_MTRR_PHYSBASE3 0x206
1399	#define IA32_MTRR_PHYSMASK3 0x207
1400	#define IA32_MTRR_PHYSBASE4 0x208
1401	#define IA32_MTRR_PHYSMASK4 0x209
1402	#define IA32_MTRR_PHYSBASE5 0x20a
1403	#define IA32_MTRR_PHYSMASK5 0x20b
1404	#define IA32_MTRR_PHYSBASE6 0x20c
1405	#define IA32_MTRR_PHYSMASK6 0x20d
1406	#define IA32_MTRR_PHYSBASE7 0x20e
1407	#define IA32_MTRR_PHYSMASK7 0x20f
1408	#define IA32_MTRR_PHYSBASE8 0x210
1409	#define IA32_MTRR_PHYSMASK8 0x211
1410	#define IA32_MTRR_PHYSBASE9 0x212
1411	#define IA32_MTRR_PHYSMASK9 0x213
1412
1413	/** Fixed range MTRRs.
1414	* @{ */
1415	#define IA32_MTRR_FIX64K_00000 0x250
1416	#define IA32_MTRR_FIX16K_80000 0x258
1417	#define IA32_MTRR_FIX16K_A0000 0x259
1418	#define IA32_MTRR_FIX4K_C0000 0x268
1419	#define IA32_MTRR_FIX4K_C8000 0x269
1420	#define IA32_MTRR_FIX4K_D0000 0x26a
1421	#define IA32_MTRR_FIX4K_D8000 0x26b
1422	#define IA32_MTRR_FIX4K_E0000 0x26c
1423	#define IA32_MTRR_FIX4K_E8000 0x26d
1424	#define IA32_MTRR_FIX4K_F0000 0x26e
1425	#define IA32_MTRR_FIX4K_F8000 0x26f
1426	/** @} */
1427
1428	/** MTRR Default Range. */
1429	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1430
1431	/** Global performance counter control facilities (Intel only). */
1432	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1433	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1434	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1435
1436	/** Precise Event Based sampling (Intel only). */
1437	#define MSR_IA32_PEBS_ENABLE 0x3F1
1438
1439	#define MSR_IA32_MC0_CTL 0x400
1440	#define MSR_IA32_MC0_STATUS 0x401
1441
1442	/** Basic VMX information. */
1443	#define MSR_IA32_VMX_BASIC 0x480
1444	/** Allowed settings for pin-based VM execution controls. */
1445	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1446	/** Allowed settings for proc-based VM execution controls. */
1447	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1448	/** Allowed settings for the VM-exit controls. */
1449	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1450	/** Allowed settings for the VM-entry controls. */
1451	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1452	/** Misc VMX info. */
1453	#define MSR_IA32_VMX_MISC 0x485
1454	/** Fixed cleared bits in CR0. */
1455	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1456	/** Fixed set bits in CR0. */
1457	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1458	/** Fixed cleared bits in CR4. */
1459	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1460	/** Fixed set bits in CR4. */
1461	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1462	/** Information for enumerating fields in the VMCS. */
1463	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1464	/** Allowed settings for secondary proc-based VM execution controls */
1465	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1466	/** EPT capabilities. */
1467	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1468	/** Allowed settings of all pin-based VM execution controls. */
1469	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1470	/** Allowed settings of all proc-based VM execution controls. */
1471	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1472	/** Allowed settings of all VMX exit controls. */
1473	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1474	/** Allowed settings of all VMX entry controls. */
1475	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1476	/** Allowed settings for the VM-function controls. */
1477	#define MSR_IA32_VMX_VMFUNC 0x491
1478
1479	/** Intel PT - Enable and control for trace packet generation. */
1480	#define MSR_IA32_RTIT_CTL 0x570
1481
1482	/** DS Save Area (R/W). */
1483	#define MSR_IA32_DS_AREA 0x600
1484	/** Running Average Power Limit (RAPL) power units. */
1485	#define MSR_RAPL_POWER_UNIT 0x606
1486	/** Package C3 Interrupt Response Limit. */
1487	#define MSR_PKGC3_IRTL 0x60a
1488	/** Package C6/C7S Interrupt Response Limit 1. */
1489	#define MSR_PKGC_IRTL1 0x60b
1490	/** Package C6/C7S Interrupt Response Limit 2. */
1491	#define MSR_PKGC_IRTL2 0x60c
1492	/** Package C2 Residency Counter. */
1493	#define MSR_PKG_C2_RESIDENCY 0x60d
1494	/** PKG RAPL Power Limit Control. */
1495	#define MSR_PKG_POWER_LIMIT 0x610
1496	/** PKG Energy Status. */
1497	#define MSR_PKG_ENERGY_STATUS 0x611
1498	/** PKG Perf Status. */
1499	#define MSR_PKG_PERF_STATUS 0x613
1500	/** PKG RAPL Parameters. */
1501	#define MSR_PKG_POWER_INFO 0x614
1502	/** DRAM RAPL Power Limit Control. */
1503	#define MSR_DRAM_POWER_LIMIT 0x618
1504	/** DRAM Energy Status. */
1505	#define MSR_DRAM_ENERGY_STATUS 0x619
1506	/** DRAM Performance Throttling Status. */
1507	#define MSR_DRAM_PERF_STATUS 0x61b
1508	/** DRAM RAPL Parameters. */
1509	#define MSR_DRAM_POWER_INFO 0x61c
1510	/** Package C10 Residency Counter. */
1511	#define MSR_PKG_C10_RESIDENCY 0x632
1512	/** PP0 Energy Status. */
1513	#define MSR_PP0_ENERGY_STATUS 0x639
1514	/** PP1 Energy Status. */
1515	#define MSR_PP1_ENERGY_STATUS 0x641
1516	/** Turbo Activation Ratio. */
1517	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1518	/** Core Performance Limit Reasons. */
1519	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1520
1521	/** Last branch record from IP MSRs.
1522	* @{ */
1523	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1524	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1525	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1526	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1527	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1528	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1529	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1530	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1531	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1532	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1533	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1534	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1535	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1536	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1537	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1538	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1539	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1540	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1541	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1542	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1543	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1544	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1545	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1546	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1547	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1548	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1549	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1550	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1551	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1552	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1553	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1554	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1555	/** @} */
1556
1557	/** Last branch record to IP MSRs.
1558	* @{ */
1559	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1560	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1561	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1562	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1563	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1564	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1565	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1566	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1567	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1568	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1569	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1570	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1571	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1572	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1573	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1574	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1575	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1576	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1577	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1578	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1579	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1580	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1581	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1582	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1583	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1584	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1585	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1586	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1587	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1588	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1589	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1590	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1591	/** @} */
1592
1593	/** X2APIC MSR range start. */
1594	#define MSR_IA32_X2APIC_START 0x800
1595	/** X2APIC MSR - APIC ID Register. */
1596	#define MSR_IA32_X2APIC_ID 0x802
1597	/** X2APIC MSR - APIC Version Register. */
1598	#define MSR_IA32_X2APIC_VERSION 0x803
1599	/** X2APIC MSR - Task Priority Register. */
1600	#define MSR_IA32_X2APIC_TPR 0x808
1601	/** X2APIC MSR - Processor Priority register. */
1602	#define MSR_IA32_X2APIC_PPR 0x80A
1603	/** X2APIC MSR - End Of Interrupt register. */
1604	#define MSR_IA32_X2APIC_EOI 0x80B
1605	/** X2APIC MSR - Logical Destination Register. */
1606	#define MSR_IA32_X2APIC_LDR 0x80D
1607	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1608	#define MSR_IA32_X2APIC_SVR 0x80F
1609	/** X2APIC MSR - In-service Register (bits 31:0). */
1610	#define MSR_IA32_X2APIC_ISR0 0x810
1611	/** X2APIC MSR - In-service Register (bits 63:32). */
1612	#define MSR_IA32_X2APIC_ISR1 0x811
1613	/** X2APIC MSR - In-service Register (bits 95:64). */
1614	#define MSR_IA32_X2APIC_ISR2 0x812
1615	/** X2APIC MSR - In-service Register (bits 127:96). */
1616	#define MSR_IA32_X2APIC_ISR3 0x813
1617	/** X2APIC MSR - In-service Register (bits 159:128). */
1618	#define MSR_IA32_X2APIC_ISR4 0x814
1619	/** X2APIC MSR - In-service Register (bits 191:160). */
1620	#define MSR_IA32_X2APIC_ISR5 0x815
1621	/** X2APIC MSR - In-service Register (bits 223:192). */
1622	#define MSR_IA32_X2APIC_ISR6 0x816
1623	/** X2APIC MSR - In-service Register (bits 255:224). */
1624	#define MSR_IA32_X2APIC_ISR7 0x817
1625	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1626	#define MSR_IA32_X2APIC_TMR0 0x818
1627	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1628	#define MSR_IA32_X2APIC_TMR1 0x819
1629	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1630	#define MSR_IA32_X2APIC_TMR2 0x81A
1631	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1632	#define MSR_IA32_X2APIC_TMR3 0x81B
1633	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1634	#define MSR_IA32_X2APIC_TMR4 0x81C
1635	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1636	#define MSR_IA32_X2APIC_TMR5 0x81D
1637	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1638	#define MSR_IA32_X2APIC_TMR6 0x81E
1639	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1640	#define MSR_IA32_X2APIC_TMR7 0x81F
1641	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1642	#define MSR_IA32_X2APIC_IRR0 0x820
1643	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1644	#define MSR_IA32_X2APIC_IRR1 0x821
1645	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1646	#define MSR_IA32_X2APIC_IRR2 0x822
1647	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1648	#define MSR_IA32_X2APIC_IRR3 0x823
1649	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1650	#define MSR_IA32_X2APIC_IRR4 0x824
1651	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1652	#define MSR_IA32_X2APIC_IRR5 0x825
1653	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1654	#define MSR_IA32_X2APIC_IRR6 0x826
1655	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1656	#define MSR_IA32_X2APIC_IRR7 0x827
1657	/** X2APIC MSR - Error Status Register. */
1658	#define MSR_IA32_X2APIC_ESR 0x828
1659	/** X2APIC MSR - LVT CMCI Register. */
1660	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1661	/** X2APIC MSR - Interrupt Command Register. */
1662	#define MSR_IA32_X2APIC_ICR 0x830
1663	/** X2APIC MSR - LVT Timer Register. */
1664	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1665	/** X2APIC MSR - LVT Thermal Sensor Register. */
1666	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1667	/** X2APIC MSR - LVT Performance Counter Register. */
1668	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1669	/** X2APIC MSR - LVT LINT0 Register. */
1670	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1671	/** X2APIC MSR - LVT LINT1 Register. */
1672	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1673	/** X2APIC MSR - LVT Error Register . */
1674	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1675	/** X2APIC MSR - Timer Initial Count Register. */
1676	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1677	/** X2APIC MSR - Timer Current Count Register. */
1678	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1679	/** X2APIC MSR - Timer Divide Configuration Register. */
1680	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1681	/** X2APIC MSR - Self IPI. */
1682	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1683	/** X2APIC MSR range end. */
1684	#define MSR_IA32_X2APIC_END 0xBFF
1685	/** X2APIC MSR - LVT start range. */
1686	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1687	/** X2APIC MSR - LVT end range (inclusive). */
1688	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1689
1690	/** K6 EFER - Extended Feature Enable Register. */
1691	#define MSR_K6_EFER UINT32_C(0xc0000080)
1692	/** @todo document EFER */
1693	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1694	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1695	/** Bit 8 - LME - Long mode enabled. (R/W) */
1696	#define MSR_K6_EFER_LME RT_BIT_32(8)
1697	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1698	/** Bit 10 - LMA - Long mode active. (R) */
1699	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1700	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1701	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1702	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1703	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1704	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1705	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1706	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1707	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1708	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1709	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1710	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1711	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1712	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1713	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1714
1715	/** K6 STAR - SYSCALL/RET targets. */
1716	#define MSR_K6_STAR UINT32_C(0xc0000081)
1717	/** Shift value for getting the SYSRET CS and SS value. */
1718	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1719	/** Shift value for getting the SYSCALL CS and SS value. */
1720	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1721	/** Selector mask for use after shifting. */
1722	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1723	/** The mask which give the SYSCALL EIP. */
1724	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1725	/** K6 WHCR - Write Handling Control Register. */
1726	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1727	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1728	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1729	/** K6 PSOR - Processor State Observability Register. */
1730	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1731	/** K6 PFIR - Page Flush/Invalidate Register. */
1732	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1733
1734	/** Performance counter MSRs. (AMD only) */
1735	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1736	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1737	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1738	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1739	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1740	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1741	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1742	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1743
1744	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1745	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1746	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1747	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1748	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1749	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1750	/** K8 FS.base - The 64-bit base FS register. */
1751	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1752	/** K8 GS.base - The 64-bit base GS register. */
1753	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1754	/** K8 KernelGSbase - Used with SWAPGS. */
1755	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1756	/** K8 TSC_AUX - Used with RDTSCP. */
1757	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1758	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1759	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1760	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1761	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1762	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1763	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1764	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1765	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1766	/** North bridge config? See BIOS & Kernel dev guides for
1767	* details. */
1768	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1769
1770	/** Hypertransport interrupt pending register.
1771	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1772	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1773
1774	/** SVM Control. */
1775	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1776	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1777	* features. */
1778	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1779	/** If set, non-intercepted INIT signals are converted to \#SX
1780	* exceptions. */
1781	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1782	/** Disables A20 masking. */
1783	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1784	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1785	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1786	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1787	* clear, EFER.SVME can be written normally. */
1788	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1789
1790	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1791	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1792	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1793	* host state during world switch. */
1794	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1795
1796	/** @} */
1797
1798
1799	/** @name Page Table / Directory / Directory Pointers / L4.
1800	* @{
1801	*/
1802
1803	/** Page table/directory entry as an unsigned integer. */
1804	typedef uint32_t X86PGUINT;
1805	/** Pointer to a page table/directory table entry as an unsigned integer. */
1806	typedef X86PGUINT *PX86PGUINT;
1807	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1808	typedef X86PGUINT const *PCX86PGUINT;
1809
1810	/** Number of entries in a 32-bit PT/PD. */
1811	#define X86_PG_ENTRIES 1024
1812
1813
1814	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1815	typedef uint64_t X86PGPAEUINT;
1816	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1817	typedef X86PGPAEUINT *PX86PGPAEUINT;
1818	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1819	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1820
1821	/** Number of entries in a PAE PT/PD. */
1822	#define X86_PG_PAE_ENTRIES 512
1823	/** Number of entries in a PAE PDPT. */
1824	#define X86_PG_PAE_PDPE_ENTRIES 4
1825
1826	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1827	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1828	/** Number of entries in an AMD64 PDPT.
1829	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1830	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1831
1832	/** The size of a default page. */
1833	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1834	/** The page shift of a default page. */
1835	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1836	/** The default page offset mask. */
1837	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1838	/** The default page base mask for virtual addresses. */
1839	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1840	/** The default page base mask for virtual addresses - 32bit version. */
1841	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1842
1843	/** The size of a 4KB page. */
1844	#define X86_PAGE_4K_SIZE _4K
1845	/** The page shift of a 4KB page. */
1846	#define X86_PAGE_4K_SHIFT 12
1847	/** The 4KB page offset mask. */
1848	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1849	/** The 4KB page base mask for virtual addresses. */
1850	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1851	/** The 4KB page base mask for virtual addresses - 32bit version. */
1852	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1853
1854	/** The size of a 2MB page. */
1855	#define X86_PAGE_2M_SIZE _2M
1856	/** The page shift of a 2MB page. */
1857	#define X86_PAGE_2M_SHIFT 21
1858	/** The 2MB page offset mask. */
1859	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1860	/** The 2MB page base mask for virtual addresses. */
1861	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1862	/** The 2MB page base mask for virtual addresses - 32bit version. */
1863	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1864
1865	/** The size of a 4MB page. */
1866	#define X86_PAGE_4M_SIZE _4M
1867	/** The page shift of a 4MB page. */
1868	#define X86_PAGE_4M_SHIFT 22
1869	/** The 4MB page offset mask. */
1870	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1871	/** The 4MB page base mask for virtual addresses. */
1872	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1873	/** The 4MB page base mask for virtual addresses - 32bit version. */
1874	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1875
1876	/** The size of a 1GB page. */
1877	#define X86_PAGE_1G_SIZE _1G
1878	/** The page shift of a 1GB page. */
1879	#define X86_PAGE_1G_SHIFT 30
1880	/** The 1GB page offset mask. */
1881	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1882	/** The 1GB page base mask for virtual addresses. */
1883	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1884
1885	/**
1886	* Check if the given address is canonical.
1887	*/
1888	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1889
1890
1891	/** @name Page Table Entry
1892	* @{
1893	*/
1894	/** Bit 0 - P - Present bit. */
1895	#define X86_PTE_BIT_P 0
1896	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1897	#define X86_PTE_BIT_RW 1
1898	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1899	#define X86_PTE_BIT_US 2
1900	/** Bit 3 - PWT - Page level write thru bit. */
1901	#define X86_PTE_BIT_PWT 3
1902	/** Bit 4 - PCD - Page level cache disable bit. */
1903	#define X86_PTE_BIT_PCD 4
1904	/** Bit 5 - A - Access bit. */
1905	#define X86_PTE_BIT_A 5
1906	/** Bit 6 - D - Dirty bit. */
1907	#define X86_PTE_BIT_D 6
1908	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1909	#define X86_PTE_BIT_PAT 7
1910	/** Bit 8 - G - Global flag. */
1911	#define X86_PTE_BIT_G 8
1912	/** Bits 63 - NX - PAE/LM - No execution flag. */
1913	#define X86_PTE_PAE_BIT_NX 63
1914
1915	/** Bit 0 - P - Present bit mask. */
1916	#define X86_PTE_P RT_BIT_32(0)
1917	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1918	#define X86_PTE_RW RT_BIT_32(1)
1919	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1920	#define X86_PTE_US RT_BIT_32(2)
1921	/** Bit 3 - PWT - Page level write thru bit mask. */
1922	#define X86_PTE_PWT RT_BIT_32(3)
1923	/** Bit 4 - PCD - Page level cache disable bit mask. */
1924	#define X86_PTE_PCD RT_BIT_32(4)
1925	/** Bit 5 - A - Access bit mask. */
1926	#define X86_PTE_A RT_BIT_32(5)
1927	/** Bit 6 - D - Dirty bit mask. */
1928	#define X86_PTE_D RT_BIT_32(6)
1929	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1930	#define X86_PTE_PAT RT_BIT_32(7)
1931	/** Bit 8 - G - Global bit mask. */
1932	#define X86_PTE_G RT_BIT_32(8)
1933
1934	/** Bits 9-11 - - Available for use to system software. */
1935	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1936	/** Bits 12-31 - - Physical Page number of the next level. */
1937	#define X86_PTE_PG_MASK ( 0xfffff000 )
1938
1939	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1940	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1941	/** Bits 63 - NX - PAE/LM - No execution flag. */
1942	#define X86_PTE_PAE_NX RT_BIT_64(63)
1943	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1944	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1945	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1946	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1947	/** No bits - - LM - MBZ bits when NX is active. */
1948	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1949	/** Bits 63 - - LM - MBZ bits when no NX. */
1950	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1951
1952	/**
1953	* Page table entry.
1954	*/
1955	typedef struct X86PTEBITS
1956	{
1957	/** Flags whether(=1) or not the page is present. */
1958	uint32_t u1Present : 1;
1959	/** Read(=0) / Write(=1) flag. */
1960	uint32_t u1Write : 1;
1961	/** User(=1) / Supervisor (=0) flag. */
1962	uint32_t u1User : 1;
1963	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1964	uint32_t u1WriteThru : 1;
1965	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1966	uint32_t u1CacheDisable : 1;
1967	/** Accessed flag.
1968	* Indicates that the page have been read or written to. */
1969	uint32_t u1Accessed : 1;
1970	/** Dirty flag.
1971	* Indicates that the page has been written to. */
1972	uint32_t u1Dirty : 1;
1973	/** Reserved / If PAT enabled, bit 2 of the index. */
1974	uint32_t u1PAT : 1;
1975	/** Global flag. (Ignored in all but final level.) */
1976	uint32_t u1Global : 1;
1977	/** Available for use to system software. */
1978	uint32_t u3Available : 3;
1979	/** Physical Page number of the next level. */
1980	uint32_t u20PageNo : 20;
1981	} X86PTEBITS;
1982	#ifndef VBOX_FOR_DTRACE_LIB
1983	AssertCompileSize(X86PTEBITS, 4);
1984	#endif
1985	/** Pointer to a page table entry. */
1986	typedef X86PTEBITS *PX86PTEBITS;
1987	/** Pointer to a const page table entry. */
1988	typedef const X86PTEBITS *PCX86PTEBITS;
1989
1990	/**
1991	* Page table entry.
1992	*/
1993	typedef union X86PTE
1994	{
1995	/** Unsigned integer view */
1996	X86PGUINT u;
1997	/** Bit field view. */
1998	X86PTEBITS n;
1999	/** 32-bit view. */
2000	uint32_t au32[1];
2001	/** 16-bit view. */
2002	uint16_t au16[2];
2003	/** 8-bit view. */
2004	uint8_t au8[4];
2005	} X86PTE;
2006	#ifndef VBOX_FOR_DTRACE_LIB
2007	AssertCompileSize(X86PTE, 4);
2008	#endif
2009	/** Pointer to a page table entry. */
2010	typedef X86PTE *PX86PTE;
2011	/** Pointer to a const page table entry. */
2012	typedef const X86PTE *PCX86PTE;
2013
2014
2015	/**
2016	* PAE page table entry.
2017	*/
2018	typedef struct X86PTEPAEBITS
2019	{
2020	/** Flags whether(=1) or not the page is present. */
2021	uint32_t u1Present : 1;
2022	/** Read(=0) / Write(=1) flag. */
2023	uint32_t u1Write : 1;
2024	/** User(=1) / Supervisor(=0) flag. */
2025	uint32_t u1User : 1;
2026	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2027	uint32_t u1WriteThru : 1;
2028	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2029	uint32_t u1CacheDisable : 1;
2030	/** Accessed flag.
2031	* Indicates that the page have been read or written to. */
2032	uint32_t u1Accessed : 1;
2033	/** Dirty flag.
2034	* Indicates that the page has been written to. */
2035	uint32_t u1Dirty : 1;
2036	/** Reserved / If PAT enabled, bit 2 of the index. */
2037	uint32_t u1PAT : 1;
2038	/** Global flag. (Ignored in all but final level.) */
2039	uint32_t u1Global : 1;
2040	/** Available for use to system software. */
2041	uint32_t u3Available : 3;
2042	/** Physical Page number of the next level - Low Part. Don't use this. */
2043	uint32_t u20PageNoLow : 20;
2044	/** Physical Page number of the next level - High Part. Don't use this. */
2045	uint32_t u20PageNoHigh : 20;
2046	/** MBZ bits */
2047	uint32_t u11Reserved : 11;
2048	/** No Execute flag. */
2049	uint32_t u1NoExecute : 1;
2050	} X86PTEPAEBITS;
2051	#ifndef VBOX_FOR_DTRACE_LIB
2052	AssertCompileSize(X86PTEPAEBITS, 8);
2053	#endif
2054	/** Pointer to a page table entry. */
2055	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2056	/** Pointer to a page table entry. */
2057	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2058
2059	/**
2060	* PAE Page table entry.
2061	*/
2062	typedef union X86PTEPAE
2063	{
2064	/** Unsigned integer view */
2065	X86PGPAEUINT u;
2066	/** Bit field view. */
2067	X86PTEPAEBITS n;
2068	/** 32-bit view. */
2069	uint32_t au32[2];
2070	/** 16-bit view. */
2071	uint16_t au16[4];
2072	/** 8-bit view. */
2073	uint8_t au8[8];
2074	} X86PTEPAE;
2075	#ifndef VBOX_FOR_DTRACE_LIB
2076	AssertCompileSize(X86PTEPAE, 8);
2077	#endif
2078	/** Pointer to a PAE page table entry. */
2079	typedef X86PTEPAE *PX86PTEPAE;
2080	/** Pointer to a const PAE page table entry. */
2081	typedef const X86PTEPAE *PCX86PTEPAE;
2082	/** @} */
2083
2084	/**
2085	* Page table.
2086	*/
2087	typedef struct X86PT
2088	{
2089	/** PTE Array. */
2090	X86PTE a[X86_PG_ENTRIES];
2091	} X86PT;
2092	#ifndef VBOX_FOR_DTRACE_LIB
2093	AssertCompileSize(X86PT, 4096);
2094	#endif
2095	/** Pointer to a page table. */
2096	typedef X86PT *PX86PT;
2097	/** Pointer to a const page table. */
2098	typedef const X86PT *PCX86PT;
2099
2100	/** The page shift to get the PT index. */
2101	#define X86_PT_SHIFT 12
2102	/** The PT index mask (apply to a shifted page address). */
2103	#define X86_PT_MASK 0x3ff
2104
2105
2106	/**
2107	* Page directory.
2108	*/
2109	typedef struct X86PTPAE
2110	{
2111	/** PTE Array. */
2112	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2113	} X86PTPAE;
2114	#ifndef VBOX_FOR_DTRACE_LIB
2115	AssertCompileSize(X86PTPAE, 4096);
2116	#endif
2117	/** Pointer to a page table. */
2118	typedef X86PTPAE *PX86PTPAE;
2119	/** Pointer to a const page table. */
2120	typedef const X86PTPAE *PCX86PTPAE;
2121
2122	/** The page shift to get the PA PTE index. */
2123	#define X86_PT_PAE_SHIFT 12
2124	/** The PAE PT index mask (apply to a shifted page address). */
2125	#define X86_PT_PAE_MASK 0x1ff
2126
2127
2128	/** @name 4KB Page Directory Entry
2129	* @{
2130	*/
2131	/** Bit 0 - P - Present bit. */
2132	#define X86_PDE_P RT_BIT_32(0)
2133	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2134	#define X86_PDE_RW RT_BIT_32(1)
2135	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2136	#define X86_PDE_US RT_BIT_32(2)
2137	/** Bit 3 - PWT - Page level write thru bit. */
2138	#define X86_PDE_PWT RT_BIT_32(3)
2139	/** Bit 4 - PCD - Page level cache disable bit. */
2140	#define X86_PDE_PCD RT_BIT_32(4)
2141	/** Bit 5 - A - Access bit. */
2142	#define X86_PDE_A RT_BIT_32(5)
2143	/** Bit 7 - PS - Page size attribute.
2144	* Clear mean 4KB pages, set means large pages (2/4MB). */
2145	#define X86_PDE_PS RT_BIT_32(7)
2146	/** Bits 9-11 - - Available for use to system software. */
2147	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2148	/** Bits 12-31 - - Physical Page number of the next level. */
2149	#define X86_PDE_PG_MASK ( 0xfffff000 )
2150
2151	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2152	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2153	/** Bits 63 - NX - PAE/LM - No execution flag. */
2154	#define X86_PDE_PAE_NX RT_BIT_64(63)
2155	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2156	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2157	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2158	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2159	/** Bit 7 - - LM - MBZ bits when NX is active. */
2160	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2161	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2162	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2163
2164	/**
2165	* Page directory entry.
2166	*/
2167	typedef struct X86PDEBITS
2168	{
2169	/** Flags whether(=1) or not the page is present. */
2170	uint32_t u1Present : 1;
2171	/** Read(=0) / Write(=1) flag. */
2172	uint32_t u1Write : 1;
2173	/** User(=1) / Supervisor (=0) flag. */
2174	uint32_t u1User : 1;
2175	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2176	uint32_t u1WriteThru : 1;
2177	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2178	uint32_t u1CacheDisable : 1;
2179	/** Accessed flag.
2180	* Indicates that the page has been read or written to. */
2181	uint32_t u1Accessed : 1;
2182	/** Reserved / Ignored (dirty bit). */
2183	uint32_t u1Reserved0 : 1;
2184	/** Size bit if PSE is enabled - in any event it's 0. */
2185	uint32_t u1Size : 1;
2186	/** Reserved / Ignored (global bit). */
2187	uint32_t u1Reserved1 : 1;
2188	/** Available for use to system software. */
2189	uint32_t u3Available : 3;
2190	/** Physical Page number of the next level. */
2191	uint32_t u20PageNo : 20;
2192	} X86PDEBITS;
2193	#ifndef VBOX_FOR_DTRACE_LIB
2194	AssertCompileSize(X86PDEBITS, 4);
2195	#endif
2196	/** Pointer to a page directory entry. */
2197	typedef X86PDEBITS *PX86PDEBITS;
2198	/** Pointer to a const page directory entry. */
2199	typedef const X86PDEBITS *PCX86PDEBITS;
2200
2201
2202	/**
2203	* PAE page directory entry.
2204	*/
2205	typedef struct X86PDEPAEBITS
2206	{
2207	/** Flags whether(=1) or not the page is present. */
2208	uint32_t u1Present : 1;
2209	/** Read(=0) / Write(=1) flag. */
2210	uint32_t u1Write : 1;
2211	/** User(=1) / Supervisor (=0) flag. */
2212	uint32_t u1User : 1;
2213	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2214	uint32_t u1WriteThru : 1;
2215	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2216	uint32_t u1CacheDisable : 1;
2217	/** Accessed flag.
2218	* Indicates that the page has been read or written to. */
2219	uint32_t u1Accessed : 1;
2220	/** Reserved / Ignored (dirty bit). */
2221	uint32_t u1Reserved0 : 1;
2222	/** Size bit if PSE is enabled - in any event it's 0. */
2223	uint32_t u1Size : 1;
2224	/** Reserved / Ignored (global bit). / */
2225	uint32_t u1Reserved1 : 1;
2226	/** Available for use to system software. */
2227	uint32_t u3Available : 3;
2228	/** Physical Page number of the next level - Low Part. Don't use! */
2229	uint32_t u20PageNoLow : 20;
2230	/** Physical Page number of the next level - High Part. Don't use! */
2231	uint32_t u20PageNoHigh : 20;
2232	/** MBZ bits */
2233	uint32_t u11Reserved : 11;
2234	/** No Execute flag. */
2235	uint32_t u1NoExecute : 1;
2236	} X86PDEPAEBITS;
2237	#ifndef VBOX_FOR_DTRACE_LIB
2238	AssertCompileSize(X86PDEPAEBITS, 8);
2239	#endif
2240	/** Pointer to a page directory entry. */
2241	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2242	/** Pointer to a const page directory entry. */
2243	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2244
2245	/** @} */
2246
2247
2248	/** @name 2/4MB Page Directory Entry
2249	* @{
2250	*/
2251	/** Bit 0 - P - Present bit. */
2252	#define X86_PDE4M_P RT_BIT_32(0)
2253	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2254	#define X86_PDE4M_RW RT_BIT_32(1)
2255	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2256	#define X86_PDE4M_US RT_BIT_32(2)
2257	/** Bit 3 - PWT - Page level write thru bit. */
2258	#define X86_PDE4M_PWT RT_BIT_32(3)
2259	/** Bit 4 - PCD - Page level cache disable bit. */
2260	#define X86_PDE4M_PCD RT_BIT_32(4)
2261	/** Bit 5 - A - Access bit. */
2262	#define X86_PDE4M_A RT_BIT_32(5)
2263	/** Bit 6 - D - Dirty bit. */
2264	#define X86_PDE4M_D RT_BIT_32(6)
2265	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2266	#define X86_PDE4M_PS RT_BIT_32(7)
2267	/** Bit 8 - G - Global flag. */
2268	#define X86_PDE4M_G RT_BIT_32(8)
2269	/** Bits 9-11 - AVL - Available for use to system software. */
2270	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2271	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2272	#define X86_PDE4M_PAT RT_BIT_32(12)
2273	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2274	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2275	/** Bits 22-31 - - Physical Page number. */
2276	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2277	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2278	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2279	/** The number of bits to the high part of the page number. */
2280	#define X86_PDE4M_PG_HIGH_SHIFT 19
2281	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2282	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2283
2284	/** Bits 21-51 - - PAE/LM - Physical Page number.
2285	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2286	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2287	/** Bits 63 - NX - PAE/LM - No execution flag. */
2288	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2289	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2290	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2291	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2292	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2293	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2294	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2295	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2296	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2297
2298	/**
2299	* 4MB page directory entry.
2300	*/
2301	typedef struct X86PDE4MBITS
2302	{
2303	/** Flags whether(=1) or not the page is present. */
2304	uint32_t u1Present : 1;
2305	/** Read(=0) / Write(=1) flag. */
2306	uint32_t u1Write : 1;
2307	/** User(=1) / Supervisor (=0) flag. */
2308	uint32_t u1User : 1;
2309	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2310	uint32_t u1WriteThru : 1;
2311	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2312	uint32_t u1CacheDisable : 1;
2313	/** Accessed flag.
2314	* Indicates that the page have been read or written to. */
2315	uint32_t u1Accessed : 1;
2316	/** Dirty flag.
2317	* Indicates that the page has been written to. */
2318	uint32_t u1Dirty : 1;
2319	/** Page size flag - always 1 for 4MB entries. */
2320	uint32_t u1Size : 1;
2321	/** Global flag. */
2322	uint32_t u1Global : 1;
2323	/** Available for use to system software. */
2324	uint32_t u3Available : 3;
2325	/** Reserved / If PAT enabled, bit 2 of the index. */
2326	uint32_t u1PAT : 1;
2327	/** Bits 32-39 of the page number on AMD64.
2328	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2329	uint32_t u8PageNoHigh : 8;
2330	/** Reserved. */
2331	uint32_t u1Reserved : 1;
2332	/** Physical Page number of the page. */
2333	uint32_t u10PageNo : 10;
2334	} X86PDE4MBITS;
2335	#ifndef VBOX_FOR_DTRACE_LIB
2336	AssertCompileSize(X86PDE4MBITS, 4);
2337	#endif
2338	/** Pointer to a page table entry. */
2339	typedef X86PDE4MBITS *PX86PDE4MBITS;
2340	/** Pointer to a const page table entry. */
2341	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2342
2343
2344	/**
2345	* 2MB PAE page directory entry.
2346	*/
2347	typedef struct X86PDE2MPAEBITS
2348	{
2349	/** Flags whether(=1) or not the page is present. */
2350	uint32_t u1Present : 1;
2351	/** Read(=0) / Write(=1) flag. */
2352	uint32_t u1Write : 1;
2353	/** User(=1) / Supervisor(=0) flag. */
2354	uint32_t u1User : 1;
2355	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2356	uint32_t u1WriteThru : 1;
2357	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2358	uint32_t u1CacheDisable : 1;
2359	/** Accessed flag.
2360	* Indicates that the page have been read or written to. */
2361	uint32_t u1Accessed : 1;
2362	/** Dirty flag.
2363	* Indicates that the page has been written to. */
2364	uint32_t u1Dirty : 1;
2365	/** Page size flag - always 1 for 2MB entries. */
2366	uint32_t u1Size : 1;
2367	/** Global flag. */
2368	uint32_t u1Global : 1;
2369	/** Available for use to system software. */
2370	uint32_t u3Available : 3;
2371	/** Reserved / If PAT enabled, bit 2 of the index. */
2372	uint32_t u1PAT : 1;
2373	/** Reserved. */
2374	uint32_t u9Reserved : 9;
2375	/** Physical Page number of the next level - Low part. Don't use! */
2376	uint32_t u10PageNoLow : 10;
2377	/** Physical Page number of the next level - High part. Don't use! */
2378	uint32_t u20PageNoHigh : 20;
2379	/** MBZ bits */
2380	uint32_t u11Reserved : 11;
2381	/** No Execute flag. */
2382	uint32_t u1NoExecute : 1;
2383	} X86PDE2MPAEBITS;
2384	#ifndef VBOX_FOR_DTRACE_LIB
2385	AssertCompileSize(X86PDE2MPAEBITS, 8);
2386	#endif
2387	/** Pointer to a 2MB PAE page table entry. */
2388	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2389	/** Pointer to a 2MB PAE page table entry. */
2390	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2391
2392	/** @} */
2393
2394	/**
2395	* Page directory entry.
2396	*/
2397	typedef union X86PDE
2398	{
2399	/** Unsigned integer view. */
2400	X86PGUINT u;
2401	/** Normal view. */
2402	X86PDEBITS n;
2403	/** 4MB view (big). */
2404	X86PDE4MBITS b;
2405	/** 8 bit unsigned integer view. */
2406	uint8_t au8[4];
2407	/** 16 bit unsigned integer view. */
2408	uint16_t au16[2];
2409	/** 32 bit unsigned integer view. */
2410	uint32_t au32[1];
2411	} X86PDE;
2412	#ifndef VBOX_FOR_DTRACE_LIB
2413	AssertCompileSize(X86PDE, 4);
2414	#endif
2415	/** Pointer to a page directory entry. */
2416	typedef X86PDE *PX86PDE;
2417	/** Pointer to a const page directory entry. */
2418	typedef const X86PDE *PCX86PDE;
2419
2420	/**
2421	* PAE page directory entry.
2422	*/
2423	typedef union X86PDEPAE
2424	{
2425	/** Unsigned integer view. */
2426	X86PGPAEUINT u;
2427	/** Normal view. */
2428	X86PDEPAEBITS n;
2429	/** 2MB page view (big). */
2430	X86PDE2MPAEBITS b;
2431	/** 8 bit unsigned integer view. */
2432	uint8_t au8[8];
2433	/** 16 bit unsigned integer view. */
2434	uint16_t au16[4];
2435	/** 32 bit unsigned integer view. */
2436	uint32_t au32[2];
2437	} X86PDEPAE;
2438	#ifndef VBOX_FOR_DTRACE_LIB
2439	AssertCompileSize(X86PDEPAE, 8);
2440	#endif
2441	/** Pointer to a page directory entry. */
2442	typedef X86PDEPAE *PX86PDEPAE;
2443	/** Pointer to a const page directory entry. */
2444	typedef const X86PDEPAE *PCX86PDEPAE;
2445
2446	/**
2447	* Page directory.
2448	*/
2449	typedef struct X86PD
2450	{
2451	/** PDE Array. */
2452	X86PDE a[X86_PG_ENTRIES];
2453	} X86PD;
2454	#ifndef VBOX_FOR_DTRACE_LIB
2455	AssertCompileSize(X86PD, 4096);
2456	#endif
2457	/** Pointer to a page directory. */
2458	typedef X86PD *PX86PD;
2459	/** Pointer to a const page directory. */
2460	typedef const X86PD *PCX86PD;
2461
2462	/** The page shift to get the PD index. */
2463	#define X86_PD_SHIFT 22
2464	/** The PD index mask (apply to a shifted page address). */
2465	#define X86_PD_MASK 0x3ff
2466
2467
2468	/**
2469	* PAE page directory.
2470	*/
2471	typedef struct X86PDPAE
2472	{
2473	/** PDE Array. */
2474	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2475	} X86PDPAE;
2476	#ifndef VBOX_FOR_DTRACE_LIB
2477	AssertCompileSize(X86PDPAE, 4096);
2478	#endif
2479	/** Pointer to a PAE page directory. */
2480	typedef X86PDPAE *PX86PDPAE;
2481	/** Pointer to a const PAE page directory. */
2482	typedef const X86PDPAE *PCX86PDPAE;
2483
2484	/** The page shift to get the PAE PD index. */
2485	#define X86_PD_PAE_SHIFT 21
2486	/** The PAE PD index mask (apply to a shifted page address). */
2487	#define X86_PD_PAE_MASK 0x1ff
2488
2489
2490	/** @name Page Directory Pointer Table Entry (PAE)
2491	* @{
2492	*/
2493	/** Bit 0 - P - Present bit. */
2494	#define X86_PDPE_P RT_BIT_32(0)
2495	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2496	#define X86_PDPE_RW RT_BIT_32(1)
2497	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2498	#define X86_PDPE_US RT_BIT_32(2)
2499	/** Bit 3 - PWT - Page level write thru bit. */
2500	#define X86_PDPE_PWT RT_BIT_32(3)
2501	/** Bit 4 - PCD - Page level cache disable bit. */
2502	#define X86_PDPE_PCD RT_BIT_32(4)
2503	/** Bit 5 - A - Access bit. Long Mode only. */
2504	#define X86_PDPE_A RT_BIT_32(5)
2505	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2506	#define X86_PDPE_LM_PS RT_BIT_32(7)
2507	/** Bits 9-11 - - Available for use to system software. */
2508	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2509	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2510	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2511	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2512	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2513	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2514	#define X86_PDPE_LM_NX RT_BIT_64(63)
2515	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2516	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2517	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2518	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2519	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2520	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2521	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2522	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2523
2524
2525	/**
2526	* Page directory pointer table entry.
2527	*/
2528	typedef struct X86PDPEBITS
2529	{
2530	/** Flags whether(=1) or not the page is present. */
2531	uint32_t u1Present : 1;
2532	/** Chunk of reserved bits. */
2533	uint32_t u2Reserved : 2;
2534	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2535	uint32_t u1WriteThru : 1;
2536	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2537	uint32_t u1CacheDisable : 1;
2538	/** Chunk of reserved bits. */
2539	uint32_t u4Reserved : 4;
2540	/** Available for use to system software. */
2541	uint32_t u3Available : 3;
2542	/** Physical Page number of the next level - Low Part. Don't use! */
2543	uint32_t u20PageNoLow : 20;
2544	/** Physical Page number of the next level - High Part. Don't use! */
2545	uint32_t u20PageNoHigh : 20;
2546	/** MBZ bits */
2547	uint32_t u12Reserved : 12;
2548	} X86PDPEBITS;
2549	#ifndef VBOX_FOR_DTRACE_LIB
2550	AssertCompileSize(X86PDPEBITS, 8);
2551	#endif
2552	/** Pointer to a page directory pointer table entry. */
2553	typedef X86PDPEBITS *PX86PTPEBITS;
2554	/** Pointer to a const page directory pointer table entry. */
2555	typedef const X86PDPEBITS *PCX86PTPEBITS;
2556
2557	/**
2558	* Page directory pointer table entry. AMD64 version
2559	*/
2560	typedef struct X86PDPEAMD64BITS
2561	{
2562	/** Flags whether(=1) or not the page is present. */
2563	uint32_t u1Present : 1;
2564	/** Read(=0) / Write(=1) flag. */
2565	uint32_t u1Write : 1;
2566	/** User(=1) / Supervisor (=0) flag. */
2567	uint32_t u1User : 1;
2568	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2569	uint32_t u1WriteThru : 1;
2570	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2571	uint32_t u1CacheDisable : 1;
2572	/** Accessed flag.
2573	* Indicates that the page have been read or written to. */
2574	uint32_t u1Accessed : 1;
2575	/** Chunk of reserved bits. */
2576	uint32_t u3Reserved : 3;
2577	/** Available for use to system software. */
2578	uint32_t u3Available : 3;
2579	/** Physical Page number of the next level - Low Part. Don't use! */
2580	uint32_t u20PageNoLow : 20;
2581	/** Physical Page number of the next level - High Part. Don't use! */
2582	uint32_t u20PageNoHigh : 20;
2583	/** MBZ bits */
2584	uint32_t u11Reserved : 11;
2585	/** No Execute flag. */
2586	uint32_t u1NoExecute : 1;
2587	} X86PDPEAMD64BITS;
2588	#ifndef VBOX_FOR_DTRACE_LIB
2589	AssertCompileSize(X86PDPEAMD64BITS, 8);
2590	#endif
2591	/** Pointer to a page directory pointer table entry. */
2592	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2593	/** Pointer to a const page directory pointer table entry. */
2594	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2595
2596	/**
2597	* Page directory pointer table entry for 1GB page. (AMD64 only)
2598	*/
2599	typedef struct X86PDPE1GB
2600	{
2601	/** 0: Flags whether(=1) or not the page is present. */
2602	uint32_t u1Present : 1;
2603	/** 1: Read(=0) / Write(=1) flag. */
2604	uint32_t u1Write : 1;
2605	/** 2: User(=1) / Supervisor (=0) flag. */
2606	uint32_t u1User : 1;
2607	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2608	uint32_t u1WriteThru : 1;
2609	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2610	uint32_t u1CacheDisable : 1;
2611	/** 5: Accessed flag.
2612	* Indicates that the page have been read or written to. */
2613	uint32_t u1Accessed : 1;
2614	/** 6: Dirty flag for 1GB pages. */
2615	uint32_t u1Dirty : 1;
2616	/** 7: Indicates 1GB page if set. */
2617	uint32_t u1Size : 1;
2618	/** 8: Global 1GB page. */
2619	uint32_t u1Global: 1;
2620	/** 9-11: Available for use to system software. */
2621	uint32_t u3Available : 3;
2622	/** 12: PAT bit for 1GB page. */
2623	uint32_t u1PAT : 1;
2624	/** 13-29: MBZ bits. */
2625	uint32_t u17Reserved : 17;
2626	/** 30-31: Physical page number - Low Part. Don't use! */
2627	uint32_t u2PageNoLow : 2;
2628	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2629	uint32_t u20PageNoHigh : 20;
2630	/** 52-62: MBZ bits */
2631	uint32_t u11Reserved : 11;
2632	/** 63: No Execute flag. */
2633	uint32_t u1NoExecute : 1;
2634	} X86PDPE1GB;
2635	#ifndef VBOX_FOR_DTRACE_LIB
2636	AssertCompileSize(X86PDPE1GB, 8);
2637	#endif
2638	/** Pointer to a page directory pointer table entry for a 1GB page. */
2639	typedef X86PDPE1GB *PX86PDPE1GB;
2640	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2641	typedef const X86PDPE1GB *PCX86PDPE1GB;
2642
2643	/**
2644	* Page directory pointer table entry.
2645	*/
2646	typedef union X86PDPE
2647	{
2648	/** Unsigned integer view. */
2649	X86PGPAEUINT u;
2650	/** Normal view. */
2651	X86PDPEBITS n;
2652	/** AMD64 view. */
2653	X86PDPEAMD64BITS lm;
2654	/** AMD64 big view. */
2655	X86PDPE1GB b;
2656	/** 8 bit unsigned integer view. */
2657	uint8_t au8[8];
2658	/** 16 bit unsigned integer view. */
2659	uint16_t au16[4];
2660	/** 32 bit unsigned integer view. */
2661	uint32_t au32[2];
2662	} X86PDPE;
2663	#ifndef VBOX_FOR_DTRACE_LIB
2664	AssertCompileSize(X86PDPE, 8);
2665	#endif
2666	/** Pointer to a page directory pointer table entry. */
2667	typedef X86PDPE *PX86PDPE;
2668	/** Pointer to a const page directory pointer table entry. */
2669	typedef const X86PDPE *PCX86PDPE;
2670
2671
2672	/**
2673	* Page directory pointer table.
2674	*/
2675	typedef struct X86PDPT
2676	{
2677	/** PDE Array. */
2678	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2679	} X86PDPT;
2680	#ifndef VBOX_FOR_DTRACE_LIB
2681	AssertCompileSize(X86PDPT, 4096);
2682	#endif
2683	/** Pointer to a page directory pointer table. */
2684	typedef X86PDPT *PX86PDPT;
2685	/** Pointer to a const page directory pointer table. */
2686	typedef const X86PDPT *PCX86PDPT;
2687
2688	/** The page shift to get the PDPT index. */
2689	#define X86_PDPT_SHIFT 30
2690	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2691	#define X86_PDPT_MASK_PAE 0x3
2692	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2693	#define X86_PDPT_MASK_AMD64 0x1ff
2694
2695	/** @} */
2696
2697
2698	/** @name Page Map Level-4 Entry (Long Mode PAE)
2699	* @{
2700	*/
2701	/** Bit 0 - P - Present bit. */
2702	#define X86_PML4E_P RT_BIT_32(0)
2703	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2704	#define X86_PML4E_RW RT_BIT_32(1)
2705	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2706	#define X86_PML4E_US RT_BIT_32(2)
2707	/** Bit 3 - PWT - Page level write thru bit. */
2708	#define X86_PML4E_PWT RT_BIT_32(3)
2709	/** Bit 4 - PCD - Page level cache disable bit. */
2710	#define X86_PML4E_PCD RT_BIT_32(4)
2711	/** Bit 5 - A - Access bit. */
2712	#define X86_PML4E_A RT_BIT_32(5)
2713	/** Bits 9-11 - - Available for use to system software. */
2714	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2715	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2716	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2717	/** Bits 8, 7 - - MBZ bits when NX is active. */
2718	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2719	/** Bits 63, 7 - - MBZ bits when no NX. */
2720	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2721	/** Bits 63 - NX - PAE - No execution flag. */
2722	#define X86_PML4E_NX RT_BIT_64(63)
2723
2724	/**
2725	* Page Map Level-4 Entry
2726	*/
2727	typedef struct X86PML4EBITS
2728	{
2729	/** Flags whether(=1) or not the page is present. */
2730	uint32_t u1Present : 1;
2731	/** Read(=0) / Write(=1) flag. */
2732	uint32_t u1Write : 1;
2733	/** User(=1) / Supervisor (=0) flag. */
2734	uint32_t u1User : 1;
2735	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2736	uint32_t u1WriteThru : 1;
2737	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2738	uint32_t u1CacheDisable : 1;
2739	/** Accessed flag.
2740	* Indicates that the page have been read or written to. */
2741	uint32_t u1Accessed : 1;
2742	/** Chunk of reserved bits. */
2743	uint32_t u3Reserved : 3;
2744	/** Available for use to system software. */
2745	uint32_t u3Available : 3;
2746	/** Physical Page number of the next level - Low Part. Don't use! */
2747	uint32_t u20PageNoLow : 20;
2748	/** Physical Page number of the next level - High Part. Don't use! */
2749	uint32_t u20PageNoHigh : 20;
2750	/** MBZ bits */
2751	uint32_t u11Reserved : 11;
2752	/** No Execute flag. */
2753	uint32_t u1NoExecute : 1;
2754	} X86PML4EBITS;
2755	#ifndef VBOX_FOR_DTRACE_LIB
2756	AssertCompileSize(X86PML4EBITS, 8);
2757	#endif
2758	/** Pointer to a page map level-4 entry. */
2759	typedef X86PML4EBITS *PX86PML4EBITS;
2760	/** Pointer to a const page map level-4 entry. */
2761	typedef const X86PML4EBITS *PCX86PML4EBITS;
2762
2763	/**
2764	* Page Map Level-4 Entry.
2765	*/
2766	typedef union X86PML4E
2767	{
2768	/** Unsigned integer view. */
2769	X86PGPAEUINT u;
2770	/** Normal view. */
2771	X86PML4EBITS n;
2772	/** 8 bit unsigned integer view. */
2773	uint8_t au8[8];
2774	/** 16 bit unsigned integer view. */
2775	uint16_t au16[4];
2776	/** 32 bit unsigned integer view. */
2777	uint32_t au32[2];
2778	} X86PML4E;
2779	#ifndef VBOX_FOR_DTRACE_LIB
2780	AssertCompileSize(X86PML4E, 8);
2781	#endif
2782	/** Pointer to a page map level-4 entry. */
2783	typedef X86PML4E *PX86PML4E;
2784	/** Pointer to a const page map level-4 entry. */
2785	typedef const X86PML4E *PCX86PML4E;
2786
2787
2788	/**
2789	* Page Map Level-4.
2790	*/
2791	typedef struct X86PML4
2792	{
2793	/** PDE Array. */
2794	X86PML4E a[X86_PG_PAE_ENTRIES];
2795	} X86PML4;
2796	#ifndef VBOX_FOR_DTRACE_LIB
2797	AssertCompileSize(X86PML4, 4096);
2798	#endif
2799	/** Pointer to a page map level-4. */
2800	typedef X86PML4 *PX86PML4;
2801	/** Pointer to a const page map level-4. */
2802	typedef const X86PML4 *PCX86PML4;
2803
2804	/** The page shift to get the PML4 index. */
2805	#define X86_PML4_SHIFT 39
2806	/** The PML4 index mask (apply to a shifted page address). */
2807	#define X86_PML4_MASK 0x1ff
2808
2809	/** @} */
2810
2811	/** @} */
2812
2813	/**
2814	* Intel PCID invalidation types.
2815	*/
2816	/** Individual address invalidation. */
2817	#define X86_INVPCID_TYPE_INDV_ADDR 0
2818	/** Single-context invalidation. */
2819	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2820	/** All-context including globals invalidation. */
2821	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2822	/** All-context excluding globals invalidation. */
2823	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2824	/** The maximum valid invalidation type value. */
2825	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2826
2827	/**
2828	* 32-bit protected mode FSTENV image.
2829	*/
2830	typedef struct X86FSTENV32P
2831	{
2832	uint16_t FCW;
2833	uint16_t padding1;
2834	uint16_t FSW;
2835	uint16_t padding2;
2836	uint16_t FTW;
2837	uint16_t padding3;
2838	uint32_t FPUIP;
2839	uint16_t FPUCS;
2840	uint16_t FOP;
2841	uint32_t FPUDP;
2842	uint16_t FPUDS;
2843	uint16_t padding4;
2844	} X86FSTENV32P;
2845	/** Pointer to a 32-bit protected mode FSTENV image. */
2846	typedef X86FSTENV32P *PX86FSTENV32P;
2847	/** Pointer to a const 32-bit protected mode FSTENV image. */
2848	typedef X86FSTENV32P const *PCX86FSTENV32P;
2849
2850
2851	/**
2852	* 80-bit MMX/FPU register type.
2853	*/
2854	typedef struct X86FPUMMX
2855	{
2856	uint8_t reg[10];
2857	} X86FPUMMX;
2858	#ifndef VBOX_FOR_DTRACE_LIB
2859	AssertCompileSize(X86FPUMMX, 10);
2860	#endif
2861	/** Pointer to a 80-bit MMX/FPU register type. */
2862	typedef X86FPUMMX *PX86FPUMMX;
2863	/** Pointer to a const 80-bit MMX/FPU register type. */
2864	typedef const X86FPUMMX *PCX86FPUMMX;
2865
2866	/** FPU (x87) register. */
2867	typedef union X86FPUREG
2868	{
2869	/** MMX view. */
2870	uint64_t mmx;
2871	/** FPU view - todo. */
2872	X86FPUMMX fpu;
2873	/** Extended precision floating point view. */
2874	RTFLOAT80U r80;
2875	/** Extended precision floating point view v2 */
2876	RTFLOAT80U2 r80Ex;
2877	/** 8-bit view. */
2878	uint8_t au8[16];
2879	/** 16-bit view. */
2880	uint16_t au16[8];
2881	/** 32-bit view. */
2882	uint32_t au32[4];
2883	/** 64-bit view. */
2884	uint64_t au64[2];
2885	/** 128-bit view. (yeah, very helpful) */
2886	uint128_t au128[1];
2887	} X86FPUREG;
2888	#ifndef VBOX_FOR_DTRACE_LIB
2889	AssertCompileSize(X86FPUREG, 16);
2890	#endif
2891	/** Pointer to a FPU register. */
2892	typedef X86FPUREG *PX86FPUREG;
2893	/** Pointer to a const FPU register. */
2894	typedef X86FPUREG const *PCX86FPUREG;
2895
2896	/**
2897	* XMM register union.
2898	*/
2899	typedef union X86XMMREG
2900	{
2901	/** XMM Register view. */
2902	uint128_t xmm;
2903	/** 8-bit view. */
2904	uint8_t au8[16];
2905	/** 16-bit view. */
2906	uint16_t au16[8];
2907	/** 32-bit view. */
2908	uint32_t au32[4];
2909	/** 64-bit view. */
2910	uint64_t au64[2];
2911	/** 128-bit view. (yeah, very helpful) */
2912	uint128_t au128[1];
2913	#ifndef VBOX_FOR_DTRACE_LIB
2914	/** Confusing nested 128-bit union view (this is what xmm should've been). */
2915	RTUINT128U uXmm;
2916	#endif
2917	} X86XMMREG;
2918	#ifndef VBOX_FOR_DTRACE_LIB
2919	AssertCompileSize(X86XMMREG, 16);
2920	#endif
2921	/** Pointer to an XMM register state. */
2922	typedef X86XMMREG *PX86XMMREG;
2923	/** Pointer to a const XMM register state. */
2924	typedef X86XMMREG const *PCX86XMMREG;
2925
2926	/**
2927	* YMM register union.
2928	*/
2929	typedef union X86YMMREG
2930	{
2931	/** 8-bit view. */
2932	uint8_t au8[32];
2933	/** 16-bit view. */
2934	uint16_t au16[16];
2935	/** 32-bit view. */
2936	uint32_t au32[8];
2937	/** 64-bit view. */
2938	uint64_t au64[4];
2939	/** 128-bit view. (yeah, very helpful) */
2940	uint128_t au128[2];
2941	/** XMM sub register view. */
2942	X86XMMREG aXmm[2];
2943	} X86YMMREG;
2944	#ifndef VBOX_FOR_DTRACE_LIB
2945	AssertCompileSize(X86YMMREG, 32);
2946	#endif
2947	/** Pointer to an YMM register state. */
2948	typedef X86YMMREG *PX86YMMREG;
2949	/** Pointer to a const YMM register state. */
2950	typedef X86YMMREG const *PCX86YMMREG;
2951
2952	/**
2953	* ZMM register union.
2954	*/
2955	typedef union X86ZMMREG
2956	{
2957	/** 8-bit view. */
2958	uint8_t au8[64];
2959	/** 16-bit view. */
2960	uint16_t au16[32];
2961	/** 32-bit view. */
2962	uint32_t au32[16];
2963	/** 64-bit view. */
2964	uint64_t au64[8];
2965	/** 128-bit view. (yeah, very helpful) */
2966	uint128_t au128[4];
2967	/** XMM sub register view. */
2968	X86XMMREG aXmm[4];
2969	/** YMM sub register view. */
2970	X86YMMREG aYmm[2];
2971	} X86ZMMREG;
2972	#ifndef VBOX_FOR_DTRACE_LIB
2973	AssertCompileSize(X86ZMMREG, 64);
2974	#endif
2975	/** Pointer to an ZMM register state. */
2976	typedef X86ZMMREG *PX86ZMMREG;
2977	/** Pointer to a const ZMM register state. */
2978	typedef X86ZMMREG const *PCX86ZMMREG;
2979
2980
2981	/**
2982	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2983	* @todo verify this...
2984	*/
2985	#pragma pack(1)
2986	typedef struct X86FPUSTATE
2987	{
2988	/** 0x00 - Control word. */
2989	uint16_t FCW;
2990	/** 0x02 - Alignment word */
2991	uint16_t Dummy1;
2992	/** 0x04 - Status word. */
2993	uint16_t FSW;
2994	/** 0x06 - Alignment word */
2995	uint16_t Dummy2;
2996	/** 0x08 - Tag word */
2997	uint16_t FTW;
2998	/** 0x0a - Alignment word */
2999	uint16_t Dummy3;
3000
3001	/** 0x0c - Instruction pointer. */
3002	uint32_t FPUIP;
3003	/** 0x10 - Code selector. */
3004	uint16_t CS;
3005	/** 0x12 - Opcode. */
3006	uint16_t FOP;
3007	/** 0x14 - FOO. */
3008	uint32_t FPUOO;
3009	/** 0x18 - FOS. */
3010	uint32_t FPUOS;
3011	/** 0x1c - FPU register. */
3012	X86FPUREG regs[8];
3013	} X86FPUSTATE;
3014	#pragma pack()
3015	/** Pointer to a FPU state. */
3016	typedef X86FPUSTATE *PX86FPUSTATE;
3017	/** Pointer to a const FPU state. */
3018	typedef const X86FPUSTATE *PCX86FPUSTATE;
3019
3020	/**
3021	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3022	*/
3023	#pragma pack(1)
3024	typedef struct X86FXSTATE
3025	{
3026	/** 0x00 - Control word. */
3027	uint16_t FCW;
3028	/** 0x02 - Status word. */
3029	uint16_t FSW;
3030	/** 0x04 - Tag word. (The upper byte is always zero.) */
3031	uint16_t FTW;
3032	/** 0x06 - Opcode. */
3033	uint16_t FOP;
3034	/** 0x08 - Instruction pointer. */
3035	uint32_t FPUIP;
3036	/** 0x0c - Code selector. */
3037	uint16_t CS;
3038	uint16_t Rsrvd1;
3039	/** 0x10 - Data pointer. */
3040	uint32_t FPUDP;
3041	/** 0x14 - Data segment */
3042	uint16_t DS;
3043	/** 0x16 */
3044	uint16_t Rsrvd2;
3045	/** 0x18 */
3046	uint32_t MXCSR;
3047	/** 0x1c */
3048	uint32_t MXCSR_MASK;
3049	/** 0x20 - FPU registers. */
3050	X86FPUREG aRegs[8];
3051	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3052	X86XMMREG aXMM[16];
3053	/* - offset 416 - */
3054	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3055	/* - offset 464 - Software usable reserved bits. */
3056	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3057	} X86FXSTATE;
3058	#pragma pack()
3059	/** Pointer to a FPU Extended state. */
3060	typedef X86FXSTATE *PX86FXSTATE;
3061	/** Pointer to a const FPU Extended state. */
3062	typedef const X86FXSTATE *PCX86FXSTATE;
3063
3064	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3065	* magic. Don't forget to update x86.mac if you change this! */
3066	#define X86_OFF_FXSTATE_RSVD 0x1d0
3067	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3068	* forget to update x86.mac if you change this!
3069	* @todo r=bird: This has nothing what-so-ever to do here.... */
3070	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3071	#ifndef VBOX_FOR_DTRACE_LIB
3072	AssertCompileSize(X86FXSTATE, 512);
3073	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3074	#endif
3075
3076	/** @name FPU status word flags.
3077	* @{ */
3078	/** Exception Flag: Invalid operation. */
3079	#define X86_FSW_IE RT_BIT_32(0)
3080	/** Exception Flag: Denormalized operand. */
3081	#define X86_FSW_DE RT_BIT_32(1)
3082	/** Exception Flag: Zero divide. */
3083	#define X86_FSW_ZE RT_BIT_32(2)
3084	/** Exception Flag: Overflow. */
3085	#define X86_FSW_OE RT_BIT_32(3)
3086	/** Exception Flag: Underflow. */
3087	#define X86_FSW_UE RT_BIT_32(4)
3088	/** Exception Flag: Precision. */
3089	#define X86_FSW_PE RT_BIT_32(5)
3090	/** Stack fault. */
3091	#define X86_FSW_SF RT_BIT_32(6)
3092	/** Error summary status. */
3093	#define X86_FSW_ES RT_BIT_32(7)
3094	/** Mask of exceptions flags, excluding the summary bit. */
3095	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3096	/** Mask of exceptions flags, including the summary bit. */
3097	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3098	/** Condition code 0. */
3099	#define X86_FSW_C0 RT_BIT_32(8)
3100	/** Condition code 1. */
3101	#define X86_FSW_C1 RT_BIT_32(9)
3102	/** Condition code 2. */
3103	#define X86_FSW_C2 RT_BIT_32(10)
3104	/** Top of the stack mask. */
3105	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3106	/** TOP shift value. */
3107	#define X86_FSW_TOP_SHIFT 11
3108	/** Mask for getting TOP value after shifting it right. */
3109	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3110	/** Get the TOP value. */
3111	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3112	/** Condition code 3. */
3113	#define X86_FSW_C3 RT_BIT_32(14)
3114	/** Mask of exceptions flags, including the summary bit. */
3115	#define X86_FSW_C_MASK UINT16_C(0x4700)
3116	/** FPU busy. */
3117	#define X86_FSW_B RT_BIT_32(15)
3118	/** @} */
3119
3120
3121	/** @name FPU control word flags.
3122	* @{ */
3123	/** Exception Mask: Invalid operation. */
3124	#define X86_FCW_IM RT_BIT_32(0)
3125	/** Exception Mask: Denormalized operand. */
3126	#define X86_FCW_DM RT_BIT_32(1)
3127	/** Exception Mask: Zero divide. */
3128	#define X86_FCW_ZM RT_BIT_32(2)
3129	/** Exception Mask: Overflow. */
3130	#define X86_FCW_OM RT_BIT_32(3)
3131	/** Exception Mask: Underflow. */
3132	#define X86_FCW_UM RT_BIT_32(4)
3133	/** Exception Mask: Precision. */
3134	#define X86_FCW_PM RT_BIT_32(5)
3135	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3136	* @remarks This includes reserved bit 6. */
3137	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3138	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3139	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3140	/** Precision control mask. */
3141	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3142	/** Precision control: 24-bit. */
3143	#define X86_FCW_PC_24 UINT16_C(0x0000)
3144	/** Precision control: Reserved. */
3145	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3146	/** Precision control: 53-bit. */
3147	#define X86_FCW_PC_53 UINT16_C(0x0200)
3148	/** Precision control: 64-bit. */
3149	#define X86_FCW_PC_64 UINT16_C(0x0300)
3150	/** Rounding control mask. */
3151	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3152	/** Rounding control: To nearest. */
3153	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3154	/** Rounding control: Down. */
3155	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3156	/** Rounding control: Up. */
3157	#define X86_FCW_RC_UP UINT16_C(0x0800)
3158	/** Rounding control: Towards zero. */
3159	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3160	/** Bits which should be zero, apparently. */
3161	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3162	/** @} */
3163
3164	/** @name SSE MXCSR
3165	* @{ */
3166	/** Exception Flag: Invalid operation. */
3167	#define X86_MXCSR_IE RT_BIT_32(0)
3168	/** Exception Flag: Denormalized operand. */
3169	#define X86_MXCSR_DE RT_BIT_32(1)
3170	/** Exception Flag: Zero divide. */
3171	#define X86_MXCSR_ZE RT_BIT_32(2)
3172	/** Exception Flag: Overflow. */
3173	#define X86_MXCSR_OE RT_BIT_32(3)
3174	/** Exception Flag: Underflow. */
3175	#define X86_MXCSR_UE RT_BIT_32(4)
3176	/** Exception Flag: Precision. */
3177	#define X86_MXCSR_PE RT_BIT_32(5)
3178
3179	/** Denormals are zero. */
3180	#define X86_MXCSR_DAZ RT_BIT_32(6)
3181
3182	/** Exception Mask: Invalid operation. */
3183	#define X86_MXCSR_IM RT_BIT_32(7)
3184	/** Exception Mask: Denormalized operand. */
3185	#define X86_MXCSR_DM RT_BIT_32(8)
3186	/** Exception Mask: Zero divide. */
3187	#define X86_MXCSR_ZM RT_BIT_32(9)
3188	/** Exception Mask: Overflow. */
3189	#define X86_MXCSR_OM RT_BIT_32(10)
3190	/** Exception Mask: Underflow. */
3191	#define X86_MXCSR_UM RT_BIT_32(11)
3192	/** Exception Mask: Precision. */
3193	#define X86_MXCSR_PM RT_BIT_32(12)
3194
3195	/** Rounding control mask. */
3196	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3197	/** Rounding control: To nearest. */
3198	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3199	/** Rounding control: Down. */
3200	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3201	/** Rounding control: Up. */
3202	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3203	/** Rounding control: Towards zero. */
3204	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3205
3206	/** Flush-to-zero for masked underflow. */
3207	#define X86_MXCSR_FZ RT_BIT_32(15)
3208
3209	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3210	#define X86_MXCSR_MM RT_BIT_32(17)
3211	/** @} */
3212
3213	/**
3214	* XSAVE header.
3215	*/
3216	typedef struct X86XSAVEHDR
3217	{
3218	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3219	uint64_t bmXState;
3220	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3221	uint64_t bmXComp;
3222	/** Reserved for furture extensions, probably MBZ. */
3223	uint64_t au64Reserved[6];
3224	} X86XSAVEHDR;
3225	#ifndef VBOX_FOR_DTRACE_LIB
3226	AssertCompileSize(X86XSAVEHDR, 64);
3227	#endif
3228	/** Pointer to an XSAVE header. */
3229	typedef X86XSAVEHDR *PX86XSAVEHDR;
3230	/** Pointer to a const XSAVE header. */
3231	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3232
3233
3234	/**
3235	* The high 128-bit YMM register state (XSAVE_C_YMM).
3236	* (The lower 128-bits being in X86FXSTATE.)
3237	*/
3238	typedef struct X86XSAVEYMMHI
3239	{
3240	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3241	X86XMMREG aYmmHi[16];
3242	} X86XSAVEYMMHI;
3243	#ifndef VBOX_FOR_DTRACE_LIB
3244	AssertCompileSize(X86XSAVEYMMHI, 256);
3245	#endif
3246	/** Pointer to a high 128-bit YMM register state. */
3247	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3248	/** Pointer to a const high 128-bit YMM register state. */
3249	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3250
3251	/**
3252	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3253	*/
3254	typedef struct X86XSAVEBNDREGS
3255	{
3256	/** Array of registers (BND0...BND3). */
3257	struct
3258	{
3259	/** Lower bound. */
3260	uint64_t uLowerBound;
3261	/** Upper bound. */
3262	uint64_t uUpperBound;
3263	} aRegs[4];
3264	} X86XSAVEBNDREGS;
3265	#ifndef VBOX_FOR_DTRACE_LIB
3266	AssertCompileSize(X86XSAVEBNDREGS, 64);
3267	#endif
3268	/** Pointer to a MPX bound register state. */
3269	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3270	/** Pointer to a const MPX bound register state. */
3271	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3272
3273	/**
3274	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3275	*/
3276	typedef struct X86XSAVEBNDCFG
3277	{
3278	uint64_t fConfig;
3279	uint64_t fStatus;
3280	} X86XSAVEBNDCFG;
3281	#ifndef VBOX_FOR_DTRACE_LIB
3282	AssertCompileSize(X86XSAVEBNDCFG, 16);
3283	#endif
3284	/** Pointer to a MPX bound config and status register state. */
3285	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3286	/** Pointer to a const MPX bound config and status register state. */
3287	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3288
3289	/**
3290	* AVX-512 opmask state (XSAVE_C_OPMASK).
3291	*/
3292	typedef struct X86XSAVEOPMASK
3293	{
3294	/** The K0..K7 values. */
3295	uint64_t aKRegs[8];
3296	} X86XSAVEOPMASK;
3297	#ifndef VBOX_FOR_DTRACE_LIB
3298	AssertCompileSize(X86XSAVEOPMASK, 64);
3299	#endif
3300	/** Pointer to a AVX-512 opmask state. */
3301	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3302	/** Pointer to a const AVX-512 opmask state. */
3303	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3304
3305	/**
3306	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3307	*/
3308	typedef struct X86XSAVEZMMHI256
3309	{
3310	/** Upper 256-bits of ZMM0-15. */
3311	X86YMMREG aHi256Regs[16];
3312	} X86XSAVEZMMHI256;
3313	#ifndef VBOX_FOR_DTRACE_LIB
3314	AssertCompileSize(X86XSAVEZMMHI256, 512);
3315	#endif
3316	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3317	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3318	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3319	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3320
3321	/**
3322	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3323	*/
3324	typedef struct X86XSAVEZMM16HI
3325	{
3326	/** ZMM16 thru ZMM31. */
3327	X86ZMMREG aRegs[16];
3328	} X86XSAVEZMM16HI;
3329	#ifndef VBOX_FOR_DTRACE_LIB
3330	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3331	#endif
3332	/** Pointer to a state comprising ZMM16-32. */
3333	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3334	/** Pointer to a const state comprising ZMM16-32. */
3335	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3336
3337	/**
3338	* AMD Light weight profiling state (XSAVE_C_LWP).
3339	*
3340	* We probably won't play with this as AMD seems to be dropping from their "zen"
3341	* processor micro architecture.
3342	*/
3343	typedef struct X86XSAVELWP
3344	{
3345	/** Details when needed. */
3346	uint64_t auLater[128/8];
3347	} X86XSAVELWP;
3348	#ifndef VBOX_FOR_DTRACE_LIB
3349	AssertCompileSize(X86XSAVELWP, 128);
3350	#endif
3351
3352
3353	/**
3354	* x86 FPU/SSE/AVX/XXXX state.
3355	*
3356	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3357	* changes to this structure.
3358	*/
3359	typedef struct X86XSAVEAREA
3360	{
3361	/** The x87 and SSE region (or legacy region if you like). */
3362	X86FXSTATE x87;
3363	/** The XSAVE header. */
3364	X86XSAVEHDR Hdr;
3365	/** Beyond the header, there isn't really a fixed layout, but we can
3366	generally assume the YMM (AVX) register extensions are present and
3367	follows immediately. */
3368	union
3369	{
3370	/** The high 128-bit AVX registers for easy access by IEM.
3371	* @note This ASSUMES they will always be here... */
3372	X86XSAVEYMMHI YmmHi;
3373
3374	/** This is a typical layout on intel CPUs (good for debuggers). */
3375	struct
3376	{
3377	X86XSAVEYMMHI YmmHi;
3378	X86XSAVEBNDREGS BndRegs;
3379	X86XSAVEBNDCFG BndCfg;
3380	uint8_t abFudgeToMatchDocs[0xB0];
3381	X86XSAVEOPMASK Opmask;
3382	X86XSAVEZMMHI256 ZmmHi256;
3383	X86XSAVEZMM16HI Zmm16Hi;
3384	} Intel;
3385
3386	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3387	struct
3388	{
3389	X86XSAVEYMMHI YmmHi;
3390	X86XSAVELWP Lwp;
3391	} AmdBd;
3392
3393	/** To enbling static deployments that have a reasonable chance of working for
3394	* the next 3-6 CPU generations without running short on space, we allocate a
3395	* lot of extra space here, making the structure a round 8KB in size. This
3396	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3397	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3398	uint8_t ab[8192 - 512 - 64];
3399	} u;
3400	} X86XSAVEAREA;
3401	#ifndef VBOX_FOR_DTRACE_LIB
3402	AssertCompileSize(X86XSAVEAREA, 8192);
3403	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3404	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3405	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3406	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3407	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3408	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3409	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3410	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3411	#endif
3412	/** Pointer to a XSAVE area. */
3413	typedef X86XSAVEAREA *PX86XSAVEAREA;
3414	/** Pointer to a const XSAVE area. */
3415	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3416
3417
3418	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3419	* @{ */
3420	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3421	#define XSAVE_C_X87_BIT 0
3422	/** Bit 0 - x87 - Legacy FPU state. */
3423	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3424	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3425	#define XSAVE_C_SSE_BIT 1
3426	/** Bit 1 - SSE - 128-bit SSE state. */
3427	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3428	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3429	#define XSAVE_C_YMM_BIT 2
3430	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3431	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3432	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3433	#define XSAVE_C_BNDREGS_BIT 3
3434	/** Bit 3 - BNDREGS - MPX bound register state. */
3435	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3436	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3437	#define XSAVE_C_BNDCSR_BIT 4
3438	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3439	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3440	/** Bit 5 - Opmask - opmask state (bit number). */
3441	#define XSAVE_C_OPMASK_BIT 5
3442	/** Bit 5 - Opmask - opmask state. */
3443	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3444	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3445	#define XSAVE_C_ZMM_HI256_BIT 6
3446	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3447	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3448	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3449	#define XSAVE_C_ZMM_16HI_BIT 7
3450	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3451	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3452	/** Bit 9 - PKRU - Protection-key state (bit number). */
3453	#define XSAVE_C_PKRU_BIT 9
3454	/** Bit 9 - PKRU - Protection-key state. */
3455	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3456	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3457	#define XSAVE_C_LWP_BIT 62
3458	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3459	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3460	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3461	#define XSAVE_C_X_BIT 63
3462	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3463	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3464	/** @} */
3465
3466
3467
3468	/** @name Selector Descriptor
3469	* @{
3470	*/
3471
3472	#ifndef VBOX_FOR_DTRACE_LIB
3473	/**
3474	* Descriptor attributes (as seen by VT-x).
3475	*/
3476	typedef struct X86DESCATTRBITS
3477	{
3478	/** 00 - Segment Type. */
3479	unsigned u4Type : 4;
3480	/** 04 - Descriptor Type. System(=0) or code/data selector */
3481	unsigned u1DescType : 1;
3482	/** 05 - Descriptor Privilege level. */
3483	unsigned u2Dpl : 2;
3484	/** 07 - Flags selector present(=1) or not. */
3485	unsigned u1Present : 1;
3486	/** 08 - Segment limit 16-19. */
3487	unsigned u4LimitHigh : 4;
3488	/** 0c - Available for system software. */
3489	unsigned u1Available : 1;
3490	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3491	unsigned u1Long : 1;
3492	/** 0e - This flags meaning depends on the segment type. Try make sense out
3493	* of the intel manual yourself. */
3494	unsigned u1DefBig : 1;
3495	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3496	* clear byte. */
3497	unsigned u1Granularity : 1;
3498	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3499	unsigned u1Unusable : 1;
3500	} X86DESCATTRBITS;
3501	#endif /* !VBOX_FOR_DTRACE_LIB */
3502
3503	/** @name X86DESCATTR masks
3504	* @{ */
3505	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3506	#define X86DESCATTR_DT UINT32_C(0x00000010)
3507	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3508	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3509	#define X86DESCATTR_P UINT32_C(0x00000080)
3510	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3511	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3512	#define X86DESCATTR_L UINT32_C(0x00002000)
3513	#define X86DESCATTR_D UINT32_C(0x00004000)
3514	#define X86DESCATTR_G UINT32_C(0x00008000)
3515	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3516	/** @} */
3517
3518	#pragma pack(1)
3519	typedef union X86DESCATTR
3520	{
3521	/** Unsigned integer view. */
3522	uint32_t u;
3523	#ifndef VBOX_FOR_DTRACE_LIB
3524	/** Normal view. */
3525	X86DESCATTRBITS n;
3526	#endif
3527	} X86DESCATTR;
3528	#pragma pack()
3529	/** Pointer to descriptor attributes. */
3530	typedef X86DESCATTR *PX86DESCATTR;
3531	/** Pointer to const descriptor attributes. */
3532	typedef const X86DESCATTR *PCX86DESCATTR;
3533
3534	#ifndef VBOX_FOR_DTRACE_LIB
3535
3536	/**
3537	* Generic descriptor table entry
3538	*/
3539	#pragma pack(1)
3540	typedef struct X86DESCGENERIC
3541	{
3542	/** 00 - Limit - Low word. */
3543	unsigned u16LimitLow : 16;
3544	/** 10 - Base address - low word.
3545	* Don't try set this to 24 because MSC is doing stupid things then. */
3546	unsigned u16BaseLow : 16;
3547	/** 20 - Base address - first 8 bits of high word. */
3548	unsigned u8BaseHigh1 : 8;
3549	/** 28 - Segment Type. */
3550	unsigned u4Type : 4;
3551	/** 2c - Descriptor Type. System(=0) or code/data selector */
3552	unsigned u1DescType : 1;
3553	/** 2d - Descriptor Privilege level. */
3554	unsigned u2Dpl : 2;
3555	/** 2f - Flags selector present(=1) or not. */
3556	unsigned u1Present : 1;
3557	/** 30 - Segment limit 16-19. */
3558	unsigned u4LimitHigh : 4;
3559	/** 34 - Available for system software. */
3560	unsigned u1Available : 1;
3561	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3562	unsigned u1Long : 1;
3563	/** 36 - This flags meaning depends on the segment type. Try make sense out
3564	* of the intel manual yourself. */
3565	unsigned u1DefBig : 1;
3566	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3567	* clear byte. */
3568	unsigned u1Granularity : 1;
3569	/** 38 - Base address - highest 8 bits. */
3570	unsigned u8BaseHigh2 : 8;
3571	} X86DESCGENERIC;
3572	#pragma pack()
3573	/** Pointer to a generic descriptor entry. */
3574	typedef X86DESCGENERIC *PX86DESCGENERIC;
3575	/** Pointer to a const generic descriptor entry. */
3576	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3577
3578	/** @name Bit offsets of X86DESCGENERIC members.
3579	* @{*/
3580	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3581	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3582	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3583	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3584	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3585	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3586	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3587	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3588	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3589	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3590	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3591	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3592	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3593	/** @} */
3594
3595
3596	/** @name LAR mask
3597	* @{ */
3598	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3599	#define X86LAR_F_DT UINT16_C( 0x1000)
3600	#define X86LAR_F_DPL UINT16_C( 0x6000)
3601	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3602	#define X86LAR_F_P UINT16_C( 0x8000)
3603	#define X86LAR_F_AVL UINT32_C(0x00100000)
3604	#define X86LAR_F_L UINT32_C(0x00200000)
3605	#define X86LAR_F_D UINT32_C(0x00400000)
3606	#define X86LAR_F_G UINT32_C(0x00800000)
3607	/** @} */
3608
3609
3610	/**
3611	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3612	*/
3613	typedef struct X86DESCGATE
3614	{
3615	/** 00 - Target code segment offset - Low word.
3616	* Ignored if task-gate. */
3617	unsigned u16OffsetLow : 16;
3618	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3619	* TSS selector if task-gate. */
3620	unsigned u16Sel : 16;
3621	/** 20 - Number of parameters for a call-gate.
3622	* Ignored if interrupt-, trap- or task-gate. */
3623	unsigned u5ParmCount : 5;
3624	/** 25 - Reserved / ignored. */
3625	unsigned u3Reserved : 3;
3626	/** 28 - Segment Type. */
3627	unsigned u4Type : 4;
3628	/** 2c - Descriptor Type (0 = system). */
3629	unsigned u1DescType : 1;
3630	/** 2d - Descriptor Privilege level. */
3631	unsigned u2Dpl : 2;
3632	/** 2f - Flags selector present(=1) or not. */
3633	unsigned u1Present : 1;
3634	/** 30 - Target code segment offset - High word.
3635	* Ignored if task-gate. */
3636	unsigned u16OffsetHigh : 16;
3637	} X86DESCGATE;
3638	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3639	typedef X86DESCGATE *PX86DESCGATE;
3640	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3641	typedef const X86DESCGATE *PCX86DESCGATE;
3642
3643	#endif /* VBOX_FOR_DTRACE_LIB */
3644
3645	/**
3646	* Descriptor table entry.
3647	*/
3648	#pragma pack(1)
3649	typedef union X86DESC
3650	{
3651	#ifndef VBOX_FOR_DTRACE_LIB
3652	/** Generic descriptor view. */
3653	X86DESCGENERIC Gen;
3654	/** Gate descriptor view. */
3655	X86DESCGATE Gate;
3656	#endif
3657
3658	/** 8 bit unsigned integer view. */
3659	uint8_t au8[8];
3660	/** 16 bit unsigned integer view. */
3661	uint16_t au16[4];
3662	/** 32 bit unsigned integer view. */
3663	uint32_t au32[2];
3664	/** 64 bit unsigned integer view. */
3665	uint64_t au64[1];
3666	/** Unsigned integer view. */
3667	uint64_t u;
3668	} X86DESC;
3669	#ifndef VBOX_FOR_DTRACE_LIB
3670	AssertCompileSize(X86DESC, 8);
3671	#endif
3672	#pragma pack()
3673	/** Pointer to descriptor table entry. */
3674	typedef X86DESC *PX86DESC;
3675	/** Pointer to const descriptor table entry. */
3676	typedef const X86DESC *PCX86DESC;
3677
3678	/** @def X86DESC_BASE
3679	* Return the base address of a descriptor.
3680	*/
3681	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3682	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3683	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3684	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3685
3686	/** @def X86DESC_LIMIT
3687	* Return the limit of a descriptor.
3688	*/
3689	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3690	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3691	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3692
3693	/** @def X86DESC_LIMIT_G
3694	* Return the limit of a descriptor with the granularity bit taken into account.
3695	* @returns Selector limit (uint32_t).
3696	* @param a_pDesc Pointer to the descriptor.
3697	*/
3698	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3699	( (a_pDesc)->Gen.u1Granularity \
3700	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3701	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3702	)
3703
3704	/** @def X86DESC_GET_HID_ATTR
3705	* Get the descriptor attributes for the hidden register.
3706	*/
3707	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3708	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3709
3710	#ifndef VBOX_FOR_DTRACE_LIB
3711
3712	/**
3713	* 64 bits generic descriptor table entry
3714	* Note: most of these bits have no meaning in long mode.
3715	*/
3716	#pragma pack(1)
3717	typedef struct X86DESC64GENERIC
3718	{
3719	/** Limit - Low word - IGNORED. */
3720	uint32_t u16LimitLow : 16;
3721	/** Base address - low word. - IGNORED
3722	* Don't try set this to 24 because MSC is doing stupid things then. */
3723	uint32_t u16BaseLow : 16;
3724	/** Base address - first 8 bits of high word. - IGNORED */
3725	uint32_t u8BaseHigh1 : 8;
3726	/** Segment Type. */
3727	uint32_t u4Type : 4;
3728	/** Descriptor Type. System(=0) or code/data selector */
3729	uint32_t u1DescType : 1;
3730	/** Descriptor Privilege level. */
3731	uint32_t u2Dpl : 2;
3732	/** Flags selector present(=1) or not. */
3733	uint32_t u1Present : 1;
3734	/** Segment limit 16-19. - IGNORED */
3735	uint32_t u4LimitHigh : 4;
3736	/** Available for system software. - IGNORED */
3737	uint32_t u1Available : 1;
3738	/** Long mode flag. */
3739	uint32_t u1Long : 1;
3740	/** This flags meaning depends on the segment type. Try make sense out
3741	* of the intel manual yourself. */
3742	uint32_t u1DefBig : 1;
3743	/** Granularity of the limit. If set 4KB granularity is used, if
3744	* clear byte. - IGNORED */
3745	uint32_t u1Granularity : 1;
3746	/** Base address - highest 8 bits. - IGNORED */
3747	uint32_t u8BaseHigh2 : 8;
3748	/** Base address - bits 63-32. */
3749	uint32_t u32BaseHigh3 : 32;
3750	uint32_t u8Reserved : 8;
3751	uint32_t u5Zeros : 5;
3752	uint32_t u19Reserved : 19;
3753	} X86DESC64GENERIC;
3754	#pragma pack()
3755	/** Pointer to a generic descriptor entry. */
3756	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3757	/** Pointer to a const generic descriptor entry. */
3758	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3759
3760	/**
3761	* System descriptor table entry (64 bits)
3762	*
3763	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3764	*/
3765	#pragma pack(1)
3766	typedef struct X86DESC64SYSTEM
3767	{
3768	/** Limit - Low word. */
3769	uint32_t u16LimitLow : 16;
3770	/** Base address - low word.
3771	* Don't try set this to 24 because MSC is doing stupid things then. */
3772	uint32_t u16BaseLow : 16;
3773	/** Base address - first 8 bits of high word. */
3774	uint32_t u8BaseHigh1 : 8;
3775	/** Segment Type. */
3776	uint32_t u4Type : 4;
3777	/** Descriptor Type. System(=0) or code/data selector */
3778	uint32_t u1DescType : 1;
3779	/** Descriptor Privilege level. */
3780	uint32_t u2Dpl : 2;
3781	/** Flags selector present(=1) or not. */
3782	uint32_t u1Present : 1;
3783	/** Segment limit 16-19. */
3784	uint32_t u4LimitHigh : 4;
3785	/** Available for system software. */
3786	uint32_t u1Available : 1;
3787	/** Reserved - 0. */
3788	uint32_t u1Reserved : 1;
3789	/** This flags meaning depends on the segment type. Try make sense out
3790	* of the intel manual yourself. */
3791	uint32_t u1DefBig : 1;
3792	/** Granularity of the limit. If set 4KB granularity is used, if
3793	* clear byte. */
3794	uint32_t u1Granularity : 1;
3795	/** Base address - bits 31-24. */
3796	uint32_t u8BaseHigh2 : 8;
3797	/** Base address - bits 63-32. */
3798	uint32_t u32BaseHigh3 : 32;
3799	uint32_t u8Reserved : 8;
3800	uint32_t u5Zeros : 5;
3801	uint32_t u19Reserved : 19;
3802	} X86DESC64SYSTEM;
3803	#pragma pack()
3804	/** Pointer to a system descriptor entry. */
3805	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3806	/** Pointer to a const system descriptor entry. */
3807	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3808
3809	/**
3810	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3811	*/
3812	typedef struct X86DESC64GATE
3813	{
3814	/** Target code segment offset - Low word. */
3815	uint32_t u16OffsetLow : 16;
3816	/** Target code segment selector. */
3817	uint32_t u16Sel : 16;
3818	/** Interrupt stack table for interrupt- and trap-gates.
3819	* Ignored by call-gates. */
3820	uint32_t u3IST : 3;
3821	/** Reserved / ignored. */
3822	uint32_t u5Reserved : 5;
3823	/** Segment Type. */
3824	uint32_t u4Type : 4;
3825	/** Descriptor Type (0 = system). */
3826	uint32_t u1DescType : 1;
3827	/** Descriptor Privilege level. */
3828	uint32_t u2Dpl : 2;
3829	/** Flags selector present(=1) or not. */
3830	uint32_t u1Present : 1;
3831	/** Target code segment offset - High word.
3832	* Ignored if task-gate. */
3833	uint32_t u16OffsetHigh : 16;
3834	/** Target code segment offset - Top dword.
3835	* Ignored if task-gate. */
3836	uint32_t u32OffsetTop : 32;
3837	/** Reserved / ignored / must be zero.
3838	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3839	uint32_t u32Reserved : 32;
3840	} X86DESC64GATE;
3841	AssertCompileSize(X86DESC64GATE, 16);
3842	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3843	typedef X86DESC64GATE *PX86DESC64GATE;
3844	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3845	typedef const X86DESC64GATE *PCX86DESC64GATE;
3846
3847	#endif /* VBOX_FOR_DTRACE_LIB */
3848
3849	/**
3850	* Descriptor table entry.
3851	*/
3852	#pragma pack(1)
3853	typedef union X86DESC64
3854	{
3855	#ifndef VBOX_FOR_DTRACE_LIB
3856	/** Generic descriptor view. */
3857	X86DESC64GENERIC Gen;
3858	/** System descriptor view. */
3859	X86DESC64SYSTEM System;
3860	/** Gate descriptor view. */
3861	X86DESC64GATE Gate;
3862	#endif
3863
3864	/** 8 bit unsigned integer view. */
3865	uint8_t au8[16];
3866	/** 16 bit unsigned integer view. */
3867	uint16_t au16[8];
3868	/** 32 bit unsigned integer view. */
3869	uint32_t au32[4];
3870	/** 64 bit unsigned integer view. */
3871	uint64_t au64[2];
3872	} X86DESC64;
3873	#ifndef VBOX_FOR_DTRACE_LIB
3874	AssertCompileSize(X86DESC64, 16);
3875	#endif
3876	#pragma pack()
3877	/** Pointer to descriptor table entry. */
3878	typedef X86DESC64 *PX86DESC64;
3879	/** Pointer to const descriptor table entry. */
3880	typedef const X86DESC64 *PCX86DESC64;
3881
3882	/** @def X86DESC64_BASE
3883	* Return the base of a 64-bit descriptor.
3884	*/
3885	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3886	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3887	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3888	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3889	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3890
3891
3892
3893	/** @name Host system descriptor table entry - Use with care!
3894	* @{ */
3895	/** Host system descriptor table entry. */
3896	#if HC_ARCH_BITS == 64
3897	typedef X86DESC64 X86DESCHC;
3898	#else
3899	typedef X86DESC X86DESCHC;
3900	#endif
3901	/** Pointer to a host system descriptor table entry. */
3902	#if HC_ARCH_BITS == 64
3903	typedef PX86DESC64 PX86DESCHC;
3904	#else
3905	typedef PX86DESC PX86DESCHC;
3906	#endif
3907	/** Pointer to a const host system descriptor table entry. */
3908	#if HC_ARCH_BITS == 64
3909	typedef PCX86DESC64 PCX86DESCHC;
3910	#else
3911	typedef PCX86DESC PCX86DESCHC;
3912	#endif
3913	/** @} */
3914
3915
3916	/** @name Selector Descriptor Types.
3917	* @{
3918	*/
3919
3920	/** @name Non-System Selector Types.
3921	* @{ */
3922	/** Code(=set)/Data(=clear) bit. */
3923	#define X86_SEL_TYPE_CODE 8
3924	/** Memory(=set)/System(=clear) bit. */
3925	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3926	/** Accessed bit. */
3927	#define X86_SEL_TYPE_ACCESSED 1
3928	/** Expand down bit (for data selectors only). */
3929	#define X86_SEL_TYPE_DOWN 4
3930	/** Conforming bit (for code selectors only). */
3931	#define X86_SEL_TYPE_CONF 4
3932	/** Write bit (for data selectors only). */
3933	#define X86_SEL_TYPE_WRITE 2
3934	/** Read bit (for code selectors only). */
3935	#define X86_SEL_TYPE_READ 2
3936	/** The bit number of the code segment read bit (relative to u4Type). */
3937	#define X86_SEL_TYPE_READ_BIT 1
3938
3939	/** Read only selector type. */
3940	#define X86_SEL_TYPE_RO 0
3941	/** Accessed read only selector type. */
3942	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3943	/** Read write selector type. */
3944	#define X86_SEL_TYPE_RW 2
3945	/** Accessed read write selector type. */
3946	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3947	/** Expand down read only selector type. */
3948	#define X86_SEL_TYPE_RO_DOWN 4
3949	/** Accessed expand down read only selector type. */
3950	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3951	/** Expand down read write selector type. */
3952	#define X86_SEL_TYPE_RW_DOWN 6
3953	/** Accessed expand down read write selector type. */
3954	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3955	/** Execute only selector type. */
3956	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3957	/** Accessed execute only selector type. */
3958	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3959	/** Execute and read selector type. */
3960	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3961	/** Accessed execute and read selector type. */
3962	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3963	/** Conforming execute only selector type. */
3964	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3965	/** Accessed Conforming execute only selector type. */
3966	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3967	/** Conforming execute and write selector type. */
3968	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3969	/** Accessed Conforming execute and write selector type. */
3970	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3971	/** @} */
3972
3973
3974	/** @name System Selector Types.
3975	* @{ */
3976	/** The TSS busy bit mask. */
3977	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3978
3979	/** Undefined system selector type. */
3980	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3981	/** 286 TSS selector. */
3982	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3983	/** LDT selector. */
3984	#define X86_SEL_TYPE_SYS_LDT 2
3985	/** 286 TSS selector - Busy. */
3986	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3987	/** 286 Callgate selector. */
3988	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3989	/** Taskgate selector. */
3990	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3991	/** 286 Interrupt gate selector. */
3992	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3993	/** 286 Trapgate selector. */
3994	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3995	/** Undefined system selector. */
3996	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3997	/** 386 TSS selector. */
3998	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3999	/** Undefined system selector. */
4000	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4001	/** 386 TSS selector - Busy. */
4002	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4003	/** 386 Callgate selector. */
4004	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4005	/** Undefined system selector. */
4006	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4007	/** 386 Interruptgate selector. */
4008	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4009	/** 386 Trapgate selector. */
4010	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4011	/** @} */
4012
4013	/** @name AMD64 System Selector Types.
4014	* @{ */
4015	/** LDT selector. */
4016	#define AMD64_SEL_TYPE_SYS_LDT 2
4017	/** TSS selector - Busy. */
4018	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4019	/** TSS selector - Busy. */
4020	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4021	/** Callgate selector. */
4022	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4023	/** Interruptgate selector. */
4024	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4025	/** Trapgate selector. */
4026	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4027	/** @} */
4028
4029	/** @} */
4030
4031
4032	/** @name Descriptor Table Entry Flag Masks.
4033	* These are for the 2nd 32-bit word of a descriptor.
4034	* @{ */
4035	/** Bits 8-11 - TYPE - Descriptor type mask. */
4036	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4037	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4038	#define X86_DESC_S RT_BIT_32(12)
4039	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4040	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4041	/** Bit 15 - P - Present. */
4042	#define X86_DESC_P RT_BIT_32(15)
4043	/** Bit 20 - AVL - Available for system software. */
4044	#define X86_DESC_AVL RT_BIT_32(20)
4045	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4046	#define X86_DESC_DB RT_BIT_32(22)
4047	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4048	* used, if clear byte. */
4049	#define X86_DESC_G RT_BIT_32(23)
4050	/** @} */
4051
4052	/** @} */
4053
4054
4055	/** @name Task Segments.
4056	* @{
4057	*/
4058
4059	/**
4060	* The minimum TSS descriptor limit for 286 tasks.
4061	*/
4062	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4063
4064	/**
4065	* The minimum TSS descriptor segment limit for 386 tasks.
4066	*/
4067	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4068
4069	/**
4070	* 16-bit Task Segment (TSS).
4071	*/
4072	#pragma pack(1)
4073	typedef struct X86TSS16
4074	{
4075	/** Back link to previous task. (static) */
4076	RTSEL selPrev;
4077	/** Ring-0 stack pointer. (static) */
4078	uint16_t sp0;
4079	/** Ring-0 stack segment. (static) */
4080	RTSEL ss0;
4081	/** Ring-1 stack pointer. (static) */
4082	uint16_t sp1;
4083	/** Ring-1 stack segment. (static) */
4084	RTSEL ss1;
4085	/** Ring-2 stack pointer. (static) */
4086	uint16_t sp2;
4087	/** Ring-2 stack segment. (static) */
4088	RTSEL ss2;
4089	/** IP before task switch. */
4090	uint16_t ip;
4091	/** FLAGS before task switch. */
4092	uint16_t flags;
4093	/** AX before task switch. */
4094	uint16_t ax;
4095	/** CX before task switch. */
4096	uint16_t cx;
4097	/** DX before task switch. */
4098	uint16_t dx;
4099	/** BX before task switch. */
4100	uint16_t bx;
4101	/** SP before task switch. */
4102	uint16_t sp;
4103	/** BP before task switch. */
4104	uint16_t bp;
4105	/** SI before task switch. */
4106	uint16_t si;
4107	/** DI before task switch. */
4108	uint16_t di;
4109	/** ES before task switch. */
4110	RTSEL es;
4111	/** CS before task switch. */
4112	RTSEL cs;
4113	/** SS before task switch. */
4114	RTSEL ss;
4115	/** DS before task switch. */
4116	RTSEL ds;
4117	/** LDTR before task switch. */
4118	RTSEL selLdt;
4119	} X86TSS16;
4120	#ifndef VBOX_FOR_DTRACE_LIB
4121	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4122	#endif
4123	#pragma pack()
4124	/** Pointer to a 16-bit task segment. */
4125	typedef X86TSS16 *PX86TSS16;
4126	/** Pointer to a const 16-bit task segment. */
4127	typedef const X86TSS16 *PCX86TSS16;
4128
4129
4130	/**
4131	* 32-bit Task Segment (TSS).
4132	*/
4133	#pragma pack(1)
4134	typedef struct X86TSS32
4135	{
4136	/** Back link to previous task. (static) */
4137	RTSEL selPrev;
4138	uint16_t padding1;
4139	/** Ring-0 stack pointer. (static) */
4140	uint32_t esp0;
4141	/** Ring-0 stack segment. (static) */
4142	RTSEL ss0;
4143	uint16_t padding_ss0;
4144	/** Ring-1 stack pointer. (static) */
4145	uint32_t esp1;
4146	/** Ring-1 stack segment. (static) */
4147	RTSEL ss1;
4148	uint16_t padding_ss1;
4149	/** Ring-2 stack pointer. (static) */
4150	uint32_t esp2;
4151	/** Ring-2 stack segment. (static) */
4152	RTSEL ss2;
4153	uint16_t padding_ss2;
4154	/** Page directory for the task. (static) */
4155	uint32_t cr3;
4156	/** EIP before task switch. */
4157	uint32_t eip;
4158	/** EFLAGS before task switch. */
4159	uint32_t eflags;
4160	/** EAX before task switch. */
4161	uint32_t eax;
4162	/** ECX before task switch. */
4163	uint32_t ecx;
4164	/** EDX before task switch. */
4165	uint32_t edx;
4166	/** EBX before task switch. */
4167	uint32_t ebx;
4168	/** ESP before task switch. */
4169	uint32_t esp;
4170	/** EBP before task switch. */
4171	uint32_t ebp;
4172	/** ESI before task switch. */
4173	uint32_t esi;
4174	/** EDI before task switch. */
4175	uint32_t edi;
4176	/** ES before task switch. */
4177	RTSEL es;
4178	uint16_t padding_es;
4179	/** CS before task switch. */
4180	RTSEL cs;
4181	uint16_t padding_cs;
4182	/** SS before task switch. */
4183	RTSEL ss;
4184	uint16_t padding_ss;
4185	/** DS before task switch. */
4186	RTSEL ds;
4187	uint16_t padding_ds;
4188	/** FS before task switch. */
4189	RTSEL fs;
4190	uint16_t padding_fs;
4191	/** GS before task switch. */
4192	RTSEL gs;
4193	uint16_t padding_gs;
4194	/** LDTR before task switch. */
4195	RTSEL selLdt;
4196	uint16_t padding_ldt;
4197	/** Debug trap flag */
4198	uint16_t fDebugTrap;
4199	/** Offset relative to the TSS of the start of the I/O Bitmap
4200	* and the end of the interrupt redirection bitmap. */
4201	uint16_t offIoBitmap;
4202	} X86TSS32;
4203	#pragma pack()
4204	/** Pointer to task segment. */
4205	typedef X86TSS32 *PX86TSS32;
4206	/** Pointer to const task segment. */
4207	typedef const X86TSS32 *PCX86TSS32;
4208	#ifndef VBOX_FOR_DTRACE_LIB
4209	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4210	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4211	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4212	#endif
4213
4214	/**
4215	* 64-bit Task segment.
4216	*/
4217	#pragma pack(1)
4218	typedef struct X86TSS64
4219	{
4220	/** Reserved. */
4221	uint32_t u32Reserved;
4222	/** Ring-0 stack pointer. (static) */
4223	uint64_t rsp0;
4224	/** Ring-1 stack pointer. (static) */
4225	uint64_t rsp1;
4226	/** Ring-2 stack pointer. (static) */
4227	uint64_t rsp2;
4228	/** Reserved. */
4229	uint32_t u32Reserved2[2];
4230	/* IST */
4231	uint64_t ist1;
4232	uint64_t ist2;
4233	uint64_t ist3;
4234	uint64_t ist4;
4235	uint64_t ist5;
4236	uint64_t ist6;
4237	uint64_t ist7;
4238	/* Reserved. */
4239	uint16_t u16Reserved[5];
4240	/** Offset relative to the TSS of the start of the I/O Bitmap
4241	* and the end of the interrupt redirection bitmap. */
4242	uint16_t offIoBitmap;
4243	} X86TSS64;
4244	#pragma pack()
4245	/** Pointer to a 64-bit task segment. */
4246	typedef X86TSS64 *PX86TSS64;
4247	/** Pointer to a const 64-bit task segment. */
4248	typedef const X86TSS64 *PCX86TSS64;
4249	#ifndef VBOX_FOR_DTRACE_LIB
4250	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4251	#endif
4252
4253	/** @} */
4254
4255
4256	/** @name Selectors.
4257	* @{
4258	*/
4259
4260	/**
4261	* The shift used to convert a selector from and to index an index (C).
4262	*/
4263	#define X86_SEL_SHIFT 3
4264
4265	/**
4266	* The mask used to mask off the table indicator and RPL of an selector.
4267	*/
4268	#define X86_SEL_MASK 0xfff8U
4269
4270	/**
4271	* The mask used to mask off the RPL of an selector.
4272	* This is suitable for checking for NULL selectors.
4273	*/
4274	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4275
4276	/**
4277	* The bit indicating that a selector is in the LDT and not in the GDT.
4278	*/
4279	#define X86_SEL_LDT 0x0004U
4280
4281	/**
4282	* The bit mask for getting the RPL of a selector.
4283	*/
4284	#define X86_SEL_RPL 0x0003U
4285
4286	/**
4287	* The mask covering both RPL and LDT.
4288	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4289	* checks.
4290	*/
4291	#define X86_SEL_RPL_LDT 0x0007U
4292
4293	/** @} */
4294
4295
4296	/**
4297	* x86 Exceptions/Faults/Traps.
4298	*/
4299	typedef enum X86XCPT
4300	{
4301	/** \#DE - Divide error. */
4302	X86_XCPT_DE = 0x00,
4303	/** \#DB - Debug event (single step, DRx, ..) */
4304	X86_XCPT_DB = 0x01,
4305	/** NMI - Non-Maskable Interrupt */
4306	X86_XCPT_NMI = 0x02,
4307	/** \#BP - Breakpoint (INT3). */
4308	X86_XCPT_BP = 0x03,
4309	/** \#OF - Overflow (INTO). */
4310	X86_XCPT_OF = 0x04,
4311	/** \#BR - Bound range exceeded (BOUND). */
4312	X86_XCPT_BR = 0x05,
4313	/** \#UD - Undefined opcode. */
4314	X86_XCPT_UD = 0x06,
4315	/** \#NM - Device not available (math coprocessor device). */
4316	X86_XCPT_NM = 0x07,
4317	/** \#DF - Double fault. */
4318	X86_XCPT_DF = 0x08,
4319	/** ??? - Coprocessor segment overrun (obsolete). */
4320	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4321	/** \#TS - Taskswitch (TSS). */
4322	X86_XCPT_TS = 0x0a,
4323	/** \#NP - Segment no present. */
4324	X86_XCPT_NP = 0x0b,
4325	/** \#SS - Stack segment fault. */
4326	X86_XCPT_SS = 0x0c,
4327	/** \#GP - General protection fault. */
4328	X86_XCPT_GP = 0x0d,
4329	/** \#PF - Page fault. */
4330	X86_XCPT_PF = 0x0e,
4331	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4332	/** \#MF - Math fault (FPU). */
4333	X86_XCPT_MF = 0x10,
4334	/** \#AC - Alignment check. */
4335	X86_XCPT_AC = 0x11,
4336	/** \#MC - Machine check. */
4337	X86_XCPT_MC = 0x12,
4338	/** \#XF - SIMD Floating-Pointer Exception. */
4339	X86_XCPT_XF = 0x13,
4340	/** \#VE - Virtualization Exception. */
4341	X86_XCPT_VE = 0x14,
4342	/** \#SX - Security Exception. */
4343	X86_XCPT_SX = 0x1e
4344	} X86XCPT;
4345	/** Pointer to a x86 exception code. */
4346	typedef X86XCPT *PX86XCPT;
4347	/** Pointer to a const x86 exception code. */
4348	typedef const X86XCPT *PCX86XCPT;
4349	/** The last valid (currently reserved) exception value. */
4350	#define X86_XCPT_LAST 0x1f
4351
4352
4353	/** @name Trap Error Codes
4354	* @{
4355	*/
4356	/** External indicator. */
4357	#define X86_TRAP_ERR_EXTERNAL 1
4358	/** IDT indicator. */
4359	#define X86_TRAP_ERR_IDT 2
4360	/** Descriptor table indicator - If set LDT, if clear GDT. */
4361	#define X86_TRAP_ERR_TI 4
4362	/** Mask for getting the selector. */
4363	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4364	/** Shift for getting the selector table index (C type index). */
4365	#define X86_TRAP_ERR_SEL_SHIFT 3
4366	/** @} */
4367
4368
4369	/** @name \#PF Trap Error Codes
4370	* @{
4371	*/
4372	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4373	#define X86_TRAP_PF_P RT_BIT_32(0)
4374	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4375	#define X86_TRAP_PF_RW RT_BIT_32(1)
4376	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4377	#define X86_TRAP_PF_US RT_BIT_32(2)
4378	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4379	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4380	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4381	#define X86_TRAP_PF_ID RT_BIT_32(4)
4382	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4383	#define X86_TRAP_PF_PK RT_BIT_32(5)
4384	/** @} */
4385
4386	#pragma pack(1)
4387	/**
4388	* 16-bit IDTR.
4389	*/
4390	typedef struct X86IDTR16
4391	{
4392	/** Offset. */
4393	uint16_t offSel;
4394	/** Selector. */
4395	uint16_t uSel;
4396	} X86IDTR16, *PX86IDTR16;
4397	#pragma pack()
4398
4399	#pragma pack(1)
4400	/**
4401	* 32-bit IDTR/GDTR.
4402	*/
4403	typedef struct X86XDTR32
4404	{
4405	/** Size of the descriptor table. */
4406	uint16_t cb;
4407	/** Address of the descriptor table. */
4408	#ifndef VBOX_FOR_DTRACE_LIB
4409	uint32_t uAddr;
4410	#else
4411	uint16_t au16Addr[2];
4412	#endif
4413	} X86XDTR32, *PX86XDTR32;
4414	#pragma pack()
4415
4416	#pragma pack(1)
4417	/**
4418	* 64-bit IDTR/GDTR.
4419	*/
4420	typedef struct X86XDTR64
4421	{
4422	/** Size of the descriptor table. */
4423	uint16_t cb;
4424	/** Address of the descriptor table. */
4425	#ifndef VBOX_FOR_DTRACE_LIB
4426	uint64_t uAddr;
4427	#else
4428	uint16_t au16Addr[4];
4429	#endif
4430	} X86XDTR64, *PX86XDTR64;
4431	#pragma pack()
4432
4433
4434	/** @name ModR/M
4435	* @{ */
4436	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4437	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4438	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4439	#define X86_MODRM_REG_SHIFT 3
4440	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4441	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4442	#define X86_MODRM_MOD_SHIFT 6
4443	#ifndef VBOX_FOR_DTRACE_LIB
4444	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4445	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4446	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4447	/** @def X86_MODRM_MAKE
4448	* @param a_Mod The mod value (0..3).
4449	* @param a_Reg The register value (0..7).
4450	* @param a_RegMem The register or memory value (0..7). */
4451	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4452	#endif
4453	/** @} */
4454
4455	/** @name SIB
4456	* @{ */
4457	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4458	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4459	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4460	#define X86_SIB_INDEX_SHIFT 3
4461	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4462	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4463	#define X86_SIB_SCALE_SHIFT 6
4464	#ifndef VBOX_FOR_DTRACE_LIB
4465	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4466	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4467	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4468	#endif
4469	/** @} */
4470
4471	/** @name General register indexes.
4472	* @{ */
4473	#define X86_GREG_xAX 0
4474	#define X86_GREG_xCX 1
4475	#define X86_GREG_xDX 2
4476	#define X86_GREG_xBX 3
4477	#define X86_GREG_xSP 4
4478	#define X86_GREG_xBP 5
4479	#define X86_GREG_xSI 6
4480	#define X86_GREG_xDI 7
4481	#define X86_GREG_x8 8
4482	#define X86_GREG_x9 9
4483	#define X86_GREG_x10 10
4484	#define X86_GREG_x11 11
4485	#define X86_GREG_x12 12
4486	#define X86_GREG_x13 13
4487	#define X86_GREG_x14 14
4488	#define X86_GREG_x15 15
4489	/** @} */
4490	/** General register count. */
4491	#define X86_GREG_COUNT 16
4492
4493	/** @name X86_SREG_XXX - Segment register indexes.
4494	* @{ */
4495	#define X86_SREG_ES 0
4496	#define X86_SREG_CS 1
4497	#define X86_SREG_SS 2
4498	#define X86_SREG_DS 3
4499	#define X86_SREG_FS 4
4500	#define X86_SREG_GS 5
4501	/** @} */
4502	/** Segment register count. */
4503	#define X86_SREG_COUNT 6
4504
4505
4506	/** @name X86_OP_XXX - Prefixes
4507	* @{ */
4508	#define X86_OP_PRF_CS UINT8_C(0x2e)
4509	#define X86_OP_PRF_SS UINT8_C(0x36)
4510	#define X86_OP_PRF_DS UINT8_C(0x3e)
4511	#define X86_OP_PRF_ES UINT8_C(0x26)
4512	#define X86_OP_PRF_FS UINT8_C(0x64)
4513	#define X86_OP_PRF_GS UINT8_C(0x65)
4514	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4515	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4516	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4517	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4518	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4519	#define X86_OP_REX_B UINT8_C(0x41)
4520	#define X86_OP_REX_X UINT8_C(0x42)
4521	#define X86_OP_REX_R UINT8_C(0x44)
4522	#define X86_OP_REX_W UINT8_C(0x48)
4523	/** @} */
4524
4525
4526	/** @} */
4527
4528	#endif /* !IPRT_INCLUDED_x86_h */
4529

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