x86.h@ 42024

最後變更在這個檔案從42024是 42024,由 vboxsync 提交於 13 年前
VMM: RDTSCP support on Intel. Segregated some common CPU features from the AMD superset into Extended features as they're now available on Intel too.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 110.8 KB

行
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.alldomusa.eu.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	/** Bit 1 - Reserved, reads as 1. */
165	#define X86_EFL_1 RT_BIT(1)
166	/** Bit 2 - PF - Parity flag - Status flag. */
167	#define X86_EFL_PF RT_BIT(2)
168	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169	#define X86_EFL_AF RT_BIT(4)
170	/** Bit 6 - ZF - Zero flag - Status flag. */
171	#define X86_EFL_ZF RT_BIT(6)
172	/** Bit 7 - SF - Signed flag - Status flag. */
173	#define X86_EFL_SF RT_BIT(7)
174	/** Bit 8 - TF - Trap flag - System flag. */
175	#define X86_EFL_TF RT_BIT(8)
176	/** Bit 9 - IF - Interrupt flag - System flag. */
177	#define X86_EFL_IF RT_BIT(9)
178	/** Bit 10 - DF - Direction flag - Control flag. */
179	#define X86_EFL_DF RT_BIT(10)
180	/** Bit 11 - OF - Overflow flag - Status flag. */
181	#define X86_EFL_OF RT_BIT(11)
182	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
184	/** Bit 14 - NT - Nested task flag - System flag. */
185	#define X86_EFL_NT RT_BIT(14)
186	/** Bit 16 - RF - Resume flag - System flag. */
187	#define X86_EFL_RF RT_BIT(16)
188	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189	#define X86_EFL_VM RT_BIT(17)
190	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191	#define X86_EFL_AC RT_BIT(18)
192	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193	#define X86_EFL_VIF RT_BIT(19)
194	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195	#define X86_EFL_VIP RT_BIT(20)
196	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197	#define X86_EFL_ID RT_BIT(21)
198	/** IOPL shift. */
199	#define X86_EFL_IOPL_SHIFT 12
200	/** The the IOPL level from the flags. */
201	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202	/** Bits restored by popf */
203	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
204	/** @} */
205
206
207	/** CPUID Feature information - ECX.
208	* CPUID query with EAX=1.
209	*/
210	#ifndef VBOX_FOR_DTRACE_LIB
211	typedef struct X86CPUIDFEATECX
212	{
213	/** Bit 0 - SSE3 - Supports SSE3 or not. */
214	unsigned u1SSE3 : 1;
215	/** Bit 1 - PCLMULQDQ. */
216	unsigned u1PCLMULQDQ : 1;
217	/** Bit 2 - DS Area 64-bit layout. */
218	unsigned u1DTE64 : 1;
219	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
220	unsigned u1Monitor : 1;
221	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
222	unsigned u1CPLDS : 1;
223	/** Bit 5 - VMX - Virtual Machine Technology. */
224	unsigned u1VMX : 1;
225	/** Bit 6 - SMX: Safer Mode Extensions. */
226	unsigned u1SMX : 1;
227	/** Bit 7 - EST - Enh. SpeedStep Tech. */
228	unsigned u1EST : 1;
229	/** Bit 8 - TM2 - Terminal Monitor 2. */
230	unsigned u1TM2 : 1;
231	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
232	unsigned u1SSSE3 : 1;
233	/** Bit 10 - CNTX-ID - L1 Context ID. */
234	unsigned u1CNTXID : 1;
235	/** Bit 11 - Reserved. */
236	unsigned u1Reserved1 : 1;
237	/** Bit 12 - FMA. */
238	unsigned u1FMA : 1;
239	/** Bit 13 - CX16 - CMPXCHG16B. */
240	unsigned u1CX16 : 1;
241	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
242	unsigned u1TPRUpdate : 1;
243	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
244	unsigned u1PDCM : 1;
245	/** Bit 16 - Reserved. */
246	unsigned u1Reserved2 : 1;
247	/** Bit 17 - PCID - Process-context identifiers. */
248	unsigned u1PCID : 1;
249	/** Bit 18 - Direct Cache Access. */
250	unsigned u1DCA : 1;
251	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
252	unsigned u1SSE4_1 : 1;
253	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
254	unsigned u1SSE4_2 : 1;
255	/** Bit 21 - x2APIC. */
256	unsigned u1x2APIC : 1;
257	/** Bit 22 - MOVBE - Supports MOVBE. */
258	unsigned u1MOVBE : 1;
259	/** Bit 23 - POPCNT - Supports POPCNT. */
260	unsigned u1POPCNT : 1;
261	/** Bit 24 - TSC-Deadline. */
262	unsigned u1TSCDEADLINE : 1;
263	/** Bit 25 - AES. */
264	unsigned u1AES : 1;
265	/** Bit 26 - XSAVE - Supports XSAVE. */
266	unsigned u1XSAVE : 1;
267	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
268	unsigned u1OSXSAVE : 1;
269	/** Bit 28 - AVX - Supports AVX instruction extensions. */
270	unsigned u1AVX : 1;
271	/** Bit 29 - 30 - Reserved */
272	unsigned u2Reserved3 : 2;
273	/** Bit 31 - Hypervisor present (we're a guest). */
274	unsigned u1HVP : 1;
275	} X86CPUIDFEATECX;
276	#else /* VBOX_FOR_DTRACE_LIB */
277	typedef uint32_t X86CPUIDFEATECX;
278	#endif /* VBOX_FOR_DTRACE_LIB */
279	/** Pointer to CPUID Feature Information - ECX. */
280	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
281	/** Pointer to const CPUID Feature Information - ECX. */
282	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
283
284
285	/** CPUID Feature Information - EDX.
286	* CPUID query with EAX=1.
287	*/
288	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
289	typedef struct X86CPUIDFEATEDX
290	{
291	/** Bit 0 - FPU - x87 FPU on Chip. */
292	unsigned u1FPU : 1;
293	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
294	unsigned u1VME : 1;
295	/** Bit 2 - DE - Debugging extensions. */
296	unsigned u1DE : 1;
297	/** Bit 3 - PSE - Page Size Extension. */
298	unsigned u1PSE : 1;
299	/** Bit 4 - TSC - Time Stamp Counter. */
300	unsigned u1TSC : 1;
301	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
302	unsigned u1MSR : 1;
303	/** Bit 6 - PAE - Physical Address Extension. */
304	unsigned u1PAE : 1;
305	/** Bit 7 - MCE - Machine Check Exception. */
306	unsigned u1MCE : 1;
307	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
308	unsigned u1CX8 : 1;
309	/** Bit 9 - APIC - APIC On-Chip. */
310	unsigned u1APIC : 1;
311	/** Bit 10 - Reserved. */
312	unsigned u1Reserved1 : 1;
313	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
314	unsigned u1SEP : 1;
315	/** Bit 12 - MTRR - Memory Type Range Registers. */
316	unsigned u1MTRR : 1;
317	/** Bit 13 - PGE - PTE Global Bit. */
318	unsigned u1PGE : 1;
319	/** Bit 14 - MCA - Machine Check Architecture. */
320	unsigned u1MCA : 1;
321	/** Bit 15 - CMOV - Conditional Move Instructions. */
322	unsigned u1CMOV : 1;
323	/** Bit 16 - PAT - Page Attribute Table. */
324	unsigned u1PAT : 1;
325	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
326	unsigned u1PSE36 : 1;
327	/** Bit 18 - PSN - Processor Serial Number. */
328	unsigned u1PSN : 1;
329	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
330	unsigned u1CLFSH : 1;
331	/** Bit 20 - Reserved. */
332	unsigned u1Reserved2 : 1;
333	/** Bit 21 - DS - Debug Store. */
334	unsigned u1DS : 1;
335	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
336	unsigned u1ACPI : 1;
337	/** Bit 23 - MMX - Intel MMX 'Technology'. */
338	unsigned u1MMX : 1;
339	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
340	unsigned u1FXSR : 1;
341	/** Bit 25 - SSE - SSE Support. */
342	unsigned u1SSE : 1;
343	/** Bit 26 - SSE2 - SSE2 Support. */
344	unsigned u1SSE2 : 1;
345	/** Bit 27 - SS - Self Snoop. */
346	unsigned u1SS : 1;
347	/** Bit 28 - HTT - Hyper-Threading Technology. */
348	unsigned u1HTT : 1;
349	/** Bit 29 - TM - Thermal Monitor. */
350	unsigned u1TM : 1;
351	/** Bit 30 - Reserved - . */
352	unsigned u1Reserved3 : 1;
353	/** Bit 31 - PBE - Pending Break Enabled. */
354	unsigned u1PBE : 1;
355	} X86CPUIDFEATEDX;
356	#else /* VBOX_FOR_DTRACE_LIB */
357	typedef uint32_t X86CPUIDFEATEDX;
358	#endif /* VBOX_FOR_DTRACE_LIB */
359	/** Pointer to CPUID Feature Information - EDX. */
360	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
361	/** Pointer to const CPUID Feature Information - EDX. */
362	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
363
364	/** @name CPUID Vendor information.
365	* CPUID query with EAX=0.
366	* @{
367	*/
368	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
369	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
370	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
371
372	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
373	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
374	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
375	/** @} */
376
377
378	/** @name CPUID Feature information.
379	* CPUID query with EAX=1.
380	* @{
381	*/
382	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
383	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
384	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
385	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
386	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
387	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
388	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
389	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
390	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
391	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
392	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
393	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
394	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
395	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
396	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
397	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
398	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
399	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
400	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
401	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
402	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
403	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
404	/** ECX Bit 12 - FMA. */
405	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
406	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
407	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
408	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
409	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
410	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
411	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
412	/** ECX Bit 17 - PCID - Process-context identifiers. */
413	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
414	/** ECX Bit 18 - DCA - Direct Cache Access. */
415	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
416	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
417	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
418	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
419	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
420	/** ECX Bit 21 - x2APIC support. */
421	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
422	/** ECX Bit 22 - MOVBE instruction. */
423	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
424	/** ECX Bit 23 - POPCNT instruction. */
425	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
426	/** ECX Bir 24 - TSC-Deadline. */
427	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
428	/** ECX Bit 25 - AES instructions. */
429	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
430	/** ECX Bit 26 - XSAVE instruction. */
431	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
432	/** ECX Bit 27 - OSXSAVE instruction. */
433	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
434	/** ECX Bit 28 - AVX. */
435	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
436	/** ECX Bit 31 - Hypervisor Present (software only). */
437	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
438
439
440	/** Bit 0 - FPU - x87 FPU on Chip. */
441	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
442	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
443	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
444	/** Bit 2 - DE - Debugging extensions. */
445	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
446	/** Bit 3 - PSE - Page Size Extension. */
447	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
448	/** Bit 4 - TSC - Time Stamp Counter. */
449	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
450	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
451	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
452	/** Bit 6 - PAE - Physical Address Extension. */
453	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
454	/** Bit 7 - MCE - Machine Check Exception. */
455	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
456	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
457	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
458	/** Bit 9 - APIC - APIC On-Chip. */
459	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
460	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
461	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
462	/** Bit 12 - MTRR - Memory Type Range Registers. */
463	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
464	/** Bit 13 - PGE - PTE Global Bit. */
465	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
466	/** Bit 14 - MCA - Machine Check Architecture. */
467	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
468	/** Bit 15 - CMOV - Conditional Move Instructions. */
469	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
470	/** Bit 16 - PAT - Page Attribute Table. */
471	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
472	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
473	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
474	/** Bit 18 - PSN - Processor Serial Number. */
475	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
476	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
477	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
478	/** Bit 21 - DS - Debug Store. */
479	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
480	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
481	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
482	/** Bit 23 - MMX - Intel MMX Technology. */
483	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
484	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
485	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
486	/** Bit 25 - SSE - SSE Support. */
487	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
488	/** Bit 26 - SSE2 - SSE2 Support. */
489	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
490	/** Bit 27 - SS - Self Snoop. */
491	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
492	/** Bit 28 - HTT - Hyper-Threading Technology. */
493	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
494	/** Bit 29 - TM - Therm. Monitor. */
495	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
496	/** Bit 31 - PBE - Pending Break Enabled. */
497	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
498	/** @} */
499
500	/** @name CPUID mwait/monitor information.
501	* CPUID query with EAX=5.
502	* @{
503	*/
504	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
505	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
506	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
507	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
508	/** @} */
509
510
511	/** @name CPUID Extended Feature information.
512	* CPUID query with EAX=0x80000001.
513	* @{
514	*/
515	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
516	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
517
518	/** EDX Bit 11 - SYSCALL/SYSRET. */
519	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
520	/** EDX Bit 20 - No-Execute/Execute-Disable. */
521	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
522	/** EDX Bit 26 - 1 GB large page. */
523	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
524	/** EDX Bit 27 - RDTSCP. */
525	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
526	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
527	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
528	/** @}*/
529
530	/** @name CPUID AMD Feature information.
531	* CPUID query with EAX=0x80000001.
532	* @{
533	*/
534	/** Bit 0 - FPU - x87 FPU on Chip. */
535	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
536	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
537	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
538	/** Bit 2 - DE - Debugging extensions. */
539	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
540	/** Bit 3 - PSE - Page Size Extension. */
541	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
542	/** Bit 4 - TSC - Time Stamp Counter. */
543	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
544	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
545	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
546	/** Bit 6 - PAE - Physical Address Extension. */
547	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
548	/** Bit 7 - MCE - Machine Check Exception. */
549	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
550	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
551	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
552	/** Bit 9 - APIC - APIC On-Chip. */
553	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
554	/** Bit 12 - MTRR - Memory Type Range Registers. */
555	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
556	/** Bit 13 - PGE - PTE Global Bit. */
557	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
558	/** Bit 14 - MCA - Machine Check Architecture. */
559	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
560	/** Bit 15 - CMOV - Conditional Move Instructions. */
561	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
562	/** Bit 16 - PAT - Page Attribute Table. */
563	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
564	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
565	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
566	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
567	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
568	/** Bit 23 - MMX - Intel MMX Technology. */
569	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
570	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
571	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
572	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
573	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
574	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
575	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
576	/** Bit 31 - 3DNOW - AMD 3DNow. */
577	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
578
579	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
580	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
581	/** Bit 2 - SVM - AMD VM extensions. */
582	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
583	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
584	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
585	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
586	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
587	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
588	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
589	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
590	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
591	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
592	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
593	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
594	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
595	/** Bit 9 - OSVW - AMD OS visible workaround. */
596	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
597	/** Bit 10 - IBS - Instruct based sampling. */
598	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
599	/** Bit 11 - SSE5 - SSE5 instruction support. */
600	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
601	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
602	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
603	/** Bit 13 - WDT - AMD Watchdog timer support. */
604	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
605
606	/** @} */
607
608
609	/** @name CPUID AMD Feature information.
610	* CPUID query with EAX=0x80000007.
611	* @{
612	*/
613	/** Bit 0 - TS - Temperature Sensor. */
614	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
615	/** Bit 1 - FID - Frequency ID Control. */
616	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
617	/** Bit 2 - VID - Voltage ID Control. */
618	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
619	/** Bit 3 - TTP - THERMTRIP. */
620	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
621	/** Bit 4 - TM - Hardware Thermal Control. */
622	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
623	/** Bit 5 - STC - Software Thermal Control. */
624	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
625	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
626	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
627	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
628	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
629	/** Bit 8 - TSCINVAR - TSC Invariant. */
630	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
631	/** @} */
632
633
634	/** @name CR0
635	* @{ */
636	/** Bit 0 - PE - Protection Enabled */
637	#define X86_CR0_PE RT_BIT(0)
638	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
639	/** Bit 1 - MP - Monitor Coprocessor */
640	#define X86_CR0_MP RT_BIT(1)
641	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
642	/** Bit 2 - EM - Emulation. */
643	#define X86_CR0_EM RT_BIT(2)
644	#define X86_CR0_EMULATE_FPU RT_BIT(2)
645	/** Bit 3 - TS - Task Switch. */
646	#define X86_CR0_TS RT_BIT(3)
647	#define X86_CR0_TASK_SWITCH RT_BIT(3)
648	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
649	#define X86_CR0_ET RT_BIT(4)
650	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
651	/** Bit 5 - NE - Numeric error. */
652	#define X86_CR0_NE RT_BIT(5)
653	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
654	/** Bit 16 - WP - Write Protect. */
655	#define X86_CR0_WP RT_BIT(16)
656	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
657	/** Bit 18 - AM - Alignment Mask. */
658	#define X86_CR0_AM RT_BIT(18)
659	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
660	/** Bit 29 - NW - Not Write-though. */
661	#define X86_CR0_NW RT_BIT(29)
662	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
663	/** Bit 30 - WP - Cache Disable. */
664	#define X86_CR0_CD RT_BIT(30)
665	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
666	/** Bit 31 - PG - Paging. */
667	#define X86_CR0_PG RT_BIT(31)
668	#define X86_CR0_PAGING RT_BIT(31)
669	/** @} */
670
671
672	/** @name CR3
673	* @{ */
674	/** Bit 3 - PWT - Page-level Writes Transparent. */
675	#define X86_CR3_PWT RT_BIT(3)
676	/** Bit 4 - PCD - Page-level Cache Disable. */
677	#define X86_CR3_PCD RT_BIT(4)
678	/** Bits 12-31 - - Page directory page number. */
679	#define X86_CR3_PAGE_MASK (0xfffff000)
680	/** Bits 5-31 - - PAE Page directory page number. */
681	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
682	/** Bits 12-51 - - AMD64 Page directory page number. */
683	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
684	/** @} */
685
686
687	/** @name CR4
688	* @{ */
689	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
690	#define X86_CR4_VME RT_BIT(0)
691	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
692	#define X86_CR4_PVI RT_BIT(1)
693	/** Bit 2 - TSD - Time Stamp Disable. */
694	#define X86_CR4_TSD RT_BIT(2)
695	/** Bit 3 - DE - Debugging Extensions. */
696	#define X86_CR4_DE RT_BIT(3)
697	/** Bit 4 - PSE - Page Size Extension. */
698	#define X86_CR4_PSE RT_BIT(4)
699	/** Bit 5 - PAE - Physical Address Extension. */
700	#define X86_CR4_PAE RT_BIT(5)
701	/** Bit 6 - MCE - Machine-Check Enable. */
702	#define X86_CR4_MCE RT_BIT(6)
703	/** Bit 7 - PGE - Page Global Enable. */
704	#define X86_CR4_PGE RT_BIT(7)
705	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
706	#define X86_CR4_PCE RT_BIT(8)
707	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
708	#define X86_CR4_OSFSXR RT_BIT(9)
709	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
710	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
711	/** Bit 13 - VMXE - VMX mode is enabled. */
712	#define X86_CR4_VMXE RT_BIT(13)
713	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
714	#define X86_CR4_SMXE RT_BIT(14)
715	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
716	#define X86_CR4_PCIDE RT_BIT(17)
717	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
718	* extended states. */
719	#define X86_CR4_OSXSAVE RT_BIT(18)
720	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
721	#define X86_CR4_SMEP RT_BIT(20)
722	/** @} */
723
724
725	/** @name DR6
726	* @{ */
727	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
728	#define X86_DR6_B0 RT_BIT(0)
729	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
730	#define X86_DR6_B1 RT_BIT(1)
731	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
732	#define X86_DR6_B2 RT_BIT(2)
733	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
734	#define X86_DR6_B3 RT_BIT(3)
735	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
736	#define X86_DR6_BD RT_BIT(13)
737	/** Bit 14 - BS - Single step */
738	#define X86_DR6_BS RT_BIT(14)
739	/** Bit 15 - BT - Task switch. (TSS T bit.) */
740	#define X86_DR6_BT RT_BIT(15)
741	/** Value of DR6 after powerup/reset. */
742	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
743	/** @} */
744
745
746	/** @name DR7
747	* @{ */
748	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
749	#define X86_DR7_L0 RT_BIT(0)
750	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
751	#define X86_DR7_G0 RT_BIT(1)
752	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
753	#define X86_DR7_L1 RT_BIT(2)
754	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
755	#define X86_DR7_G1 RT_BIT(3)
756	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
757	#define X86_DR7_L2 RT_BIT(4)
758	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
759	#define X86_DR7_G2 RT_BIT(5)
760	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
761	#define X86_DR7_L3 RT_BIT(6)
762	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
763	#define X86_DR7_G3 RT_BIT(7)
764	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
765	#define X86_DR7_LE RT_BIT(8)
766	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
767	#define X86_DR7_GE RT_BIT(9)
768
769	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
770	* any DR register is accessed. */
771	#define X86_DR7_GD RT_BIT(13)
772	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
773	#define X86_DR7_RW0_MASK (3 << 16)
774	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
775	#define X86_DR7_LEN0_MASK (3 << 18)
776	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
777	#define X86_DR7_RW1_MASK (3 << 20)
778	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
779	#define X86_DR7_LEN1_MASK (3 << 22)
780	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
781	#define X86_DR7_RW2_MASK (3 << 24)
782	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
783	#define X86_DR7_LEN2_MASK (3 << 26)
784	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
785	#define X86_DR7_RW3_MASK (3 << 28)
786	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
787	#define X86_DR7_LEN3_MASK (3 << 30)
788
789	/** Bits which must be 1s. */
790	#define X86_DR7_MB1_MASK (RT_BIT(10))
791
792	/** Calcs the L bit of Nth breakpoint.
793	* @param iBp The breakpoint number [0..3].
794	*/
795	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
796
797	/** Calcs the G bit of Nth breakpoint.
798	* @param iBp The breakpoint number [0..3].
799	*/
800	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
801
802	/** @name Read/Write values.
803	* @{ */
804	/** Break on instruction fetch only. */
805	#define X86_DR7_RW_EO 0U
806	/** Break on write only. */
807	#define X86_DR7_RW_WO 1U
808	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
809	#define X86_DR7_RW_IO 2U
810	/** Break on read or write (but not instruction fetches). */
811	#define X86_DR7_RW_RW 3U
812	/** @} */
813
814	/** Shifts a X86_DR7_RW_* value to its right place.
815	* @param iBp The breakpoint number [0..3].
816	* @param fRw One of the X86_DR7_RW_* value.
817	*/
818	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
819
820	/** @name Length values.
821	* @{ */
822	#define X86_DR7_LEN_BYTE 0U
823	#define X86_DR7_LEN_WORD 1U
824	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
825	#define X86_DR7_LEN_DWORD 3U
826	/** @} */
827
828	/** Shifts a X86_DR7_LEN_* value to its right place.
829	* @param iBp The breakpoint number [0..3].
830	* @param cb One of the X86_DR7_LEN_* values.
831	*/
832	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
833
834	/** Fetch the breakpoint length bits from the DR7 value.
835	* @param uDR7 DR7 value
836	* @param iBp The breakpoint number [0..3].
837	*/
838	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
839
840	/** Mask used to check if any breakpoints are enabled. */
841	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
842
843	/** Mask used to check if any io breakpoints are set. */
844	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
845
846	/** Value of DR7 after powerup/reset. */
847	#define X86_DR7_INIT_VAL 0x400
848	/** @} */
849
850
851	/** @name Machine Specific Registers
852	* @{
853	*/
854
855	/** Time Stamp Counter. */
856	#define MSR_IA32_TSC 0x10
857
858	#define MSR_IA32_PLATFORM_ID 0x17
859
860	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
861	#define MSR_IA32_APICBASE 0x1b
862	#endif
863
864	/** CPU Feature control. */
865	#define MSR_IA32_FEATURE_CONTROL 0x3A
866	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
867	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
868
869	/** BIOS update trigger (microcode update). */
870	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
871
872	/** BIOS update signature (microcode). */
873	#define MSR_IA32_BIOS_SIGN_ID 0x8B
874
875	/** General performance counter no. 0. */
876	#define MSR_IA32_PMC0 0xC1
877	/** General performance counter no. 1. */
878	#define MSR_IA32_PMC1 0xC2
879	/** General performance counter no. 2. */
880	#define MSR_IA32_PMC2 0xC3
881	/** General performance counter no. 3. */
882	#define MSR_IA32_PMC3 0xC4
883
884	/** Nehalem power control. */
885	#define MSR_IA32_PLATFORM_INFO 0xCE
886
887	/** Get FSB clock status (Intel-specific). */
888	#define MSR_IA32_FSB_CLOCK_STS 0xCD
889
890	/** MTRR Capabilities. */
891	#define MSR_IA32_MTRR_CAP 0xFE
892
893
894	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
895	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
896	* R0 SS == CS + 8
897	* R3 CS == CS + 16
898	* R3 SS == CS + 24
899	*/
900	#define MSR_IA32_SYSENTER_CS 0x174
901	/** SYSENTER_ESP - the R0 ESP. */
902	#define MSR_IA32_SYSENTER_ESP 0x175
903	/** SYSENTER_EIP - the R0 EIP. */
904	#define MSR_IA32_SYSENTER_EIP 0x176
905	#endif
906
907	/** Machine Check Global Capabilities Register. */
908	#define MSR_IA32_MCP_CAP 0x179
909	/** Machine Check Global Status Register. */
910	#define MSR_IA32_MCP_STATUS 0x17A
911	/** Machine Check Global Control Register. */
912	#define MSR_IA32_MCP_CTRL 0x17B
913
914	/** Trace/Profile Resource Control (R/W) */
915	#define MSR_IA32_DEBUGCTL 0x1D9
916
917	/** Page Attribute Table. */
918	#define MSR_IA32_CR_PAT 0x277
919
920	/** Performance counter MSRs. (Intel only) */
921	#define MSR_IA32_PERFEVTSEL0 0x186
922	#define MSR_IA32_PERFEVTSEL1 0x187
923	#define MSR_IA32_FLEX_RATIO 0x194
924	#define MSR_IA32_PERF_STATUS 0x198
925	#define MSR_IA32_PERF_CTL 0x199
926	#define MSR_IA32_THERM_STATUS 0x19c
927
928	/** Enable misc. processor features (R/W). */
929	#define MSR_IA32_MISC_ENABLE 0x1A0
930	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
931	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
932	/** Automatic Thermal Control Circuit Enable (R/W). */
933	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
934	/** Performance Monitoring Available (R). */
935	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
936	/** Branch Trace Storage Unavailable (R/O). */
937	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
938	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
939	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
940	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
941	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
942	/** If MONITOR/MWAIT is supported (R/W). */
943	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
944	/** Limit CPUID Maxval to 3 leafs (R/W). */
945	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
946	/** When set to 1, xTPR messages are disabled (R/W). */
947	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
948	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
949	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
950
951	#define IA32_MTRR_PHYSBASE0 0x200
952	#define IA32_MTRR_PHYSMASK0 0x201
953	#define IA32_MTRR_PHYSBASE1 0x202
954	#define IA32_MTRR_PHYSMASK1 0x203
955	#define IA32_MTRR_PHYSBASE2 0x204
956	#define IA32_MTRR_PHYSMASK2 0x205
957	#define IA32_MTRR_PHYSBASE3 0x206
958	#define IA32_MTRR_PHYSMASK3 0x207
959	#define IA32_MTRR_PHYSBASE4 0x208
960	#define IA32_MTRR_PHYSMASK4 0x209
961	#define IA32_MTRR_PHYSBASE5 0x20a
962	#define IA32_MTRR_PHYSMASK5 0x20b
963	#define IA32_MTRR_PHYSBASE6 0x20c
964	#define IA32_MTRR_PHYSMASK6 0x20d
965	#define IA32_MTRR_PHYSBASE7 0x20e
966	#define IA32_MTRR_PHYSMASK7 0x20f
967	#define IA32_MTRR_PHYSBASE8 0x210
968	#define IA32_MTRR_PHYSMASK8 0x211
969	#define IA32_MTRR_PHYSBASE9 0x212
970	#define IA32_MTRR_PHYSMASK9 0x213
971
972	/** Fixed range MTRRs.
973	* @{ */
974	#define IA32_MTRR_FIX64K_00000 0x250
975	#define IA32_MTRR_FIX16K_80000 0x258
976	#define IA32_MTRR_FIX16K_A0000 0x259
977	#define IA32_MTRR_FIX4K_C0000 0x268
978	#define IA32_MTRR_FIX4K_C8000 0x269
979	#define IA32_MTRR_FIX4K_D0000 0x26a
980	#define IA32_MTRR_FIX4K_D8000 0x26b
981	#define IA32_MTRR_FIX4K_E0000 0x26c
982	#define IA32_MTRR_FIX4K_E8000 0x26d
983	#define IA32_MTRR_FIX4K_F0000 0x26e
984	#define IA32_MTRR_FIX4K_F8000 0x26f
985	/** @} */
986
987	/** MTRR Default Range. */
988	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
989
990	#define MSR_IA32_MC0_CTL 0x400
991	#define MSR_IA32_MC0_STATUS 0x401
992
993	/** Basic VMX information. */
994	#define MSR_IA32_VMX_BASIC_INFO 0x480
995	/** Allowed settings for pin-based VM execution controls */
996	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
997	/** Allowed settings for proc-based VM execution controls */
998	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
999	/** Allowed settings for the VMX exit controls. */
1000	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1001	/** Allowed settings for the VMX entry controls. */
1002	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1003	/** Misc VMX info. */
1004	#define MSR_IA32_VMX_MISC 0x485
1005	/** Fixed cleared bits in CR0. */
1006	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1007	/** Fixed set bits in CR0. */
1008	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1009	/** Fixed cleared bits in CR4. */
1010	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1011	/** Fixed set bits in CR4. */
1012	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1013	/** Information for enumerating fields in the VMCS. */
1014	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1015	/** Allowed settings for secondary proc-based VM execution controls */
1016	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1017	/** EPT capabilities. */
1018	#define MSR_IA32_VMX_EPT_CAPS 0x48C
1019	/** DS Save Area (R/W). */
1020	#define MSR_IA32_DS_AREA 0x600
1021	/** X2APIC MSR ranges. */
1022	#define MSR_IA32_APIC_START 0x800
1023	#define MSR_IA32_APIC_END 0x900
1024
1025	/** K6 EFER - Extended Feature Enable Register. */
1026	#define MSR_K6_EFER 0xc0000080
1027	/** @todo document EFER */
1028	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1029	#define MSR_K6_EFER_SCE RT_BIT(0)
1030	/** Bit 8 - LME - Long mode enabled. (R/W) */
1031	#define MSR_K6_EFER_LME RT_BIT(8)
1032	/** Bit 10 - LMA - Long mode active. (R) */
1033	#define MSR_K6_EFER_LMA RT_BIT(10)
1034	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1035	#define MSR_K6_EFER_NXE RT_BIT(11)
1036	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1037	#define MSR_K6_EFER_SVME RT_BIT(12)
1038	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1039	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1040	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1041	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1042	/** K6 STAR - SYSCALL/RET targets. */
1043	#define MSR_K6_STAR 0xc0000081
1044	/** Shift value for getting the SYSRET CS and SS value. */
1045	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1046	/** Shift value for getting the SYSCALL CS and SS value. */
1047	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1048	/** Selector mask for use after shifting. */
1049	#define MSR_K6_STAR_SEL_MASK 0xffff
1050	/** The mask which give the SYSCALL EIP. */
1051	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1052	/** K6 WHCR - Write Handling Control Register. */
1053	#define MSR_K6_WHCR 0xc0000082
1054	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1055	#define MSR_K6_UWCCR 0xc0000085
1056	/** K6 PSOR - Processor State Observability Register. */
1057	#define MSR_K6_PSOR 0xc0000087
1058	/** K6 PFIR - Page Flush/Invalidate Register. */
1059	#define MSR_K6_PFIR 0xc0000088
1060
1061	/** Performance counter MSRs. (AMD only) */
1062	#define MSR_K7_EVNTSEL0 0xc0010000
1063	#define MSR_K7_EVNTSEL1 0xc0010001
1064	#define MSR_K7_EVNTSEL2 0xc0010002
1065	#define MSR_K7_EVNTSEL3 0xc0010003
1066	#define MSR_K7_PERFCTR0 0xc0010004
1067	#define MSR_K7_PERFCTR1 0xc0010005
1068	#define MSR_K7_PERFCTR2 0xc0010006
1069	#define MSR_K7_PERFCTR3 0xc0010007
1070
1071	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1072	#define MSR_K8_LSTAR 0xc0000082
1073	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1074	#define MSR_K8_CSTAR 0xc0000083
1075	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1076	#define MSR_K8_SF_MASK 0xc0000084
1077	/** K8 FS.base - The 64-bit base FS register. */
1078	#define MSR_K8_FS_BASE 0xc0000100
1079	/** K8 GS.base - The 64-bit base GS register. */
1080	#define MSR_K8_GS_BASE 0xc0000101
1081	/** K8 KernelGSbase - Used with SWAPGS. */
1082	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1083	#define MSR_K8_TSC_AUX 0xc0000103
1084	#define MSR_K8_SYSCFG 0xc0010010
1085	#define MSR_K8_HWCR 0xc0010015
1086	#define MSR_K8_IORRBASE0 0xc0010016
1087	#define MSR_K8_IORRMASK0 0xc0010017
1088	#define MSR_K8_IORRBASE1 0xc0010018
1089	#define MSR_K8_IORRMASK1 0xc0010019
1090	#define MSR_K8_TOP_MEM1 0xc001001a
1091	#define MSR_K8_TOP_MEM2 0xc001001d
1092	#define MSR_K8_VM_CR 0xc0010114
1093	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1094
1095	#define MSR_K8_IGNNE 0xc0010115
1096	#define MSR_K8_SMM_CTL 0xc0010116
1097	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1098	* host state during world switch.
1099	*/
1100	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1101
1102	/** @} */
1103
1104
1105	/** @name Page Table / Directory / Directory Pointers / L4.
1106	* @{
1107	*/
1108
1109	/** Page table/directory entry as an unsigned integer. */
1110	typedef uint32_t X86PGUINT;
1111	/** Pointer to a page table/directory table entry as an unsigned integer. */
1112	typedef X86PGUINT *PX86PGUINT;
1113	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1114	typedef X86PGUINT const *PCX86PGUINT;
1115
1116	/** Number of entries in a 32-bit PT/PD. */
1117	#define X86_PG_ENTRIES 1024
1118
1119
1120	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1121	typedef uint64_t X86PGPAEUINT;
1122	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1123	typedef X86PGPAEUINT *PX86PGPAEUINT;
1124	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1125	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1126
1127	/** Number of entries in a PAE PT/PD. */
1128	#define X86_PG_PAE_ENTRIES 512
1129	/** Number of entries in a PAE PDPT. */
1130	#define X86_PG_PAE_PDPE_ENTRIES 4
1131
1132	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1133	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1134	/** Number of entries in an AMD64 PDPT.
1135	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1136	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1137
1138	/** The size of a 4KB page. */
1139	#define X86_PAGE_4K_SIZE _4K
1140	/** The page shift of a 4KB page. */
1141	#define X86_PAGE_4K_SHIFT 12
1142	/** The 4KB page offset mask. */
1143	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1144	/** The 4KB page base mask for virtual addresses. */
1145	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1146	/** The 4KB page base mask for virtual addresses - 32bit version. */
1147	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1148
1149	/** The size of a 2MB page. */
1150	#define X86_PAGE_2M_SIZE _2M
1151	/** The page shift of a 2MB page. */
1152	#define X86_PAGE_2M_SHIFT 21
1153	/** The 2MB page offset mask. */
1154	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1155	/** The 2MB page base mask for virtual addresses. */
1156	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1157	/** The 2MB page base mask for virtual addresses - 32bit version. */
1158	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1159
1160	/** The size of a 4MB page. */
1161	#define X86_PAGE_4M_SIZE _4M
1162	/** The page shift of a 4MB page. */
1163	#define X86_PAGE_4M_SHIFT 22
1164	/** The 4MB page offset mask. */
1165	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1166	/** The 4MB page base mask for virtual addresses. */
1167	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1168	/** The 4MB page base mask for virtual addresses - 32bit version. */
1169	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1170
1171
1172
1173	/** @name Page Table Entry
1174	* @{
1175	*/
1176	/** Bit 0 - P - Present bit. */
1177	#define X86_PTE_BIT_P 0
1178	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1179	#define X86_PTE_BIT_RW 1
1180	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1181	#define X86_PTE_BIT_US 2
1182	/** Bit 3 - PWT - Page level write thru bit. */
1183	#define X86_PTE_BIT_PWT 3
1184	/** Bit 4 - PCD - Page level cache disable bit. */
1185	#define X86_PTE_BIT_PCD 4
1186	/** Bit 5 - A - Access bit. */
1187	#define X86_PTE_BIT_A 5
1188	/** Bit 6 - D - Dirty bit. */
1189	#define X86_PTE_BIT_D 6
1190	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1191	#define X86_PTE_BIT_PAT 7
1192	/** Bit 8 - G - Global flag. */
1193	#define X86_PTE_BIT_G 8
1194
1195	/** Bit 0 - P - Present bit mask. */
1196	#define X86_PTE_P RT_BIT(0)
1197	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1198	#define X86_PTE_RW RT_BIT(1)
1199	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1200	#define X86_PTE_US RT_BIT(2)
1201	/** Bit 3 - PWT - Page level write thru bit mask. */
1202	#define X86_PTE_PWT RT_BIT(3)
1203	/** Bit 4 - PCD - Page level cache disable bit mask. */
1204	#define X86_PTE_PCD RT_BIT(4)
1205	/** Bit 5 - A - Access bit mask. */
1206	#define X86_PTE_A RT_BIT(5)
1207	/** Bit 6 - D - Dirty bit mask. */
1208	#define X86_PTE_D RT_BIT(6)
1209	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1210	#define X86_PTE_PAT RT_BIT(7)
1211	/** Bit 8 - G - Global bit mask. */
1212	#define X86_PTE_G RT_BIT(8)
1213
1214	/** Bits 9-11 - - Available for use to system software. */
1215	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1216	/** Bits 12-31 - - Physical Page number of the next level. */
1217	#define X86_PTE_PG_MASK ( 0xfffff000 )
1218
1219	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1220	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1221	/** Bits 63 - NX - PAE/LM - No execution flag. */
1222	#define X86_PTE_PAE_NX RT_BIT_64(63)
1223	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1224	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1225	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1226	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1227	/** No bits - - LM - MBZ bits when NX is active. */
1228	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1229	/** Bits 63 - - LM - MBZ bits when no NX. */
1230	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1231
1232	/**
1233	* Page table entry.
1234	*/
1235	typedef struct X86PTEBITS
1236	{
1237	/** Flags whether(=1) or not the page is present. */
1238	unsigned u1Present : 1;
1239	/** Read(=0) / Write(=1) flag. */
1240	unsigned u1Write : 1;
1241	/** User(=1) / Supervisor (=0) flag. */
1242	unsigned u1User : 1;
1243	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1244	unsigned u1WriteThru : 1;
1245	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1246	unsigned u1CacheDisable : 1;
1247	/** Accessed flag.
1248	* Indicates that the page have been read or written to. */
1249	unsigned u1Accessed : 1;
1250	/** Dirty flag.
1251	* Indicates that the page has been written to. */
1252	unsigned u1Dirty : 1;
1253	/** Reserved / If PAT enabled, bit 2 of the index. */
1254	unsigned u1PAT : 1;
1255	/** Global flag. (Ignored in all but final level.) */
1256	unsigned u1Global : 1;
1257	/** Available for use to system software. */
1258	unsigned u3Available : 3;
1259	/** Physical Page number of the next level. */
1260	unsigned u20PageNo : 20;
1261	} X86PTEBITS;
1262	/** Pointer to a page table entry. */
1263	typedef X86PTEBITS *PX86PTEBITS;
1264	/** Pointer to a const page table entry. */
1265	typedef const X86PTEBITS *PCX86PTEBITS;
1266
1267	/**
1268	* Page table entry.
1269	*/
1270	typedef union X86PTE
1271	{
1272	/** Unsigned integer view */
1273	X86PGUINT u;
1274	/** Bit field view. */
1275	X86PTEBITS n;
1276	/** 32-bit view. */
1277	uint32_t au32[1];
1278	/** 16-bit view. */
1279	uint16_t au16[2];
1280	/** 8-bit view. */
1281	uint8_t au8[4];
1282	} X86PTE;
1283	/** Pointer to a page table entry. */
1284	typedef X86PTE *PX86PTE;
1285	/** Pointer to a const page table entry. */
1286	typedef const X86PTE *PCX86PTE;
1287
1288
1289	/**
1290	* PAE page table entry.
1291	*/
1292	typedef struct X86PTEPAEBITS
1293	{
1294	/** Flags whether(=1) or not the page is present. */
1295	uint32_t u1Present : 1;
1296	/** Read(=0) / Write(=1) flag. */
1297	uint32_t u1Write : 1;
1298	/** User(=1) / Supervisor(=0) flag. */
1299	uint32_t u1User : 1;
1300	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1301	uint32_t u1WriteThru : 1;
1302	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1303	uint32_t u1CacheDisable : 1;
1304	/** Accessed flag.
1305	* Indicates that the page have been read or written to. */
1306	uint32_t u1Accessed : 1;
1307	/** Dirty flag.
1308	* Indicates that the page has been written to. */
1309	uint32_t u1Dirty : 1;
1310	/** Reserved / If PAT enabled, bit 2 of the index. */
1311	uint32_t u1PAT : 1;
1312	/** Global flag. (Ignored in all but final level.) */
1313	uint32_t u1Global : 1;
1314	/** Available for use to system software. */
1315	uint32_t u3Available : 3;
1316	/** Physical Page number of the next level - Low Part. Don't use this. */
1317	uint32_t u20PageNoLow : 20;
1318	/** Physical Page number of the next level - High Part. Don't use this. */
1319	uint32_t u20PageNoHigh : 20;
1320	/** MBZ bits */
1321	uint32_t u11Reserved : 11;
1322	/** No Execute flag. */
1323	uint32_t u1NoExecute : 1;
1324	} X86PTEPAEBITS;
1325	/** Pointer to a page table entry. */
1326	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1327	/** Pointer to a page table entry. */
1328	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1329
1330	/**
1331	* PAE Page table entry.
1332	*/
1333	typedef union X86PTEPAE
1334	{
1335	/** Unsigned integer view */
1336	X86PGPAEUINT u;
1337	/** Bit field view. */
1338	X86PTEPAEBITS n;
1339	/** 32-bit view. */
1340	uint32_t au32[2];
1341	/** 16-bit view. */
1342	uint16_t au16[4];
1343	/** 8-bit view. */
1344	uint8_t au8[8];
1345	} X86PTEPAE;
1346	/** Pointer to a PAE page table entry. */
1347	typedef X86PTEPAE *PX86PTEPAE;
1348	/** Pointer to a const PAE page table entry. */
1349	typedef const X86PTEPAE *PCX86PTEPAE;
1350	/** @} */
1351
1352	/**
1353	* Page table.
1354	*/
1355	typedef struct X86PT
1356	{
1357	/** PTE Array. */
1358	X86PTE a[X86_PG_ENTRIES];
1359	} X86PT;
1360	/** Pointer to a page table. */
1361	typedef X86PT *PX86PT;
1362	/** Pointer to a const page table. */
1363	typedef const X86PT *PCX86PT;
1364
1365	/** The page shift to get the PT index. */
1366	#define X86_PT_SHIFT 12
1367	/** The PT index mask (apply to a shifted page address). */
1368	#define X86_PT_MASK 0x3ff
1369
1370
1371	/**
1372	* Page directory.
1373	*/
1374	typedef struct X86PTPAE
1375	{
1376	/** PTE Array. */
1377	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1378	} X86PTPAE;
1379	/** Pointer to a page table. */
1380	typedef X86PTPAE *PX86PTPAE;
1381	/** Pointer to a const page table. */
1382	typedef const X86PTPAE *PCX86PTPAE;
1383
1384	/** The page shift to get the PA PTE index. */
1385	#define X86_PT_PAE_SHIFT 12
1386	/** The PAE PT index mask (apply to a shifted page address). */
1387	#define X86_PT_PAE_MASK 0x1ff
1388
1389
1390	/** @name 4KB Page Directory Entry
1391	* @{
1392	*/
1393	/** Bit 0 - P - Present bit. */
1394	#define X86_PDE_P RT_BIT(0)
1395	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1396	#define X86_PDE_RW RT_BIT(1)
1397	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1398	#define X86_PDE_US RT_BIT(2)
1399	/** Bit 3 - PWT - Page level write thru bit. */
1400	#define X86_PDE_PWT RT_BIT(3)
1401	/** Bit 4 - PCD - Page level cache disable bit. */
1402	#define X86_PDE_PCD RT_BIT(4)
1403	/** Bit 5 - A - Access bit. */
1404	#define X86_PDE_A RT_BIT(5)
1405	/** Bit 7 - PS - Page size attribute.
1406	* Clear mean 4KB pages, set means large pages (2/4MB). */
1407	#define X86_PDE_PS RT_BIT(7)
1408	/** Bits 9-11 - - Available for use to system software. */
1409	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1410	/** Bits 12-31 - - Physical Page number of the next level. */
1411	#define X86_PDE_PG_MASK ( 0xfffff000 )
1412
1413	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1414	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1415	/** Bits 63 - NX - PAE/LM - No execution flag. */
1416	#define X86_PDE_PAE_NX RT_BIT_64(63)
1417	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1418	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1419	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1420	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1421	/** Bit 7 - - LM - MBZ bits when NX is active. */
1422	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1423	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1424	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1425
1426	/**
1427	* Page directory entry.
1428	*/
1429	typedef struct X86PDEBITS
1430	{
1431	/** Flags whether(=1) or not the page is present. */
1432	unsigned u1Present : 1;
1433	/** Read(=0) / Write(=1) flag. */
1434	unsigned u1Write : 1;
1435	/** User(=1) / Supervisor (=0) flag. */
1436	unsigned u1User : 1;
1437	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1438	unsigned u1WriteThru : 1;
1439	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1440	unsigned u1CacheDisable : 1;
1441	/** Accessed flag.
1442	* Indicates that the page has been read or written to. */
1443	unsigned u1Accessed : 1;
1444	/** Reserved / Ignored (dirty bit). */
1445	unsigned u1Reserved0 : 1;
1446	/** Size bit if PSE is enabled - in any event it's 0. */
1447	unsigned u1Size : 1;
1448	/** Reserved / Ignored (global bit). */
1449	unsigned u1Reserved1 : 1;
1450	/** Available for use to system software. */
1451	unsigned u3Available : 3;
1452	/** Physical Page number of the next level. */
1453	unsigned u20PageNo : 20;
1454	} X86PDEBITS;
1455	/** Pointer to a page directory entry. */
1456	typedef X86PDEBITS *PX86PDEBITS;
1457	/** Pointer to a const page directory entry. */
1458	typedef const X86PDEBITS *PCX86PDEBITS;
1459
1460
1461	/**
1462	* PAE page directory entry.
1463	*/
1464	typedef struct X86PDEPAEBITS
1465	{
1466	/** Flags whether(=1) or not the page is present. */
1467	uint32_t u1Present : 1;
1468	/** Read(=0) / Write(=1) flag. */
1469	uint32_t u1Write : 1;
1470	/** User(=1) / Supervisor (=0) flag. */
1471	uint32_t u1User : 1;
1472	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1473	uint32_t u1WriteThru : 1;
1474	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1475	uint32_t u1CacheDisable : 1;
1476	/** Accessed flag.
1477	* Indicates that the page has been read or written to. */
1478	uint32_t u1Accessed : 1;
1479	/** Reserved / Ignored (dirty bit). */
1480	uint32_t u1Reserved0 : 1;
1481	/** Size bit if PSE is enabled - in any event it's 0. */
1482	uint32_t u1Size : 1;
1483	/** Reserved / Ignored (global bit). / */
1484	uint32_t u1Reserved1 : 1;
1485	/** Available for use to system software. */
1486	uint32_t u3Available : 3;
1487	/** Physical Page number of the next level - Low Part. Don't use! */
1488	uint32_t u20PageNoLow : 20;
1489	/** Physical Page number of the next level - High Part. Don't use! */
1490	uint32_t u20PageNoHigh : 20;
1491	/** MBZ bits */
1492	uint32_t u11Reserved : 11;
1493	/** No Execute flag. */
1494	uint32_t u1NoExecute : 1;
1495	} X86PDEPAEBITS;
1496	/** Pointer to a page directory entry. */
1497	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1498	/** Pointer to a const page directory entry. */
1499	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1500
1501	/** @} */
1502
1503
1504	/** @name 2/4MB Page Directory Entry
1505	* @{
1506	*/
1507	/** Bit 0 - P - Present bit. */
1508	#define X86_PDE4M_P RT_BIT(0)
1509	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1510	#define X86_PDE4M_RW RT_BIT(1)
1511	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1512	#define X86_PDE4M_US RT_BIT(2)
1513	/** Bit 3 - PWT - Page level write thru bit. */
1514	#define X86_PDE4M_PWT RT_BIT(3)
1515	/** Bit 4 - PCD - Page level cache disable bit. */
1516	#define X86_PDE4M_PCD RT_BIT(4)
1517	/** Bit 5 - A - Access bit. */
1518	#define X86_PDE4M_A RT_BIT(5)
1519	/** Bit 6 - D - Dirty bit. */
1520	#define X86_PDE4M_D RT_BIT(6)
1521	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1522	#define X86_PDE4M_PS RT_BIT(7)
1523	/** Bit 8 - G - Global flag. */
1524	#define X86_PDE4M_G RT_BIT(8)
1525	/** Bits 9-11 - AVL - Available for use to system software. */
1526	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1527	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1528	#define X86_PDE4M_PAT RT_BIT(12)
1529	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1530	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1531	/** Bits 22-31 - - Physical Page number. */
1532	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1533	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1534	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1535	/** The number of bits to the high part of the page number. */
1536	#define X86_PDE4M_PG_HIGH_SHIFT 19
1537	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1538	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1539
1540	/** Bits 21-51 - - PAE/LM - Physical Page number.
1541	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1542	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1543	/** Bits 63 - NX - PAE/LM - No execution flag. */
1544	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1545	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1546	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1547	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1548	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1549	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1550	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1551	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1552	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1553
1554	/**
1555	* 4MB page directory entry.
1556	*/
1557	typedef struct X86PDE4MBITS
1558	{
1559	/** Flags whether(=1) or not the page is present. */
1560	unsigned u1Present : 1;
1561	/** Read(=0) / Write(=1) flag. */
1562	unsigned u1Write : 1;
1563	/** User(=1) / Supervisor (=0) flag. */
1564	unsigned u1User : 1;
1565	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1566	unsigned u1WriteThru : 1;
1567	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1568	unsigned u1CacheDisable : 1;
1569	/** Accessed flag.
1570	* Indicates that the page have been read or written to. */
1571	unsigned u1Accessed : 1;
1572	/** Dirty flag.
1573	* Indicates that the page has been written to. */
1574	unsigned u1Dirty : 1;
1575	/** Page size flag - always 1 for 4MB entries. */
1576	unsigned u1Size : 1;
1577	/** Global flag. */
1578	unsigned u1Global : 1;
1579	/** Available for use to system software. */
1580	unsigned u3Available : 3;
1581	/** Reserved / If PAT enabled, bit 2 of the index. */
1582	unsigned u1PAT : 1;
1583	/** Bits 32-39 of the page number on AMD64.
1584	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1585	unsigned u8PageNoHigh : 8;
1586	/** Reserved. */
1587	unsigned u1Reserved : 1;
1588	/** Physical Page number of the page. */
1589	unsigned u10PageNo : 10;
1590	} X86PDE4MBITS;
1591	/** Pointer to a page table entry. */
1592	typedef X86PDE4MBITS *PX86PDE4MBITS;
1593	/** Pointer to a const page table entry. */
1594	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1595
1596
1597	/**
1598	* 2MB PAE page directory entry.
1599	*/
1600	typedef struct X86PDE2MPAEBITS
1601	{
1602	/** Flags whether(=1) or not the page is present. */
1603	uint32_t u1Present : 1;
1604	/** Read(=0) / Write(=1) flag. */
1605	uint32_t u1Write : 1;
1606	/** User(=1) / Supervisor(=0) flag. */
1607	uint32_t u1User : 1;
1608	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1609	uint32_t u1WriteThru : 1;
1610	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1611	uint32_t u1CacheDisable : 1;
1612	/** Accessed flag.
1613	* Indicates that the page have been read or written to. */
1614	uint32_t u1Accessed : 1;
1615	/** Dirty flag.
1616	* Indicates that the page has been written to. */
1617	uint32_t u1Dirty : 1;
1618	/** Page size flag - always 1 for 2MB entries. */
1619	uint32_t u1Size : 1;
1620	/** Global flag. */
1621	uint32_t u1Global : 1;
1622	/** Available for use to system software. */
1623	uint32_t u3Available : 3;
1624	/** Reserved / If PAT enabled, bit 2 of the index. */
1625	uint32_t u1PAT : 1;
1626	/** Reserved. */
1627	uint32_t u9Reserved : 9;
1628	/** Physical Page number of the next level - Low part. Don't use! */
1629	uint32_t u10PageNoLow : 10;
1630	/** Physical Page number of the next level - High part. Don't use! */
1631	uint32_t u20PageNoHigh : 20;
1632	/** MBZ bits */
1633	uint32_t u11Reserved : 11;
1634	/** No Execute flag. */
1635	uint32_t u1NoExecute : 1;
1636	} X86PDE2MPAEBITS;
1637	/** Pointer to a 2MB PAE page table entry. */
1638	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1639	/** Pointer to a 2MB PAE page table entry. */
1640	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1641
1642	/** @} */
1643
1644	/**
1645	* Page directory entry.
1646	*/
1647	typedef union X86PDE
1648	{
1649	/** Unsigned integer view. */
1650	X86PGUINT u;
1651	/** Normal view. */
1652	X86PDEBITS n;
1653	/** 4MB view (big). */
1654	X86PDE4MBITS b;
1655	/** 8 bit unsigned integer view. */
1656	uint8_t au8[4];
1657	/** 16 bit unsigned integer view. */
1658	uint16_t au16[2];
1659	/** 32 bit unsigned integer view. */
1660	uint32_t au32[1];
1661	} X86PDE;
1662	/** Pointer to a page directory entry. */
1663	typedef X86PDE *PX86PDE;
1664	/** Pointer to a const page directory entry. */
1665	typedef const X86PDE *PCX86PDE;
1666
1667	/**
1668	* PAE page directory entry.
1669	*/
1670	typedef union X86PDEPAE
1671	{
1672	/** Unsigned integer view. */
1673	X86PGPAEUINT u;
1674	/** Normal view. */
1675	X86PDEPAEBITS n;
1676	/** 2MB page view (big). */
1677	X86PDE2MPAEBITS b;
1678	/** 8 bit unsigned integer view. */
1679	uint8_t au8[8];
1680	/** 16 bit unsigned integer view. */
1681	uint16_t au16[4];
1682	/** 32 bit unsigned integer view. */
1683	uint32_t au32[2];
1684	} X86PDEPAE;
1685	/** Pointer to a page directory entry. */
1686	typedef X86PDEPAE *PX86PDEPAE;
1687	/** Pointer to a const page directory entry. */
1688	typedef const X86PDEPAE *PCX86PDEPAE;
1689
1690	/**
1691	* Page directory.
1692	*/
1693	typedef struct X86PD
1694	{
1695	/** PDE Array. */
1696	X86PDE a[X86_PG_ENTRIES];
1697	} X86PD;
1698	/** Pointer to a page directory. */
1699	typedef X86PD *PX86PD;
1700	/** Pointer to a const page directory. */
1701	typedef const X86PD *PCX86PD;
1702
1703	/** The page shift to get the PD index. */
1704	#define X86_PD_SHIFT 22
1705	/** The PD index mask (apply to a shifted page address). */
1706	#define X86_PD_MASK 0x3ff
1707
1708
1709	/**
1710	* PAE page directory.
1711	*/
1712	typedef struct X86PDPAE
1713	{
1714	/** PDE Array. */
1715	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1716	} X86PDPAE;
1717	/** Pointer to a PAE page directory. */
1718	typedef X86PDPAE *PX86PDPAE;
1719	/** Pointer to a const PAE page directory. */
1720	typedef const X86PDPAE *PCX86PDPAE;
1721
1722	/** The page shift to get the PAE PD index. */
1723	#define X86_PD_PAE_SHIFT 21
1724	/** The PAE PD index mask (apply to a shifted page address). */
1725	#define X86_PD_PAE_MASK 0x1ff
1726
1727
1728	/** @name Page Directory Pointer Table Entry (PAE)
1729	* @{
1730	*/
1731	/** Bit 0 - P - Present bit. */
1732	#define X86_PDPE_P RT_BIT(0)
1733	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1734	#define X86_PDPE_RW RT_BIT(1)
1735	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1736	#define X86_PDPE_US RT_BIT(2)
1737	/** Bit 3 - PWT - Page level write thru bit. */
1738	#define X86_PDPE_PWT RT_BIT(3)
1739	/** Bit 4 - PCD - Page level cache disable bit. */
1740	#define X86_PDPE_PCD RT_BIT(4)
1741	/** Bit 5 - A - Access bit. Long Mode only. */
1742	#define X86_PDPE_A RT_BIT(5)
1743	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1744	#define X86_PDPE_LM_PS RT_BIT(7)
1745	/** Bits 9-11 - - Available for use to system software. */
1746	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1747	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1748	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1749	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1750	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1751	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1752	#define X86_PDPE_LM_NX RT_BIT_64(63)
1753	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1754	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1755	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1756	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1757	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1758	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1759	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1760	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1761
1762
1763	/**
1764	* Page directory pointer table entry.
1765	*/
1766	typedef struct X86PDPEBITS
1767	{
1768	/** Flags whether(=1) or not the page is present. */
1769	uint32_t u1Present : 1;
1770	/** Chunk of reserved bits. */
1771	uint32_t u2Reserved : 2;
1772	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1773	uint32_t u1WriteThru : 1;
1774	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1775	uint32_t u1CacheDisable : 1;
1776	/** Chunk of reserved bits. */
1777	uint32_t u4Reserved : 4;
1778	/** Available for use to system software. */
1779	uint32_t u3Available : 3;
1780	/** Physical Page number of the next level - Low Part. Don't use! */
1781	uint32_t u20PageNoLow : 20;
1782	/** Physical Page number of the next level - High Part. Don't use! */
1783	uint32_t u20PageNoHigh : 20;
1784	/** MBZ bits */
1785	uint32_t u12Reserved : 12;
1786	} X86PDPEBITS;
1787	/** Pointer to a page directory pointer table entry. */
1788	typedef X86PDPEBITS *PX86PTPEBITS;
1789	/** Pointer to a const page directory pointer table entry. */
1790	typedef const X86PDPEBITS *PCX86PTPEBITS;
1791
1792	/**
1793	* Page directory pointer table entry. AMD64 version
1794	*/
1795	typedef struct X86PDPEAMD64BITS
1796	{
1797	/** Flags whether(=1) or not the page is present. */
1798	uint32_t u1Present : 1;
1799	/** Read(=0) / Write(=1) flag. */
1800	uint32_t u1Write : 1;
1801	/** User(=1) / Supervisor (=0) flag. */
1802	uint32_t u1User : 1;
1803	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1804	uint32_t u1WriteThru : 1;
1805	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1806	uint32_t u1CacheDisable : 1;
1807	/** Accessed flag.
1808	* Indicates that the page have been read or written to. */
1809	uint32_t u1Accessed : 1;
1810	/** Chunk of reserved bits. */
1811	uint32_t u3Reserved : 3;
1812	/** Available for use to system software. */
1813	uint32_t u3Available : 3;
1814	/** Physical Page number of the next level - Low Part. Don't use! */
1815	uint32_t u20PageNoLow : 20;
1816	/** Physical Page number of the next level - High Part. Don't use! */
1817	uint32_t u20PageNoHigh : 20;
1818	/** MBZ bits */
1819	uint32_t u11Reserved : 11;
1820	/** No Execute flag. */
1821	uint32_t u1NoExecute : 1;
1822	} X86PDPEAMD64BITS;
1823	/** Pointer to a page directory pointer table entry. */
1824	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1825	/** Pointer to a const page directory pointer table entry. */
1826	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1827
1828	/**
1829	* Page directory pointer table entry.
1830	*/
1831	typedef union X86PDPE
1832	{
1833	/** Unsigned integer view. */
1834	X86PGPAEUINT u;
1835	/** Normal view. */
1836	X86PDPEBITS n;
1837	/** AMD64 view. */
1838	X86PDPEAMD64BITS lm;
1839	/** 8 bit unsigned integer view. */
1840	uint8_t au8[8];
1841	/** 16 bit unsigned integer view. */
1842	uint16_t au16[4];
1843	/** 32 bit unsigned integer view. */
1844	uint32_t au32[2];
1845	} X86PDPE;
1846	/** Pointer to a page directory pointer table entry. */
1847	typedef X86PDPE *PX86PDPE;
1848	/** Pointer to a const page directory pointer table entry. */
1849	typedef const X86PDPE *PCX86PDPE;
1850
1851
1852	/**
1853	* Page directory pointer table.
1854	*/
1855	typedef struct X86PDPT
1856	{
1857	/** PDE Array. */
1858	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1859	} X86PDPT;
1860	/** Pointer to a page directory pointer table. */
1861	typedef X86PDPT *PX86PDPT;
1862	/** Pointer to a const page directory pointer table. */
1863	typedef const X86PDPT *PCX86PDPT;
1864
1865	/** The page shift to get the PDPT index. */
1866	#define X86_PDPT_SHIFT 30
1867	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1868	#define X86_PDPT_MASK_PAE 0x3
1869	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1870	#define X86_PDPT_MASK_AMD64 0x1ff
1871
1872	/** @} */
1873
1874
1875	/** @name Page Map Level-4 Entry (Long Mode PAE)
1876	* @{
1877	*/
1878	/** Bit 0 - P - Present bit. */
1879	#define X86_PML4E_P RT_BIT(0)
1880	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1881	#define X86_PML4E_RW RT_BIT(1)
1882	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1883	#define X86_PML4E_US RT_BIT(2)
1884	/** Bit 3 - PWT - Page level write thru bit. */
1885	#define X86_PML4E_PWT RT_BIT(3)
1886	/** Bit 4 - PCD - Page level cache disable bit. */
1887	#define X86_PML4E_PCD RT_BIT(4)
1888	/** Bit 5 - A - Access bit. */
1889	#define X86_PML4E_A RT_BIT(5)
1890	/** Bits 9-11 - - Available for use to system software. */
1891	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1892	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1893	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1894	/** Bits 8, 7 - - MBZ bits when NX is active. */
1895	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1896	/** Bits 63, 7 - - MBZ bits when no NX. */
1897	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1898	/** Bits 63 - NX - PAE - No execution flag. */
1899	#define X86_PML4E_NX RT_BIT_64(63)
1900
1901	/**
1902	* Page Map Level-4 Entry
1903	*/
1904	typedef struct X86PML4EBITS
1905	{
1906	/** Flags whether(=1) or not the page is present. */
1907	uint32_t u1Present : 1;
1908	/** Read(=0) / Write(=1) flag. */
1909	uint32_t u1Write : 1;
1910	/** User(=1) / Supervisor (=0) flag. */
1911	uint32_t u1User : 1;
1912	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1913	uint32_t u1WriteThru : 1;
1914	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1915	uint32_t u1CacheDisable : 1;
1916	/** Accessed flag.
1917	* Indicates that the page have been read or written to. */
1918	uint32_t u1Accessed : 1;
1919	/** Chunk of reserved bits. */
1920	uint32_t u3Reserved : 3;
1921	/** Available for use to system software. */
1922	uint32_t u3Available : 3;
1923	/** Physical Page number of the next level - Low Part. Don't use! */
1924	uint32_t u20PageNoLow : 20;
1925	/** Physical Page number of the next level - High Part. Don't use! */
1926	uint32_t u20PageNoHigh : 20;
1927	/** MBZ bits */
1928	uint32_t u11Reserved : 11;
1929	/** No Execute flag. */
1930	uint32_t u1NoExecute : 1;
1931	} X86PML4EBITS;
1932	/** Pointer to a page map level-4 entry. */
1933	typedef X86PML4EBITS *PX86PML4EBITS;
1934	/** Pointer to a const page map level-4 entry. */
1935	typedef const X86PML4EBITS *PCX86PML4EBITS;
1936
1937	/**
1938	* Page Map Level-4 Entry.
1939	*/
1940	typedef union X86PML4E
1941	{
1942	/** Unsigned integer view. */
1943	X86PGPAEUINT u;
1944	/** Normal view. */
1945	X86PML4EBITS n;
1946	/** 8 bit unsigned integer view. */
1947	uint8_t au8[8];
1948	/** 16 bit unsigned integer view. */
1949	uint16_t au16[4];
1950	/** 32 bit unsigned integer view. */
1951	uint32_t au32[2];
1952	} X86PML4E;
1953	/** Pointer to a page map level-4 entry. */
1954	typedef X86PML4E *PX86PML4E;
1955	/** Pointer to a const page map level-4 entry. */
1956	typedef const X86PML4E *PCX86PML4E;
1957
1958
1959	/**
1960	* Page Map Level-4.
1961	*/
1962	typedef struct X86PML4
1963	{
1964	/** PDE Array. */
1965	X86PML4E a[X86_PG_PAE_ENTRIES];
1966	} X86PML4;
1967	/** Pointer to a page map level-4. */
1968	typedef X86PML4 *PX86PML4;
1969	/** Pointer to a const page map level-4. */
1970	typedef const X86PML4 *PCX86PML4;
1971
1972	/** The page shift to get the PML4 index. */
1973	#define X86_PML4_SHIFT 39
1974	/** The PML4 index mask (apply to a shifted page address). */
1975	#define X86_PML4_MASK 0x1ff
1976
1977	/** @} */
1978
1979	/** @} */
1980
1981
1982	/**
1983	* 80-bit MMX/FPU register type.
1984	*/
1985	typedef struct X86FPUMMX
1986	{
1987	uint8_t reg[10];
1988	} X86FPUMMX;
1989	/** Pointer to a 80-bit MMX/FPU register type. */
1990	typedef X86FPUMMX *PX86FPUMMX;
1991	/** Pointer to a const 80-bit MMX/FPU register type. */
1992	typedef const X86FPUMMX *PCX86FPUMMX;
1993
1994	/**
1995	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
1996	* @todo verify this...
1997	*/
1998	#pragma pack(1)
1999	typedef struct X86FPUSTATE
2000	{
2001	/** 0x00 - Control word. */
2002	uint16_t FCW;
2003	/** 0x02 - Alignment word */
2004	uint16_t Dummy1;
2005	/** 0x04 - Status word. */
2006	uint16_t FSW;
2007	/** 0x06 - Alignment word */
2008	uint16_t Dummy2;
2009	/** 0x08 - Tag word */
2010	uint16_t FTW;
2011	/** 0x0a - Alignment word */
2012	uint16_t Dummy3;
2013
2014	/** 0x0c - Instruction pointer. */
2015	uint32_t FPUIP;
2016	/** 0x10 - Code selector. */
2017	uint16_t CS;
2018	/** 0x12 - Opcode. */
2019	uint16_t FOP;
2020	/** 0x14 - FOO. */
2021	uint32_t FPUOO;
2022	/** 0x18 - FOS. */
2023	uint32_t FPUOS;
2024	/** 0x1c */
2025	union
2026	{
2027	/** MMX view. */
2028	uint64_t mmx;
2029	/** FPU view - todo. */
2030	X86FPUMMX fpu;
2031	/** Extended precision floating point view. */
2032	RTFLOAT80U r80;
2033	/** Extended precision floating point view v2. */
2034	RTFLOAT80U2 r80Ex;
2035	/** 8-bit view. */
2036	uint8_t au8[16];
2037	/** 16-bit view. */
2038	uint16_t au16[8];
2039	/** 32-bit view. */
2040	uint32_t au32[4];
2041	/** 64-bit view. */
2042	uint64_t au64[2];
2043	/** 128-bit view. (yeah, very helpful) */
2044	uint128_t au128[1];
2045	} regs[8];
2046	} X86FPUSTATE;
2047	#pragma pack()
2048	/** Pointer to a FPU state. */
2049	typedef X86FPUSTATE *PX86FPUSTATE;
2050	/** Pointer to a const FPU state. */
2051	typedef const X86FPUSTATE *PCX86FPUSTATE;
2052
2053	/**
2054	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2055	*/
2056	#pragma pack(1)
2057	typedef struct X86FXSTATE
2058	{
2059	/** 0x00 - Control word. */
2060	uint16_t FCW;
2061	/** 0x02 - Status word. */
2062	uint16_t FSW;
2063	/** 0x04 - Tag word. (The upper byte is always zero.) */
2064	uint16_t FTW;
2065	/** 0x06 - Opcode. */
2066	uint16_t FOP;
2067	/** 0x08 - Instruction pointer. */
2068	uint32_t FPUIP;
2069	/** 0x0c - Code selector. */
2070	uint16_t CS;
2071	uint16_t Rsrvd1;
2072	/** 0x10 - Data pointer. */
2073	uint32_t FPUDP;
2074	/** 0x14 - Data segment */
2075	uint16_t DS;
2076	/** 0x16 */
2077	uint16_t Rsrvd2;
2078	/** 0x18 */
2079	uint32_t MXCSR;
2080	/** 0x1c */
2081	uint32_t MXCSR_MASK;
2082	/** 0x20 */
2083	union
2084	{
2085	/** MMX view. */
2086	uint64_t mmx;
2087	/** FPU view - todo. */
2088	X86FPUMMX fpu;
2089	/** Extended precision floating point view. */
2090	RTFLOAT80U r80;
2091	/** Extended precision floating point view v2 */
2092	RTFLOAT80U2 r80Ex;
2093	/** 8-bit view. */
2094	uint8_t au8[16];
2095	/** 16-bit view. */
2096	uint16_t au16[8];
2097	/** 32-bit view. */
2098	uint32_t au32[4];
2099	/** 64-bit view. */
2100	uint64_t au64[2];
2101	/** 128-bit view. (yeah, very helpful) */
2102	uint128_t au128[1];
2103	} aRegs[8];
2104	/* - offset 160 - */
2105	union
2106	{
2107	/** XMM Register view . /
2108	uint128_t xmm;
2109	/** 8-bit view. */
2110	uint8_t au8[16];
2111	/** 16-bit view. */
2112	uint16_t au16[8];
2113	/** 32-bit view. */
2114	uint32_t au32[4];
2115	/** 64-bit view. */
2116	uint64_t au64[2];
2117	/** 128-bit view. (yeah, very helpful) */
2118	uint128_t au128[1];
2119	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2120	/* - offset 416 - */
2121	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2122	} X86FXSTATE;
2123	#pragma pack()
2124	/** Pointer to a FPU Extended state. */
2125	typedef X86FXSTATE *PX86FXSTATE;
2126	/** Pointer to a const FPU Extended state. */
2127	typedef const X86FXSTATE *PCX86FXSTATE;
2128
2129	/** @name FPU status word flags.
2130	* @{ */
2131	/** Exception Flag: Invalid operation. */
2132	#define X86_FSW_IE RT_BIT(0)
2133	/** Exception Flag: Denormalized operand. */
2134	#define X86_FSW_DE RT_BIT(1)
2135	/** Exception Flag: Zero divide. */
2136	#define X86_FSW_ZE RT_BIT(2)
2137	/** Exception Flag: Overflow. */
2138	#define X86_FSW_OE RT_BIT(3)
2139	/** Exception Flag: Underflow. */
2140	#define X86_FSW_UE RT_BIT(4)
2141	/** Exception Flag: Precision. */
2142	#define X86_FSW_PE RT_BIT(5)
2143	/** Stack fault. */
2144	#define X86_FSW_SF RT_BIT(6)
2145	/** Error summary status. */
2146	#define X86_FSW_ES RT_BIT(7)
2147	/** Mask of exceptions flags, excluding the summary bit. */
2148	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2149	/** Mask of exceptions flags, including the summary bit. */
2150	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2151	/** Condition code 0. */
2152	#define X86_FSW_C0 RT_BIT(8)
2153	/** Condition code 1. */
2154	#define X86_FSW_C1 RT_BIT(9)
2155	/** Condition code 2. */
2156	#define X86_FSW_C2 RT_BIT(10)
2157	/** Top of the stack mask. */
2158	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2159	/** TOP shift value. */
2160	#define X86_FSW_TOP_SHIFT 11
2161	/** Mask for getting TOP value after shifting it right. */
2162	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2163	/** Get the TOP value. */
2164	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2165	/** Condition code 3. */
2166	#define X86_FSW_C3 RT_BIT(14)
2167	/** Mask of exceptions flags, including the summary bit. */
2168	#define X86_FSW_C_MASK UINT16_C(0x4700)
2169	/** FPU busy. */
2170	#define X86_FSW_B RT_BIT(15)
2171	/** @} */
2172
2173
2174	/** @name FPU control word flags.
2175	* @{ */
2176	/** Exception Mask: Invalid operation. */
2177	#define X86_FCW_IM RT_BIT(0)
2178	/** Exception Mask: Denormalized operand. */
2179	#define X86_FCW_DM RT_BIT(1)
2180	/** Exception Mask: Zero divide. */
2181	#define X86_FCW_ZM RT_BIT(2)
2182	/** Exception Mask: Overflow. */
2183	#define X86_FCW_OM RT_BIT(3)
2184	/** Exception Mask: Underflow. */
2185	#define X86_FCW_UM RT_BIT(4)
2186	/** Exception Mask: Precision. */
2187	#define X86_FCW_PM RT_BIT(5)
2188	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2189	* @remarks This includes reserved bit 6. */
2190	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2191	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2192	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2193	/** Precision control mask. */
2194	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2195	/** Precision control: 24-bit. */
2196	#define X86_FCW_PC_24 UINT16_C(0x0000)
2197	/** Precision control: Reserved. */
2198	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2199	/** Precision control: 53-bit. */
2200	#define X86_FCW_PC_53 UINT16_C(0x0200)
2201	/** Precision control: 64-bit. */
2202	#define X86_FCW_PC_64 UINT16_C(0x0300)
2203	/** Rounding control mask. */
2204	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2205	/** Rounding control: To nearest. */
2206	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2207	/** Rounding control: Down. */
2208	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2209	/** Rounding control: Up. */
2210	#define X86_FCW_RC_UP UINT16_C(0x0800)
2211	/** Rounding control: Towards zero. */
2212	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2213	/** Bits which should be zero, apparently. */
2214	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2215	/** @} */
2216
2217
2218	/** @name Selector Descriptor
2219	* @{
2220	*/
2221
2222	#ifndef VBOX_FOR_DTRACE_LIB
2223	/**
2224	* Descriptor attributes.
2225	*/
2226	typedef struct X86DESCATTRBITS
2227	{
2228	/** 00 - Segment Type. */
2229	unsigned u4Type : 4;
2230	/** 04 - Descriptor Type. System(=0) or code/data selector */
2231	unsigned u1DescType : 1;
2232	/** 05 - Descriptor Privelege level. */
2233	unsigned u2Dpl : 2;
2234	/** 07 - Flags selector present(=1) or not. */
2235	unsigned u1Present : 1;
2236	/** 08 - Segment limit 16-19. */
2237	unsigned u4LimitHigh : 4;
2238	/** 0c - Available for system software. */
2239	unsigned u1Available : 1;
2240	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2241	unsigned u1Long : 1;
2242	/** 0e - This flags meaning depends on the segment type. Try make sense out
2243	* of the intel manual yourself. */
2244	unsigned u1DefBig : 1;
2245	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2246	* clear byte. */
2247	unsigned u1Granularity : 1;
2248	} X86DESCATTRBITS;
2249	#endif /* !VBOX_FOR_DTRACE_LIB */
2250
2251	#pragma pack(1)
2252	typedef union X86DESCATTR
2253	{
2254	/** Unsigned integer view. */
2255	uint32_t u;
2256	#ifndef VBOX_FOR_DTRACE_LIB
2257	/** Normal view. */
2258	X86DESCATTRBITS n;
2259	#endif
2260	} X86DESCATTR;
2261	#pragma pack()
2262	/** Pointer to descriptor attributes. */
2263	typedef X86DESCATTR *PX86DESCATTR;
2264	/** Pointer to const descriptor attributes. */
2265	typedef const X86DESCATTR *PCX86DESCATTR;
2266
2267	#ifndef VBOX_FOR_DTRACE_LIB
2268
2269	/**
2270	* Generic descriptor table entry
2271	*/
2272	#pragma pack(1)
2273	typedef struct X86DESCGENERIC
2274	{
2275	/** Limit - Low word. */
2276	unsigned u16LimitLow : 16;
2277	/** Base address - lowe word.
2278	* Don't try set this to 24 because MSC is doing stupid things then. */
2279	unsigned u16BaseLow : 16;
2280	/** Base address - first 8 bits of high word. */
2281	unsigned u8BaseHigh1 : 8;
2282	/** Segment Type. */
2283	unsigned u4Type : 4;
2284	/** Descriptor Type. System(=0) or code/data selector */
2285	unsigned u1DescType : 1;
2286	/** Descriptor Privelege level. */
2287	unsigned u2Dpl : 2;
2288	/** Flags selector present(=1) or not. */
2289	unsigned u1Present : 1;
2290	/** Segment limit 16-19. */
2291	unsigned u4LimitHigh : 4;
2292	/** Available for system software. */
2293	unsigned u1Available : 1;
2294	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2295	unsigned u1Long : 1;
2296	/** This flags meaning depends on the segment type. Try make sense out
2297	* of the intel manual yourself. */
2298	unsigned u1DefBig : 1;
2299	/** Granularity of the limit. If set 4KB granularity is used, if
2300	* clear byte. */
2301	unsigned u1Granularity : 1;
2302	/** Base address - highest 8 bits. */
2303	unsigned u8BaseHigh2 : 8;
2304	} X86DESCGENERIC;
2305	#pragma pack()
2306	/** Pointer to a generic descriptor entry. */
2307	typedef X86DESCGENERIC *PX86DESCGENERIC;
2308	/** Pointer to a const generic descriptor entry. */
2309	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2310
2311	/**
2312	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2313	*/
2314	typedef struct X86DESCGATE
2315	{
2316	/** 00 - Target code segment offset - Low word.
2317	* Ignored if task-gate. */
2318	unsigned u16OffsetLow : 16;
2319	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2320	* TSS selector if task-gate. */
2321	unsigned u16Sel : 16;
2322	/** 20 - Number of parameters for a call-gate.
2323	* Ignored if interrupt-, trap- or task-gate. */
2324	unsigned u4ParmCount : 4;
2325	/** 24 - Reserved / ignored. */
2326	unsigned u4Reserved : 4;
2327	/** 28 - Segment Type. */
2328	unsigned u4Type : 4;
2329	/** 2c - Descriptor Type (0 = system). */
2330	unsigned u1DescType : 1;
2331	/** 2d - Descriptor Privelege level. */
2332	unsigned u2Dpl : 2;
2333	/** 2f - Flags selector present(=1) or not. */
2334	unsigned u1Present : 1;
2335	/** 30 - Target code segment offset - High word.
2336	* Ignored if task-gate. */
2337	unsigned u16OffsetHigh : 16;
2338	} X86DESCGATE;
2339	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2340	typedef X86DESCGATE *PX86DESCGATE;
2341	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2342	typedef const X86DESCGATE *PCX86DESCGATE;
2343
2344	#endif /* VBOX_FOR_DTRACE_LIB */
2345
2346	/**
2347	* Descriptor table entry.
2348	*/
2349	#pragma pack(1)
2350	typedef union X86DESC
2351	{
2352	#ifndef VBOX_FOR_DTRACE_LIB
2353	/** Generic descriptor view. */
2354	X86DESCGENERIC Gen;
2355	/** Gate descriptor view. */
2356	X86DESCGATE Gate;
2357	#endif
2358
2359	/** 8 bit unsigned integer view. */
2360	uint8_t au8[8];
2361	/** 16 bit unsigned integer view. */
2362	uint16_t au16[4];
2363	/** 32 bit unsigned integer view. */
2364	uint32_t au32[2];
2365	/** 64 bit unsigned integer view. */
2366	uint64_t au64[1];
2367	/** Unsigned integer view. */
2368	uint64_t u;
2369	} X86DESC;
2370	#ifndef VBOX_FOR_DTRACE_LIB
2371	AssertCompileSize(X86DESC, 8);
2372	#endif
2373	#pragma pack()
2374	/** Pointer to descriptor table entry. */
2375	typedef X86DESC *PX86DESC;
2376	/** Pointer to const descriptor table entry. */
2377	typedef const X86DESC *PCX86DESC;
2378
2379	/** @def X86DESC_BASE
2380	* Return the base address of a descriptor.
2381	*/
2382	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2383	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2384	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2385	\| ( (desc).Gen.u16BaseLow ) )
2386
2387	/** @def X86DESC_LIMIT
2388	* Return the limit of a descriptor.
2389	*/
2390	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2391	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2392	\| ( (desc).Gen.u16LimitLow ) )
2393
2394	/** @def X86DESC_GET_HID_ATTR
2395	* Get the descriptor attributes for the hidden register.
2396	*/
2397	#define X86DESC_GET_HID_ATTR(desc) /ASM-NOINC/ \
2398	( (desc.u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2399
2400	#ifndef VBOX_FOR_DTRACE_LIB
2401
2402	/**
2403	* 64 bits generic descriptor table entry
2404	* Note: most of these bits have no meaning in long mode.
2405	*/
2406	#pragma pack(1)
2407	typedef struct X86DESC64GENERIC
2408	{
2409	/** Limit - Low word - IGNORED. */
2410	unsigned u16LimitLow : 16;
2411	/** Base address - low word. - IGNORED
2412	* Don't try set this to 24 because MSC is doing stupid things then. */
2413	unsigned u16BaseLow : 16;
2414	/** Base address - first 8 bits of high word. - IGNORED */
2415	unsigned u8BaseHigh1 : 8;
2416	/** Segment Type. */
2417	unsigned u4Type : 4;
2418	/** Descriptor Type. System(=0) or code/data selector */
2419	unsigned u1DescType : 1;
2420	/** Descriptor Privelege level. */
2421	unsigned u2Dpl : 2;
2422	/** Flags selector present(=1) or not. */
2423	unsigned u1Present : 1;
2424	/** Segment limit 16-19. - IGNORED */
2425	unsigned u4LimitHigh : 4;
2426	/** Available for system software. - IGNORED */
2427	unsigned u1Available : 1;
2428	/** Long mode flag. */
2429	unsigned u1Long : 1;
2430	/** This flags meaning depends on the segment type. Try make sense out
2431	* of the intel manual yourself. */
2432	unsigned u1DefBig : 1;
2433	/** Granularity of the limit. If set 4KB granularity is used, if
2434	* clear byte. - IGNORED */
2435	unsigned u1Granularity : 1;
2436	/** Base address - highest 8 bits. - IGNORED */
2437	unsigned u8BaseHigh2 : 8;
2438	/** Base address - bits 63-32. */
2439	unsigned u32BaseHigh3 : 32;
2440	unsigned u8Reserved : 8;
2441	unsigned u5Zeros : 5;
2442	unsigned u19Reserved : 19;
2443	} X86DESC64GENERIC;
2444	#pragma pack()
2445	/** Pointer to a generic descriptor entry. */
2446	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2447	/** Pointer to a const generic descriptor entry. */
2448	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2449
2450	/**
2451	* System descriptor table entry (64 bits)
2452	*
2453	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2454	*/
2455	#pragma pack(1)
2456	typedef struct X86DESC64SYSTEM
2457	{
2458	/** Limit - Low word. */
2459	unsigned u16LimitLow : 16;
2460	/** Base address - lowe word.
2461	* Don't try set this to 24 because MSC is doing stupid things then. */
2462	unsigned u16BaseLow : 16;
2463	/** Base address - first 8 bits of high word. */
2464	unsigned u8BaseHigh1 : 8;
2465	/** Segment Type. */
2466	unsigned u4Type : 4;
2467	/** Descriptor Type. System(=0) or code/data selector */
2468	unsigned u1DescType : 1;
2469	/** Descriptor Privelege level. */
2470	unsigned u2Dpl : 2;
2471	/** Flags selector present(=1) or not. */
2472	unsigned u1Present : 1;
2473	/** Segment limit 16-19. */
2474	unsigned u4LimitHigh : 4;
2475	/** Available for system software. */
2476	unsigned u1Available : 1;
2477	/** Reserved - 0. */
2478	unsigned u1Reserved : 1;
2479	/** This flags meaning depends on the segment type. Try make sense out
2480	* of the intel manual yourself. */
2481	unsigned u1DefBig : 1;
2482	/** Granularity of the limit. If set 4KB granularity is used, if
2483	* clear byte. */
2484	unsigned u1Granularity : 1;
2485	/** Base address - bits 31-24. */
2486	unsigned u8BaseHigh2 : 8;
2487	/** Base address - bits 63-32. */
2488	unsigned u32BaseHigh3 : 32;
2489	unsigned u8Reserved : 8;
2490	unsigned u5Zeros : 5;
2491	unsigned u19Reserved : 19;
2492	} X86DESC64SYSTEM;
2493	#pragma pack()
2494	/** Pointer to a system descriptor entry. */
2495	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2496	/** Pointer to a const system descriptor entry. */
2497	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2498
2499	/**
2500	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2501	*/
2502	typedef struct X86DESC64GATE
2503	{
2504	/** Target code segment offset - Low word. */
2505	unsigned u16OffsetLow : 16;
2506	/** Target code segment selector. */
2507	unsigned u16Sel : 16;
2508	/** Interrupt stack table for interrupt- and trap-gates.
2509	* Ignored by call-gates. */
2510	unsigned u3IST : 3;
2511	/** Reserved / ignored. */
2512	unsigned u5Reserved : 5;
2513	/** Segment Type. */
2514	unsigned u4Type : 4;
2515	/** Descriptor Type (0 = system). */
2516	unsigned u1DescType : 1;
2517	/** Descriptor Privelege level. */
2518	unsigned u2Dpl : 2;
2519	/** Flags selector present(=1) or not. */
2520	unsigned u1Present : 1;
2521	/** Target code segment offset - High word.
2522	* Ignored if task-gate. */
2523	unsigned u16OffsetHigh : 16;
2524	/** Target code segment offset - Top dword.
2525	* Ignored if task-gate. */
2526	unsigned u32OffsetTop : 32;
2527	/** Reserved / ignored / must be zero.
2528	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2529	unsigned u32Reserved : 32;
2530	} X86DESC64GATE;
2531	AssertCompileSize(X86DESC64GATE, 16);
2532	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2533	typedef X86DESC64GATE *PX86DESC64GATE;
2534	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2535	typedef const X86DESC64GATE *PCX86DESC64GATE;
2536
2537	#endif /* VBOX_FOR_DTRACE_LIB */
2538
2539	/**
2540	* Descriptor table entry.
2541	*/
2542	#pragma pack(1)
2543	typedef union X86DESC64
2544	{
2545	#ifndef VBOX_FOR_DTRACE_LIB
2546	/** Generic descriptor view. */
2547	X86DESC64GENERIC Gen;
2548	/** System descriptor view. */
2549	X86DESC64SYSTEM System;
2550	/** Gate descriptor view. */
2551	X86DESC64GATE Gate;
2552	#endif
2553
2554	/** 8 bit unsigned integer view. */
2555	uint8_t au8[16];
2556	/** 16 bit unsigned integer view. */
2557	uint16_t au16[8];
2558	/** 32 bit unsigned integer view. */
2559	uint32_t au32[4];
2560	/** 64 bit unsigned integer view. */
2561	uint64_t au64[2];
2562	} X86DESC64;
2563	#ifndef VBOX_FOR_DTRACE_LIB
2564	AssertCompileSize(X86DESC64, 16);
2565	#endif
2566	#pragma pack()
2567	/** Pointer to descriptor table entry. */
2568	typedef X86DESC64 *PX86DESC64;
2569	/** Pointer to const descriptor table entry. */
2570	typedef const X86DESC64 *PCX86DESC64;
2571
2572	/** @def X86DESC64_BASE
2573	* Return the base of a 64-bit descriptor.
2574	*/
2575	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2576	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2577	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2578	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2579	\| ( (desc).Gen.u16BaseLow ) )
2580
2581
2582
2583	/** @name Host system descriptor table entry - Use with care!
2584	* @{ */
2585	/** Host system descriptor table entry. */
2586	#if HC_ARCH_BITS == 64
2587	typedef X86DESC64 X86DESCHC;
2588	#else
2589	typedef X86DESC X86DESCHC;
2590	#endif
2591	/** Pointer to a host system descriptor table entry. */
2592	#if HC_ARCH_BITS == 64
2593	typedef PX86DESC64 PX86DESCHC;
2594	#else
2595	typedef PX86DESC PX86DESCHC;
2596	#endif
2597	/** Pointer to a const host system descriptor table entry. */
2598	#if HC_ARCH_BITS == 64
2599	typedef PCX86DESC64 PCX86DESCHC;
2600	#else
2601	typedef PCX86DESC PCX86DESCHC;
2602	#endif
2603	/** @} */
2604
2605
2606	/** @name Selector Descriptor Types.
2607	* @{
2608	*/
2609
2610	/** @name Non-System Selector Types.
2611	* @{ */
2612	/** Code(=set)/Data(=clear) bit. */
2613	#define X86_SEL_TYPE_CODE 8
2614	/** Memory(=set)/System(=clear) bit. */
2615	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2616	/** Accessed bit. */
2617	#define X86_SEL_TYPE_ACCESSED 1
2618	/** Expand down bit (for data selectors only). */
2619	#define X86_SEL_TYPE_DOWN 4
2620	/** Conforming bit (for code selectors only). */
2621	#define X86_SEL_TYPE_CONF 4
2622	/** Write bit (for data selectors only). */
2623	#define X86_SEL_TYPE_WRITE 2
2624	/** Read bit (for code selectors only). */
2625	#define X86_SEL_TYPE_READ 2
2626
2627	/** Read only selector type. */
2628	#define X86_SEL_TYPE_RO 0
2629	/** Accessed read only selector type. */
2630	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2631	/** Read write selector type. */
2632	#define X86_SEL_TYPE_RW 2
2633	/** Accessed read write selector type. */
2634	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2635	/** Expand down read only selector type. */
2636	#define X86_SEL_TYPE_RO_DOWN 4
2637	/** Accessed expand down read only selector type. */
2638	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2639	/** Expand down read write selector type. */
2640	#define X86_SEL_TYPE_RW_DOWN 6
2641	/** Accessed expand down read write selector type. */
2642	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2643	/** Execute only selector type. */
2644	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2645	/** Accessed execute only selector type. */
2646	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2647	/** Execute and read selector type. */
2648	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2649	/** Accessed execute and read selector type. */
2650	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2651	/** Conforming execute only selector type. */
2652	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2653	/** Accessed Conforming execute only selector type. */
2654	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2655	/** Conforming execute and write selector type. */
2656	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2657	/** Accessed Conforming execute and write selector type. */
2658	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2659	/** @} */
2660
2661
2662	/** @name System Selector Types.
2663	* @{ */
2664	/** The TSS busy bit mask. */
2665	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2666
2667	/** Undefined system selector type. */
2668	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2669	/** 286 TSS selector. */
2670	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2671	/** LDT selector. */
2672	#define X86_SEL_TYPE_SYS_LDT 2
2673	/** 286 TSS selector - Busy. */
2674	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2675	/** 286 Callgate selector. */
2676	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2677	/** Taskgate selector. */
2678	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2679	/** 286 Interrupt gate selector. */
2680	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2681	/** 286 Trapgate selector. */
2682	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2683	/** Undefined system selector. */
2684	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2685	/** 386 TSS selector. */
2686	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2687	/** Undefined system selector. */
2688	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2689	/** 386 TSS selector - Busy. */
2690	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2691	/** 386 Callgate selector. */
2692	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2693	/** Undefined system selector. */
2694	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2695	/** 386 Interruptgate selector. */
2696	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2697	/** 386 Trapgate selector. */
2698	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2699	/** @} */
2700
2701	/** @name AMD64 System Selector Types.
2702	* @{ */
2703	/** LDT selector. */
2704	#define AMD64_SEL_TYPE_SYS_LDT 2
2705	/** TSS selector - Busy. */
2706	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2707	/** TSS selector - Busy. */
2708	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2709	/** Callgate selector. */
2710	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2711	/** Interruptgate selector. */
2712	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2713	/** Trapgate selector. */
2714	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2715	/** @} */
2716
2717	/** @} */
2718
2719
2720	/** @name Descriptor Table Entry Flag Masks.
2721	* These are for the 2nd 32-bit word of a descriptor.
2722	* @{ */
2723	/** Bits 8-11 - TYPE - Descriptor type mask. */
2724	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2725	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2726	#define X86_DESC_S RT_BIT(12)
2727	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2728	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2729	/** Bit 15 - P - Present. */
2730	#define X86_DESC_P RT_BIT(15)
2731	/** Bit 20 - AVL - Available for system software. */
2732	#define X86_DESC_AVL RT_BIT(20)
2733	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2734	#define X86_DESC_DB RT_BIT(22)
2735	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2736	* used, if clear byte. */
2737	#define X86_DESC_G RT_BIT(23)
2738	/** @} */
2739
2740	/** @} */
2741
2742
2743	/** @name Task Segments.
2744	* @{
2745	*/
2746
2747	/**
2748	* 16-bit Task Segment (TSS).
2749	*/
2750	#pragma pack(1)
2751	typedef struct X86TSS16
2752	{
2753	/** Back link to previous task. (static) */
2754	RTSEL selPrev;
2755	/** Ring-0 stack pointer. (static) */
2756	uint16_t sp0;
2757	/** Ring-0 stack segment. (static) */
2758	RTSEL ss0;
2759	/** Ring-1 stack pointer. (static) */
2760	uint16_t sp1;
2761	/** Ring-1 stack segment. (static) */
2762	RTSEL ss1;
2763	/** Ring-2 stack pointer. (static) */
2764	uint16_t sp2;
2765	/** Ring-2 stack segment. (static) */
2766	RTSEL ss2;
2767	/** IP before task switch. */
2768	uint16_t ip;
2769	/** FLAGS before task switch. */
2770	uint16_t flags;
2771	/** AX before task switch. */
2772	uint16_t ax;
2773	/** CX before task switch. */
2774	uint16_t cx;
2775	/** DX before task switch. */
2776	uint16_t dx;
2777	/** BX before task switch. */
2778	uint16_t bx;
2779	/** SP before task switch. */
2780	uint16_t sp;
2781	/** BP before task switch. */
2782	uint16_t bp;
2783	/** SI before task switch. */
2784	uint16_t si;
2785	/** DI before task switch. */
2786	uint16_t di;
2787	/** ES before task switch. */
2788	RTSEL es;
2789	/** CS before task switch. */
2790	RTSEL cs;
2791	/** SS before task switch. */
2792	RTSEL ss;
2793	/** DS before task switch. */
2794	RTSEL ds;
2795	/** LDTR before task switch. */
2796	RTSEL selLdt;
2797	} X86TSS16;
2798	#ifndef VBOX_FOR_DTRACE_LIB
2799	AssertCompileSize(X86TSS16, 44);
2800	#endif
2801	#pragma pack()
2802	/** Pointer to a 16-bit task segment. */
2803	typedef X86TSS16 *PX86TSS16;
2804	/** Pointer to a const 16-bit task segment. */
2805	typedef const X86TSS16 *PCX86TSS16;
2806
2807
2808	/**
2809	* 32-bit Task Segment (TSS).
2810	*/
2811	#pragma pack(1)
2812	typedef struct X86TSS32
2813	{
2814	/** Back link to previous task. (static) */
2815	RTSEL selPrev;
2816	uint16_t padding1;
2817	/** Ring-0 stack pointer. (static) */
2818	uint32_t esp0;
2819	/** Ring-0 stack segment. (static) */
2820	RTSEL ss0;
2821	uint16_t padding_ss0;
2822	/** Ring-1 stack pointer. (static) */
2823	uint32_t esp1;
2824	/** Ring-1 stack segment. (static) */
2825	RTSEL ss1;
2826	uint16_t padding_ss1;
2827	/** Ring-2 stack pointer. (static) */
2828	uint32_t esp2;
2829	/** Ring-2 stack segment. (static) */
2830	RTSEL ss2;
2831	uint16_t padding_ss2;
2832	/** Page directory for the task. (static) */
2833	uint32_t cr3;
2834	/** EIP before task switch. */
2835	uint32_t eip;
2836	/** EFLAGS before task switch. */
2837	uint32_t eflags;
2838	/** EAX before task switch. */
2839	uint32_t eax;
2840	/** ECX before task switch. */
2841	uint32_t ecx;
2842	/** EDX before task switch. */
2843	uint32_t edx;
2844	/** EBX before task switch. */
2845	uint32_t ebx;
2846	/** ESP before task switch. */
2847	uint32_t esp;
2848	/** EBP before task switch. */
2849	uint32_t ebp;
2850	/** ESI before task switch. */
2851	uint32_t esi;
2852	/** EDI before task switch. */
2853	uint32_t edi;
2854	/** ES before task switch. */
2855	RTSEL es;
2856	uint16_t padding_es;
2857	/** CS before task switch. */
2858	RTSEL cs;
2859	uint16_t padding_cs;
2860	/** SS before task switch. */
2861	RTSEL ss;
2862	uint16_t padding_ss;
2863	/** DS before task switch. */
2864	RTSEL ds;
2865	uint16_t padding_ds;
2866	/** FS before task switch. */
2867	RTSEL fs;
2868	uint16_t padding_fs;
2869	/** GS before task switch. */
2870	RTSEL gs;
2871	uint16_t padding_gs;
2872	/** LDTR before task switch. */
2873	RTSEL selLdt;
2874	uint16_t padding_ldt;
2875	/** Debug trap flag */
2876	uint16_t fDebugTrap;
2877	/** Offset relative to the TSS of the start of the I/O Bitmap
2878	* and the end of the interrupt redirection bitmap. */
2879	uint16_t offIoBitmap;
2880	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2881	uint8_t IntRedirBitmap[32];
2882	} X86TSS32;
2883	#pragma pack()
2884	/** Pointer to task segment. */
2885	typedef X86TSS32 *PX86TSS32;
2886	/** Pointer to const task segment. */
2887	typedef const X86TSS32 *PCX86TSS32;
2888
2889
2890	/**
2891	* 64-bit Task segment.
2892	*/
2893	#pragma pack(1)
2894	typedef struct X86TSS64
2895	{
2896	/** Reserved. */
2897	uint32_t u32Reserved;
2898	/** Ring-0 stack pointer. (static) */
2899	uint64_t rsp0;
2900	/** Ring-1 stack pointer. (static) */
2901	uint64_t rsp1;
2902	/** Ring-2 stack pointer. (static) */
2903	uint64_t rsp2;
2904	/** Reserved. */
2905	uint32_t u32Reserved2[2];
2906	/* IST */
2907	uint64_t ist1;
2908	uint64_t ist2;
2909	uint64_t ist3;
2910	uint64_t ist4;
2911	uint64_t ist5;
2912	uint64_t ist6;
2913	uint64_t ist7;
2914	/* Reserved. */
2915	uint16_t u16Reserved[5];
2916	/** Offset relative to the TSS of the start of the I/O Bitmap
2917	* and the end of the interrupt redirection bitmap. */
2918	uint16_t offIoBitmap;
2919	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2920	uint8_t IntRedirBitmap[32];
2921	} X86TSS64;
2922	#pragma pack()
2923	/** Pointer to a 64-bit task segment. */
2924	typedef X86TSS64 *PX86TSS64;
2925	/** Pointer to a const 64-bit task segment. */
2926	typedef const X86TSS64 *PCX86TSS64;
2927	#ifndef VBOX_FOR_DTRACE_LIB
2928	AssertCompileSize(X86TSS64, 136);
2929	#endif
2930
2931	/** @} */
2932
2933
2934	/** @name Selectors.
2935	* @{
2936	*/
2937
2938	/**
2939	* The shift used to convert a selector from and to index an index (C).
2940	*/
2941	#define X86_SEL_SHIFT 3
2942
2943	/**
2944	* The mask used to mask off the table indicator and CPL of an selector.
2945	*/
2946	#define X86_SEL_MASK 0xfff8U
2947
2948	/**
2949	* The bit indicating that a selector is in the LDT and not in the GDT.
2950	*/
2951	#define X86_SEL_LDT 0x0004U
2952	/**
2953	* The bit mask for getting the RPL of a selector.
2954	*/
2955	#define X86_SEL_RPL 0x0003U
2956
2957	/** @} */
2958
2959
2960	/**
2961	* x86 Exceptions/Faults/Traps.
2962	*/
2963	typedef enum X86XCPT
2964	{
2965	/** \#DE - Divide error. */
2966	X86_XCPT_DE = 0x00,
2967	/** \#DB - Debug event (single step, DRx, ..) */
2968	X86_XCPT_DB = 0x01,
2969	/** NMI - Non-Maskable Interrupt */
2970	X86_XCPT_NMI = 0x02,
2971	/** \#BP - Breakpoint (INT3). */
2972	X86_XCPT_BP = 0x03,
2973	/** \#OF - Overflow (INTO). */
2974	X86_XCPT_OF = 0x04,
2975	/** \#BR - Bound range exceeded (BOUND). */
2976	X86_XCPT_BR = 0x05,
2977	/** \#UD - Undefined opcode. */
2978	X86_XCPT_UD = 0x06,
2979	/** \#NM - Device not available (math coprocessor device). */
2980	X86_XCPT_NM = 0x07,
2981	/** \#DF - Double fault. */
2982	X86_XCPT_DF = 0x08,
2983	/** ??? - Coprocessor segment overrun (obsolete). */
2984	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2985	/** \#TS - Taskswitch (TSS). */
2986	X86_XCPT_TS = 0x0a,
2987	/** \#NP - Segment no present. */
2988	X86_XCPT_NP = 0x0b,
2989	/** \#SS - Stack segment fault. */
2990	X86_XCPT_SS = 0x0c,
2991	/** \#GP - General protection fault. */
2992	X86_XCPT_GP = 0x0d,
2993	/** \#PF - Page fault. */
2994	X86_XCPT_PF = 0x0e,
2995	/* 0x0f is reserved. */
2996	/** \#MF - Math fault (FPU). */
2997	X86_XCPT_MF = 0x10,
2998	/** \#AC - Alignment check. */
2999	X86_XCPT_AC = 0x11,
3000	/** \#MC - Machine check. */
3001	X86_XCPT_MC = 0x12,
3002	/** \#XF - SIMD Floating-Pointer Exception. */
3003	X86_XCPT_XF = 0x13
3004	} X86XCPT;
3005	/** Pointer to a x86 exception code. */
3006	typedef X86XCPT *PX86XCPT;
3007	/** Pointer to a const x86 exception code. */
3008	typedef const X86XCPT *PCX86XCPT;
3009
3010
3011	/** @name Trap Error Codes
3012	* @{
3013	*/
3014	/** External indicator. */
3015	#define X86_TRAP_ERR_EXTERNAL 1
3016	/** IDT indicator. */
3017	#define X86_TRAP_ERR_IDT 2
3018	/** Descriptor table indicator - If set LDT, if clear GDT. */
3019	#define X86_TRAP_ERR_TI 4
3020	/** Mask for getting the selector. */
3021	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3022	/** Shift for getting the selector table index (C type index). */
3023	#define X86_TRAP_ERR_SEL_SHIFT 3
3024	/** @} */
3025
3026
3027	/** @name \#PF Trap Error Codes
3028	* @{
3029	*/
3030	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3031	#define X86_TRAP_PF_P RT_BIT(0)
3032	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3033	#define X86_TRAP_PF_RW RT_BIT(1)
3034	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3035	#define X86_TRAP_PF_US RT_BIT(2)
3036	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3037	#define X86_TRAP_PF_RSVD RT_BIT(3)
3038	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3039	#define X86_TRAP_PF_ID RT_BIT(4)
3040	/** @} */
3041
3042	#pragma pack(1)
3043	/**
3044	* 32-bit IDTR/GDTR.
3045	*/
3046	typedef struct X86XDTR32
3047	{
3048	/** Size of the descriptor table. */
3049	uint16_t cb;
3050	/** Address of the descriptor table. */
3051	#ifndef VBOX_FOR_DTRACE_LIB
3052	uint32_t uAddr;
3053	#else
3054	uint16_t au16Addr[2];
3055	#endif
3056	} X86XDTR32, *PX86XDTR32;
3057	#pragma pack()
3058
3059	#pragma pack(1)
3060	/**
3061	* 64-bit IDTR/GDTR.
3062	*/
3063	typedef struct X86XDTR64
3064	{
3065	/** Size of the descriptor table. */
3066	uint16_t cb;
3067	/** Address of the descriptor table. */
3068	#ifndef VBOX_FOR_DTRACE_LIB
3069	uint64_t uAddr;
3070	#else
3071	uint16_t au16Addr[4];
3072	#endif
3073	} X86XDTR64, *PX86XDTR64;
3074	#pragma pack()
3075
3076
3077	/** @name ModR/M
3078	* @{ */
3079	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3080	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3081	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3082	#define X86_MODRM_REG_SHIFT 3
3083	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3084	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3085	#define X86_MODRM_MOD_SHIFT 6
3086	#ifndef VBOX_FOR_DTRACE_LIB
3087	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3088	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3089	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3090	#endif
3091	/** @} */
3092
3093	/** @name SIB
3094	* @{ */
3095	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3096	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3097	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3098	#define X86_SIB_INDEX_SHIFT 3
3099	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3100	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3101	#define X86_SIB_SCALE_SHIFT 6
3102	#ifndef VBOX_FOR_DTRACE_LIB
3103	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3104	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3105	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3106	#endif
3107	/** @} */
3108
3109	/** @name General register indexes
3110	* @{ */
3111	#define X86_GREG_xAX 0
3112	#define X86_GREG_xCX 1
3113	#define X86_GREG_xDX 2
3114	#define X86_GREG_xBX 3
3115	#define X86_GREG_xSP 4
3116	#define X86_GREG_xBP 5
3117	#define X86_GREG_xSI 6
3118	#define X86_GREG_xDI 7
3119	#define X86_GREG_x8 8
3120	#define X86_GREG_x9 9
3121	#define X86_GREG_x10 10
3122	#define X86_GREG_x11 11
3123	#define X86_GREG_x12 12
3124	#define X86_GREG_x13 13
3125	#define X86_GREG_x14 14
3126	#define X86_GREG_x15 15
3127	/** @} */
3128
3129	/** @name X86_SREG_XXX - Segment register indexes.
3130	* @{ */
3131	#define X86_SREG_ES 0
3132	#define X86_SREG_CS 1
3133	#define X86_SREG_SS 2
3134	#define X86_SREG_DS 3
3135	#define X86_SREG_FS 4
3136	#define X86_SREG_GS 5
3137	/** @} */
3138
3139
3140	/** @} */
3141
3142	#endif
3143

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source: vbox/trunk/include/iprt/x86.h@ 42024

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