x86.h@ 100908

最後變更在這個檔案從100908是 100837,由 vboxsync 提交於 20 月前
include/iprt/x86.h: A small Solaris-specific build warning remediation. Undefine MSR_AMD_VIRT_SPEC_CTL to avoid warnings about '"MSR_AMD_VIRT_SPEC_CTL" redefined' when compiling SUPLib.cpp and SUPLibLdr.cpp. Both of these files include <iprt/alloca.h> which includes <stdlib.h> which pulls in numerous other header files before penultimately including <sys/privregs.h> which ultimately pulls in <sys/controlregs.h> which has its own definition of MSR_AMD_VIRT_SPEC_CTL as of S11.4 SRU60/st_147.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 186.7 KB

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.alldomusa.eu.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# include <iprt/types.h>
46	# include <iprt/assert.h>
47	#else
48	# pragma D depends_on library vbox-types.d
49	#endif
50
51	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
53	#ifdef RT_OS_SOLARIS
54	# undef CS
55	# undef DS
56	# undef MSR_IA32_FLUSH_CMD
57	# undef MSR_AMD_VIRT_SPEC_CTL
58	#endif
59
60	/** @defgroup grp_rt_x86 x86 Types and Definitions
61	* @ingroup grp_rt
62	* @{
63	*/
64
65	#ifndef VBOX_FOR_DTRACE_LIB
66	/**
67	* EFLAGS Bits.
68	*/
69	typedef struct X86EFLAGSBITS
70	{
71	/** Bit 0 - CF - Carry flag - Status flag. */
72	unsigned u1CF : 1;
73	/** Bit 1 - 1 - Reserved flag. */
74	unsigned u1Reserved0 : 1;
75	/** Bit 2 - PF - Parity flag - Status flag. */
76	unsigned u1PF : 1;
77	/** Bit 3 - 0 - Reserved flag. */
78	unsigned u1Reserved1 : 1;
79	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
80	unsigned u1AF : 1;
81	/** Bit 5 - 0 - Reserved flag. */
82	unsigned u1Reserved2 : 1;
83	/** Bit 6 - ZF - Zero flag - Status flag. */
84	unsigned u1ZF : 1;
85	/** Bit 7 - SF - Signed flag - Status flag. */
86	unsigned u1SF : 1;
87	/** Bit 8 - TF - Trap flag - System flag. */
88	unsigned u1TF : 1;
89	/** Bit 9 - IF - Interrupt flag - System flag. */
90	unsigned u1IF : 1;
91	/** Bit 10 - DF - Direction flag - Control flag. */
92	unsigned u1DF : 1;
93	/** Bit 11 - OF - Overflow flag - Status flag. */
94	unsigned u1OF : 1;
95	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
96	unsigned u2IOPL : 2;
97	/** Bit 14 - NT - Nested task flag - System flag. */
98	unsigned u1NT : 1;
99	/** Bit 15 - 0 - Reserved flag. */
100	unsigned u1Reserved3 : 1;
101	/** Bit 16 - RF - Resume flag - System flag. */
102	unsigned u1RF : 1;
103	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
104	unsigned u1VM : 1;
105	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
106	unsigned u1AC : 1;
107	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
108	unsigned u1VIF : 1;
109	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
110	unsigned u1VIP : 1;
111	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
112	unsigned u1ID : 1;
113	/** Bit 22-31 - 0 - Reserved flag. */
114	unsigned u10Reserved4 : 10;
115	} X86EFLAGSBITS;
116	/** Pointer to EFLAGS bits. */
117	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
118	/** Pointer to const EFLAGS bits. */
119	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
120	#endif /* !VBOX_FOR_DTRACE_LIB */
121
122	/**
123	* EFLAGS.
124	*/
125	typedef union X86EFLAGS
126	{
127	/** The plain unsigned view. */
128	uint32_t u;
129	#ifndef VBOX_FOR_DTRACE_LIB
130	/** The bitfield view. */
131	X86EFLAGSBITS Bits;
132	#endif
133	/** The 8-bit view. */
134	uint8_t au8[4];
135	/** The 16-bit view. */
136	uint16_t au16[2];
137	/** The 32-bit view. */
138	uint32_t au32[1];
139	/** The 32-bit view. */
140	uint32_t u32;
141	} X86EFLAGS;
142	/** Pointer to EFLAGS. */
143	typedef X86EFLAGS *PX86EFLAGS;
144	/** Pointer to const EFLAGS. */
145	typedef const X86EFLAGS *PCX86EFLAGS;
146
147	/**
148	* RFLAGS (32 upper bits are reserved).
149	*/
150	typedef union X86RFLAGS
151	{
152	/** The plain unsigned view. */
153	uint64_t u;
154	#ifndef VBOX_FOR_DTRACE_LIB
155	/** The bitfield view. */
156	X86EFLAGSBITS Bits;
157	#endif
158	/** The 8-bit view. */
159	uint8_t au8[8];
160	/** The 16-bit view. */
161	uint16_t au16[4];
162	/** The 32-bit view. */
163	uint32_t au32[2];
164	/** The 64-bit view. */
165	uint64_t au64[1];
166	/** The 64-bit view. */
167	uint64_t u64;
168	} X86RFLAGS;
169	/** Pointer to RFLAGS. */
170	typedef X86RFLAGS *PX86RFLAGS;
171	/** Pointer to const RFLAGS. */
172	typedef const X86RFLAGS *PCX86RFLAGS;
173
174
175	/** @name EFLAGS
176	* @{
177	*/
178	/** Bit 0 - CF - Carry flag - Status flag. */
179	#define X86_EFL_CF RT_BIT_32(0)
180	#define X86_EFL_CF_BIT 0
181	/** Bit 1 - Reserved, reads as 1. */
182	#define X86_EFL_1 RT_BIT_32(1)
183	/** Bit 2 - PF - Parity flag - Status flag. */
184	#define X86_EFL_PF RT_BIT_32(2)
185	#define X86_EFL_PF_BIT 2
186	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
187	#define X86_EFL_AF RT_BIT_32(4)
188	#define X86_EFL_AF_BIT 4
189	/** Bit 6 - ZF - Zero flag - Status flag. */
190	#define X86_EFL_ZF RT_BIT_32(6)
191	#define X86_EFL_ZF_BIT 6
192	/** Bit 7 - SF - Signed flag - Status flag. */
193	#define X86_EFL_SF RT_BIT_32(7)
194	#define X86_EFL_SF_BIT 7
195	/** Bit 8 - TF - Trap flag - System flag. */
196	#define X86_EFL_TF RT_BIT_32(8)
197	#define X86_EFL_TF_BIT 8
198	/** Bit 9 - IF - Interrupt flag - System flag. */
199	#define X86_EFL_IF RT_BIT_32(9)
200	#define X86_EFL_IF_BIT 9
201	/** Bit 10 - DF - Direction flag - Control flag. */
202	#define X86_EFL_DF RT_BIT_32(10)
203	#define X86_EFL_DF_BIT 10
204	/** Bit 11 - OF - Overflow flag - Status flag. */
205	#define X86_EFL_OF RT_BIT_32(11)
206	#define X86_EFL_OF_BIT 11
207	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
208	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
209	/** Bit 14 - NT - Nested task flag - System flag. */
210	#define X86_EFL_NT RT_BIT_32(14)
211	#define X86_EFL_NT_BIT 14
212	/** Bit 16 - RF - Resume flag - System flag. */
213	#define X86_EFL_RF RT_BIT_32(16)
214	#define X86_EFL_RF_BIT 16
215	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
216	#define X86_EFL_VM RT_BIT_32(17)
217	#define X86_EFL_VM_BIT 17
218	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
219	#define X86_EFL_AC RT_BIT_32(18)
220	#define X86_EFL_AC_BIT 18
221	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
222	#define X86_EFL_VIF RT_BIT_32(19)
223	#define X86_EFL_VIF_BIT 19
224	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
225	#define X86_EFL_VIP RT_BIT_32(20)
226	#define X86_EFL_VIP_BIT 20
227	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
228	#define X86_EFL_ID RT_BIT_32(21)
229	#define X86_EFL_ID_BIT 21
230	/** All live bits. */
231	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
232	/** Read as 1 bits. */
233	#define X86_EFL_RA1_MASK RT_BIT_32(1)
234	/** Read as 0 bits, excluding bits 31:22.
235	* Bits 3, 5, 15, and 22 thru 31. */
236	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
237	/** Read as 0 bits, excluding bits 31:22.
238	* Bits 3, 5 and 15. */
239	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
240	/** IOPL shift. */
241	#define X86_EFL_IOPL_SHIFT 12
242	/** The IOPL level from the flags. */
243	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
244	/** Bits restored by popf */
245	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
246	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
247	/** Bits restored by popf */
248	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
249	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
250	/** The status bits commonly updated by arithmetic instructions. */
251	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
252	/** @} */
253
254
255	/** CPUID Feature information - ECX.
256	* CPUID query with EAX=1.
257	*/
258	#ifndef VBOX_FOR_DTRACE_LIB
259	typedef struct X86CPUIDFEATECX
260	{
261	/** Bit 0 - SSE3 - Supports SSE3 or not. */
262	unsigned u1SSE3 : 1;
263	/** Bit 1 - PCLMULQDQ. */
264	unsigned u1PCLMULQDQ : 1;
265	/** Bit 2 - DS Area 64-bit layout. */
266	unsigned u1DTE64 : 1;
267	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
268	unsigned u1Monitor : 1;
269	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
270	unsigned u1CPLDS : 1;
271	/** Bit 5 - VMX - Virtual Machine Technology. */
272	unsigned u1VMX : 1;
273	/** Bit 6 - SMX: Safer Mode Extensions. */
274	unsigned u1SMX : 1;
275	/** Bit 7 - EST - Enh. SpeedStep Tech. */
276	unsigned u1EST : 1;
277	/** Bit 8 - TM2 - Terminal Monitor 2. */
278	unsigned u1TM2 : 1;
279	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
280	unsigned u1SSSE3 : 1;
281	/** Bit 10 - CNTX-ID - L1 Context ID. */
282	unsigned u1CNTXID : 1;
283	/** Bit 11 - Reserved. */
284	unsigned u1Reserved1 : 1;
285	/** Bit 12 - FMA. */
286	unsigned u1FMA : 1;
287	/** Bit 13 - CX16 - CMPXCHG16B. */
288	unsigned u1CX16 : 1;
289	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
290	unsigned u1TPRUpdate : 1;
291	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
292	unsigned u1PDCM : 1;
293	/** Bit 16 - Reserved. */
294	unsigned u1Reserved2 : 1;
295	/** Bit 17 - PCID - Process-context identifiers. */
296	unsigned u1PCID : 1;
297	/** Bit 18 - Direct Cache Access. */
298	unsigned u1DCA : 1;
299	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
300	unsigned u1SSE4_1 : 1;
301	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
302	unsigned u1SSE4_2 : 1;
303	/** Bit 21 - x2APIC. */
304	unsigned u1x2APIC : 1;
305	/** Bit 22 - MOVBE - Supports MOVBE. */
306	unsigned u1MOVBE : 1;
307	/** Bit 23 - POPCNT - Supports POPCNT. */
308	unsigned u1POPCNT : 1;
309	/** Bit 24 - TSC-Deadline. */
310	unsigned u1TSCDEADLINE : 1;
311	/** Bit 25 - AES. */
312	unsigned u1AES : 1;
313	/** Bit 26 - XSAVE - Supports XSAVE. */
314	unsigned u1XSAVE : 1;
315	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
316	unsigned u1OSXSAVE : 1;
317	/** Bit 28 - AVX - Supports AVX instruction extensions. */
318	unsigned u1AVX : 1;
319	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
320	unsigned u1F16C : 1;
321	/** Bit 30 - RDRAND - Supports RDRAND. */
322	unsigned u1RDRAND : 1;
323	/** Bit 31 - Hypervisor present (we're a guest). */
324	unsigned u1HVP : 1;
325	} X86CPUIDFEATECX;
326	#else /* VBOX_FOR_DTRACE_LIB */
327	typedef uint32_t X86CPUIDFEATECX;
328	#endif /* VBOX_FOR_DTRACE_LIB */
329	/** Pointer to CPUID Feature Information - ECX. */
330	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
331	/** Pointer to const CPUID Feature Information - ECX. */
332	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
333
334
335	/** CPUID Feature Information - EDX.
336	* CPUID query with EAX=1.
337	*/
338	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
339	typedef struct X86CPUIDFEATEDX
340	{
341	/** Bit 0 - FPU - x87 FPU on Chip. */
342	unsigned u1FPU : 1;
343	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
344	unsigned u1VME : 1;
345	/** Bit 2 - DE - Debugging extensions. */
346	unsigned u1DE : 1;
347	/** Bit 3 - PSE - Page Size Extension. */
348	unsigned u1PSE : 1;
349	/** Bit 4 - TSC - Time Stamp Counter. */
350	unsigned u1TSC : 1;
351	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
352	unsigned u1MSR : 1;
353	/** Bit 6 - PAE - Physical Address Extension. */
354	unsigned u1PAE : 1;
355	/** Bit 7 - MCE - Machine Check Exception. */
356	unsigned u1MCE : 1;
357	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
358	unsigned u1CX8 : 1;
359	/** Bit 9 - APIC - APIC On-Chip. */
360	unsigned u1APIC : 1;
361	/** Bit 10 - Reserved. */
362	unsigned u1Reserved1 : 1;
363	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
364	unsigned u1SEP : 1;
365	/** Bit 12 - MTRR - Memory Type Range Registers. */
366	unsigned u1MTRR : 1;
367	/** Bit 13 - PGE - PTE Global Bit. */
368	unsigned u1PGE : 1;
369	/** Bit 14 - MCA - Machine Check Architecture. */
370	unsigned u1MCA : 1;
371	/** Bit 15 - CMOV - Conditional Move Instructions. */
372	unsigned u1CMOV : 1;
373	/** Bit 16 - PAT - Page Attribute Table. */
374	unsigned u1PAT : 1;
375	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
376	unsigned u1PSE36 : 1;
377	/** Bit 18 - PSN - Processor Serial Number. */
378	unsigned u1PSN : 1;
379	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
380	unsigned u1CLFSH : 1;
381	/** Bit 20 - Reserved. */
382	unsigned u1Reserved2 : 1;
383	/** Bit 21 - DS - Debug Store. */
384	unsigned u1DS : 1;
385	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
386	unsigned u1ACPI : 1;
387	/** Bit 23 - MMX - Intel MMX 'Technology'. */
388	unsigned u1MMX : 1;
389	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
390	unsigned u1FXSR : 1;
391	/** Bit 25 - SSE - SSE Support. */
392	unsigned u1SSE : 1;
393	/** Bit 26 - SSE2 - SSE2 Support. */
394	unsigned u1SSE2 : 1;
395	/** Bit 27 - SS - Self Snoop. */
396	unsigned u1SS : 1;
397	/** Bit 28 - HTT - Hyper-Threading Technology. */
398	unsigned u1HTT : 1;
399	/** Bit 29 - TM - Thermal Monitor. */
400	unsigned u1TM : 1;
401	/** Bit 30 - Reserved - . */
402	unsigned u1Reserved3 : 1;
403	/** Bit 31 - PBE - Pending Break Enabled. */
404	unsigned u1PBE : 1;
405	} X86CPUIDFEATEDX;
406	#else /* VBOX_FOR_DTRACE_LIB */
407	typedef uint32_t X86CPUIDFEATEDX;
408	#endif /* VBOX_FOR_DTRACE_LIB */
409	/** Pointer to CPUID Feature Information - EDX. */
410	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
411	/** Pointer to const CPUID Feature Information - EDX. */
412	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
413
414	/** @name CPUID Vendor information.
415	* CPUID query with EAX=0.
416	* @{
417	*/
418	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
419	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
420	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
421
422	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
423	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
424	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
425
426	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
427	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
428	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
429
430	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
431	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
432	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
433
434	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
435	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
436	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
437	/** @} */
438
439
440	/** @name CPUID Feature information.
441	* CPUID query with EAX=1.
442	* @{
443	*/
444	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
445	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
446	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
447	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
448	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
449	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
450	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
451	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
452	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
453	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
454	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
455	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
456	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
457	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
458	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
459	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
460	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
461	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
462	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
463	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
464	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
465	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
466	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
467	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
468	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
469	/** ECX Bit 12 - FMA. */
470	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
471	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
472	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
473	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
474	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
475	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
476	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
477	/** ECX Bit 17 - PCID - Process-context identifiers. */
478	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
479	/** ECX Bit 18 - DCA - Direct Cache Access. */
480	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
481	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
482	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
483	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
484	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
485	/** ECX Bit 21 - x2APIC support. */
486	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
487	/** ECX Bit 22 - MOVBE instruction. */
488	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
489	/** ECX Bit 23 - POPCNT instruction. */
490	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
491	/** ECX Bir 24 - TSC-Deadline. */
492	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
493	/** ECX Bit 25 - AES instructions. */
494	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
495	/** ECX Bit 26 - XSAVE instruction. */
496	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
497	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
498	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
499	/** ECX Bit 28 - AVX. */
500	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
501	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
502	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
503	/** ECX Bit 30 - RDRAND instruction. */
504	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
505	/** ECX Bit 31 - Hypervisor Present (software only). */
506	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
507
508
509	/** Bit 0 - FPU - x87 FPU on Chip. */
510	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
511	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
512	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
513	/** Bit 2 - DE - Debugging extensions. */
514	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
515	/** Bit 3 - PSE - Page Size Extension. */
516	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
517	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
518	/** Bit 4 - TSC - Time Stamp Counter. */
519	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
520	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
521	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
522	/** Bit 6 - PAE - Physical Address Extension. */
523	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
524	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
525	/** Bit 7 - MCE - Machine Check Exception. */
526	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
527	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
528	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
529	/** Bit 9 - APIC - APIC On-Chip. */
530	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
531	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
532	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
533	/** Bit 12 - MTRR - Memory Type Range Registers. */
534	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
535	/** Bit 13 - PGE - PTE Global Bit. */
536	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
537	/** Bit 14 - MCA - Machine Check Architecture. */
538	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
539	/** Bit 15 - CMOV - Conditional Move Instructions. */
540	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
541	/** Bit 16 - PAT - Page Attribute Table. */
542	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
543	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
544	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
545	/** Bit 18 - PSN - Processor Serial Number. */
546	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
547	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
548	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
549	/** Bit 21 - DS - Debug Store. */
550	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
551	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
552	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
553	/** Bit 23 - MMX - Intel MMX Technology. */
554	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
555	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
556	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
557	/** Bit 25 - SSE - SSE Support. */
558	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
559	/** Bit 26 - SSE2 - SSE2 Support. */
560	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
561	/** Bit 27 - SS - Self Snoop. */
562	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
563	/** Bit 28 - HTT - Hyper-Threading Technology. */
564	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
565	/** Bit 29 - TM - Therm. Monitor. */
566	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
567	/** Bit 31 - PBE - Pending Break Enabled. */
568	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
569	/** @} */
570
571	/** @name CPUID mwait/monitor information.
572	* CPUID query with EAX=5.
573	* @{
574	*/
575	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
576	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
577	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
578	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
579	/** @} */
580
581
582	/** @name CPUID Structured Extended Feature information.
583	* CPUID query with EAX=7.
584	* @{
585	*/
586	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
588	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
589	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
590	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
591	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
592	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
593	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
594	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
596	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
597	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
598	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
599	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
600	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
601	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
602	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
603	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
604	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
605	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
606	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
607	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
608	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
609	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
610	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
611	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
612	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
613	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
614	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
615	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
616	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
617	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
618	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
619	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
620	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
621	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
622	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
623	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
624	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
625	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
626	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
627	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
628	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
629	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
630	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
631	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
632	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
633	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
634	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
635	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
636	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
637	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
638
639	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
640	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
641	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
642	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
643	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
644	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
645	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
646	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
647	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
648	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
649	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
650	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
651	/** ECX Bit 22 - RDPID - Support pread process ID. */
652	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
653	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
654	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
655
656	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
657	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
658	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
659	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
660	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
661	* IBPB command in IA32_PRED_CMD. */
662	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
663	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
664	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
665	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
666	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
667	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
668	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
669	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
670	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
671
672	/** @} */
673
674
675	/** @name CPUID Extended Feature information.
676	* CPUID query with EAX=0x80000001.
677	* @{
678	*/
679	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
680	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
681
682	/** EDX Bit 11 - SYSCALL/SYSRET. */
683	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
684	/** EDX Bit 20 - No-Execute/Execute-Disable. */
685	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
686	/** EDX Bit 26 - 1 GB large page. */
687	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
688	/** EDX Bit 27 - RDTSCP. */
689	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
690	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
691	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
692	/** @}*/
693
694	/** @name CPUID AMD Feature information.
695	* CPUID query with EAX=0x80000001.
696	* @{
697	*/
698	/** Bit 0 - FPU - x87 FPU on Chip. */
699	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
700	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
701	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
702	/** Bit 2 - DE - Debugging extensions. */
703	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
704	/** Bit 3 - PSE - Page Size Extension. */
705	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
706	/** Bit 4 - TSC - Time Stamp Counter. */
707	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
708	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
709	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
710	/** Bit 6 - PAE - Physical Address Extension. */
711	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
712	/** Bit 7 - MCE - Machine Check Exception. */
713	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
714	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
715	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
716	/** Bit 9 - APIC - APIC On-Chip. */
717	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
718	/** Bit 12 - MTRR - Memory Type Range Registers. */
719	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
720	/** Bit 13 - PGE - PTE Global Bit. */
721	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
722	/** Bit 14 - MCA - Machine Check Architecture. */
723	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
724	/** Bit 15 - CMOV - Conditional Move Instructions. */
725	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
726	/** Bit 16 - PAT - Page Attribute Table. */
727	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
728	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
729	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
730	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
731	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
732	/** Bit 23 - MMX - Intel MMX Technology. */
733	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
734	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
735	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
736	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
737	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
738	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
739	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
740	/** Bit 31 - 3DNOW - AMD 3DNow. */
741	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
742
743	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
744	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
745	/** Bit 2 - SVM - AMD VM extensions. */
746	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
747	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
748	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
749	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
750	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
751	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
752	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
753	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
754	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
755	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
756	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
757	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
758	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
759	/** Bit 9 - OSVW - AMD OS visible workaround. */
760	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
761	/** Bit 10 - IBS - Instruct based sampling. */
762	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
763	/** Bit 11 - XOP - Extended operation support (see APM6). */
764	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
765	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
766	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
767	/** Bit 13 - WDT - AMD Watchdog timer support. */
768	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
769	/** Bit 15 - LWP - Lightweight profiling support. */
770	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
771	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
772	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
773	/** Bit 19 - NodeId - Indicates support for
774	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
775	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
776	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
777	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
778	/** Bit 22 - TopologyExtensions - . */
779	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
780	/** @} */
781
782
783	/** @name CPUID AMD Feature information.
784	* CPUID query with EAX=0x80000007.
785	* @{
786	*/
787	/** Bit 0 - TS - Temperature Sensor. */
788	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
789	/** Bit 1 - FID - Frequency ID Control. */
790	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
791	/** Bit 2 - VID - Voltage ID Control. */
792	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
793	/** Bit 3 - TTP - THERMTRIP. */
794	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
795	/** Bit 4 - TM - Hardware Thermal Control. */
796	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
797	/** Bit 5 - STC - Software Thermal Control. */
798	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
799	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
800	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
801	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
802	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
803	/** Bit 8 - TSCINVAR - TSC Invariant. */
804	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
805	/** Bit 9 - CPB - TSC Invariant. */
806	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
807	/** Bit 10 - EffFreqRO - MPERF/APERF. */
808	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
809	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
810	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
811	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
812	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
813	/** @} */
814
815
816	/** @name CPUID AMD extended feature extensions ID (EBX).
817	* CPUID query with EAX=0x80000008.
818	* @{
819	*/
820	/** Bit 0 - CLZERO - Clear zero instruction. */
821	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
822	/** Bit 1 - IRPerf - Instructions retired count support. */
823	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
824	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
825	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
826	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
827	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
828	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
829	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
830	/* AMD pipeline length: 9 feature bits ;-) */
831	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
832	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
833	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
834	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
835	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
836	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
837	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
838	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
839	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
840	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
841	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
842	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
843	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
844	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
845	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
846	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
847	/** Bit 26 - Speculative Store Bypass Disable not required. */
848	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
849	/** @} */
850
851
852	/** @name CPUID AMD SVM Feature information.
853	* CPUID query with EAX=0x8000000a.
854	* @{
855	*/
856	/** Bit 0 - NP - Nested Paging supported. */
857	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
858	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
859	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
860	/** Bit 2 - SVML - SVM locking bit supported. */
861	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
862	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
863	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
864	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
865	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
866	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
867	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
868	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
869	* VMCB.TLB_Control is supported. */
870	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
871	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
872	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
873	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
874	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
875	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
876	* intercept filter cycle count threshold. */
877	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
878	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
879	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
880	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
881	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
882	/** Bit 16 - VGIF - Supports virtualized GIF. */
883	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
884	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
885	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
886	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
887	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
888	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
889	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
890	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
891	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
892	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
893	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
894	/** @} */
895
896
897	/** @name CR0
898	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
899	* reserved flags.
900	* @{ */
901	/** Bit 0 - PE - Protection Enabled */
902	#define X86_CR0_PE RT_BIT_32(0)
903	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
904	/** Bit 1 - MP - Monitor Coprocessor */
905	#define X86_CR0_MP RT_BIT_32(1)
906	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
907	/** Bit 2 - EM - Emulation. */
908	#define X86_CR0_EM RT_BIT_32(2)
909	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
910	/** Bit 3 - TS - Task Switch. */
911	#define X86_CR0_TS RT_BIT_32(3)
912	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
913	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
914	#define X86_CR0_ET RT_BIT_32(4)
915	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
916	/** Bit 5 - NE - Numeric error (486+). */
917	#define X86_CR0_NE RT_BIT_32(5)
918	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
919	/** Bit 16 - WP - Write Protect (486+). */
920	#define X86_CR0_WP RT_BIT_32(16)
921	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
922	/** Bit 18 - AM - Alignment Mask (486+). */
923	#define X86_CR0_AM RT_BIT_32(18)
924	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
925	/** Bit 29 - NW - Not Write-though (486+). */
926	#define X86_CR0_NW RT_BIT_32(29)
927	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
928	/** Bit 30 - WP - Cache Disable (486+). */
929	#define X86_CR0_CD RT_BIT_32(30)
930	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
931	/** Bit 31 - PG - Paging. */
932	#define X86_CR0_PG RT_BIT_32(31)
933	#define X86_CR0_PAGING RT_BIT_32(31)
934	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
935	/** @} */
936
937
938	/** @name CR3
939	* @{ */
940	/** Bit 3 - PWT - Page-level Writes Transparent. */
941	#define X86_CR3_PWT RT_BIT_32(3)
942	/** Bit 4 - PCD - Page-level Cache Disable. */
943	#define X86_CR3_PCD RT_BIT_32(4)
944	/** Bits 12-31 - - Page directory page number. */
945	#define X86_CR3_PAGE_MASK (0xfffff000)
946	/** Bits 5-31 - - PAE Page directory page number. */
947	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
948	/** Bits 12-51 - - AMD64 PML4 page number.
949	* @note This is a maxed out mask, the actual acceptable CR3 value can
950	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
951	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
952	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
953	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
954	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
955	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
956	/** @} */
957
958
959	/** @name CR4
960	* @{ */
961	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
962	#define X86_CR4_VME RT_BIT_32(0)
963	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
964	#define X86_CR4_PVI RT_BIT_32(1)
965	/** Bit 2 - TSD - Time Stamp Disable. */
966	#define X86_CR4_TSD RT_BIT_32(2)
967	/** Bit 3 - DE - Debugging Extensions. */
968	#define X86_CR4_DE RT_BIT_32(3)
969	/** Bit 4 - PSE - Page Size Extension. */
970	#define X86_CR4_PSE RT_BIT_32(4)
971	/** Bit 5 - PAE - Physical Address Extension. */
972	#define X86_CR4_PAE RT_BIT_32(5)
973	/** Bit 6 - MCE - Machine-Check Enable. */
974	#define X86_CR4_MCE RT_BIT_32(6)
975	/** Bit 7 - PGE - Page Global Enable. */
976	#define X86_CR4_PGE RT_BIT_32(7)
977	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
978	#define X86_CR4_PCE RT_BIT_32(8)
979	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
980	#define X86_CR4_OSFXSR RT_BIT_32(9)
981	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
982	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
983	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
984	#define X86_CR4_UMIP RT_BIT_32(11)
985	/** Bit 13 - VMXE - VMX mode is enabled. */
986	#define X86_CR4_VMXE RT_BIT_32(13)
987	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
988	#define X86_CR4_SMXE RT_BIT_32(14)
989	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
990	#define X86_CR4_FSGSBASE RT_BIT_32(16)
991	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
992	#define X86_CR4_PCIDE RT_BIT_32(17)
993	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
994	* extended states. */
995	#define X86_CR4_OSXSAVE RT_BIT_32(18)
996	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
997	#define X86_CR4_SMEP RT_BIT_32(20)
998	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
999	#define X86_CR4_SMAP RT_BIT_32(21)
1000	/** Bit 22 - PKE - Protection Key Enable. */
1001	#define X86_CR4_PKE RT_BIT_32(22)
1002	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1003	#define X86_CR4_CET RT_BIT_32(23)
1004	/** @} */
1005
1006
1007	/** @name DR6
1008	* @{ */
1009	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1010	#define X86_DR6_B0 RT_BIT_32(0)
1011	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1012	#define X86_DR6_B1 RT_BIT_32(1)
1013	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1014	#define X86_DR6_B2 RT_BIT_32(2)
1015	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1016	#define X86_DR6_B3 RT_BIT_32(3)
1017	/** Mask of all the Bx bits. */
1018	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1019	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1020	#define X86_DR6_BD RT_BIT_32(13)
1021	/** Bit 14 - BS - Single step */
1022	#define X86_DR6_BS RT_BIT_32(14)
1023	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1024	#define X86_DR6_BT RT_BIT_32(15)
1025	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1026	#define X86_DR6_RTM RT_BIT_32(16)
1027	/** Value of DR6 after powerup/reset. */
1028	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1029	/** Bits which must be 1s in DR6. */
1030	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1031	/** Bits which must be 1s in DR6, when RTM is supported. */
1032	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1033	/** Bits which must be 0s in DR6. */
1034	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1035	/** Bits which must be 0s on writes to DR6. */
1036	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1037	/** @} */
1038
1039	/** Get the DR6.Bx bit for a the given breakpoint. */
1040	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1041
1042
1043	/** @name DR7
1044	* @{ */
1045	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1046	#define X86_DR7_L0 RT_BIT_32(0)
1047	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1048	#define X86_DR7_G0 RT_BIT_32(1)
1049	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1050	#define X86_DR7_L1 RT_BIT_32(2)
1051	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1052	#define X86_DR7_G1 RT_BIT_32(3)
1053	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1054	#define X86_DR7_L2 RT_BIT_32(4)
1055	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1056	#define X86_DR7_G2 RT_BIT_32(5)
1057	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1058	#define X86_DR7_L3 RT_BIT_32(6)
1059	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1060	#define X86_DR7_G3 RT_BIT_32(7)
1061	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1062	#define X86_DR7_LE RT_BIT_32(8)
1063	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1064	#define X86_DR7_GE RT_BIT_32(9)
1065
1066	/** L0, L1, L2, and L3. */
1067	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1068	/** L0, L1, L2, and L3. */
1069	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1070
1071	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1072	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1073	#define X86_DR7_RTM RT_BIT_32(11)
1074	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1075	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1076	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1077	* instruction is executed.
1078	* @see http://www.rcollins.org/secrets/DR7.html */
1079	#define X86_DR7_ICE_IR RT_BIT_32(12)
1080	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1081	* any DR register is accessed. */
1082	#define X86_DR7_GD RT_BIT_32(13)
1083	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1084	* Pentium. */
1085	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1086	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1087	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1088	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1089	#define X86_DR7_RW0_MASK (3 << 16)
1090	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1091	#define X86_DR7_LEN0_MASK (3 << 18)
1092	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1093	#define X86_DR7_RW1_MASK (3 << 20)
1094	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1095	#define X86_DR7_LEN1_MASK (3 << 22)
1096	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1097	#define X86_DR7_RW2_MASK (3 << 24)
1098	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1099	#define X86_DR7_LEN2_MASK (3 << 26)
1100	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1101	#define X86_DR7_RW3_MASK (3 << 28)
1102	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1103	#define X86_DR7_LEN3_MASK (3 << 30)
1104
1105	/** Bits which reads as 1s. */
1106	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1107	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1108	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1109	/** Bits which must be 0s when writing to DR7. */
1110	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1111
1112	/** Calcs the L bit of Nth breakpoint.
1113	* @param iBp The breakpoint number [0..3].
1114	*/
1115	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1116
1117	/** Calcs the G bit of Nth breakpoint.
1118	* @param iBp The breakpoint number [0..3].
1119	*/
1120	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1121
1122	/** Calcs the L and G bits of Nth breakpoint.
1123	* @param iBp The breakpoint number [0..3].
1124	*/
1125	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1126
1127	/** @name Read/Write values.
1128	* @{ */
1129	/** Break on instruction fetch only. */
1130	#define X86_DR7_RW_EO UINT32_C(0)
1131	/** Break on write only. */
1132	#define X86_DR7_RW_WO UINT32_C(1)
1133	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1134	#define X86_DR7_RW_IO UINT32_C(2)
1135	/** Break on read or write (but not instruction fetches). */
1136	#define X86_DR7_RW_RW UINT32_C(3)
1137	/** @} */
1138
1139	/** Shifts a X86_DR7_RW_* value to its right place.
1140	* @param iBp The breakpoint number [0..3].
1141	* @param fRw One of the X86_DR7_RW_* value.
1142	*/
1143	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1144
1145	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1146	* one of the X86_DR7_RW_XXX constants).
1147	*
1148	* @returns X86_DR7_RW_XXX
1149	* @param uDR7 DR7 value
1150	* @param iBp The breakpoint number [0..3].
1151	*/
1152	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1153
1154	/** R/W0, R/W1, R/W2, and R/W3. */
1155	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1156
1157	#ifndef VBOX_FOR_DTRACE_LIB
1158	/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1159	* @note This does not check if it's enabled. */
1160	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1161	/** Checks if an instruction breakpoint is enabled and configured correctly.
1162	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1163	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1164	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1165	/** Checks if there are any instruction fetch breakpoint types configured in the
1166	* RW and LEN registers.
1167	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1168	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1169	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1170	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1171	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1172	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1173
1174	/** Checks if there are any I/O breakpoint types configured in the RW
1175	* registers. Does NOT check if these are enabled, sorry. */
1176	# define X86_DR7_ANY_RW_IO(uDR7) \
1177	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1178	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1179	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1180	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1181	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1182	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1183	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1184	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1185	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1186	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1187	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1188
1189	#endif /* !VBOX_FOR_DTRACE_LIB */
1190
1191	/** @name Length values.
1192	* @{ */
1193	#define X86_DR7_LEN_BYTE UINT32_C(0)
1194	#define X86_DR7_LEN_WORD UINT32_C(1)
1195	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1196	#define X86_DR7_LEN_DWORD UINT32_C(3)
1197	/** @} */
1198
1199	/** Shifts a X86_DR7_LEN_* value to its right place.
1200	* @param iBp The breakpoint number [0..3].
1201	* @param cb One of the X86_DR7_LEN_* values.
1202	*/
1203	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1204
1205	/** Fetch the breakpoint length bits from the DR7 value.
1206	* @param uDR7 DR7 value
1207	* @param iBp The breakpoint number [0..3].
1208	*/
1209	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1210
1211	/** Mask used to check if any breakpoints are enabled. */
1212	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1213
1214	/** LEN0, LEN1, LEN2, and LEN3. */
1215	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1216	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1217	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1218
1219	/** Value of DR7 after powerup/reset. */
1220	#define X86_DR7_INIT_VAL 0x400
1221	/** @} */
1222
1223
1224	/** @name Machine Specific Registers
1225	* @{
1226	*/
1227	/** Machine check address register (P5). */
1228	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1229	/** Machine check type register (P5). */
1230	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1231	/** Time Stamp Counter. */
1232	#define MSR_IA32_TSC 0x10
1233	#define MSR_IA32_CESR UINT32_C(0x00000011)
1234	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1235	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1236
1237	#define MSR_IA32_PLATFORM_ID 0x17
1238
1239	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1240	# define MSR_IA32_APICBASE 0x1b
1241	/** Local APIC enabled. */
1242	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1243	/** X2APIC enabled (requires the EN bit to be set). */
1244	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1245	/** The processor is the boot strap processor (BSP). */
1246	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1247	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1248	* width. */
1249	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1250	/** The default physical base address of the APIC. */
1251	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1252	/** Gets the physical base address from the MSR. */
1253	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1254	#endif
1255
1256	/** Undocumented intel MSR for reporting thread and core counts.
1257	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1258	* first 16 bits is the thread count. The next 16 bits the core count, except
1259	* on Westmere where it seems it's only the next 4 bits for some reason. */
1260	#define MSR_CORE_THREAD_COUNT 0x35
1261
1262	/** CPU Feature control. */
1263	#define MSR_IA32_FEATURE_CONTROL 0x3A
1264	/** Feature control - Lock MSR from writes (R/W0). */
1265	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1266	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1267	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1268	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1269	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1270	/** Feature control - SENTER local functions enable (R/WL). */
1271	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1272	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1273	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1274	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1275	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1276	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1277	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1278	/** Feature control - SENTER global enable (R/WL). */
1279	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1280	/** Feature control - SGX launch control enable (R/WL). */
1281	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1282	/** Feature control - SGX global enable (R/WL). */
1283	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1284	/** Feature control - LMCE on (R/WL). */
1285	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1286
1287	/** Per-processor TSC adjust MSR. */
1288	#define MSR_IA32_TSC_ADJUST 0x3B
1289
1290	/** Spectre control register.
1291	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1292	#define MSR_IA32_SPEC_CTRL 0x48
1293	/** IBRS - Indirect branch restricted speculation. */
1294	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1295	/** STIBP - Single thread indirect branch predictors. */
1296	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1297	/** SSBD - Speculative Store Bypass Disable. */
1298	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1299
1300	/** Prediction command register.
1301	* Write only, logical processor scope, no state since write only. */
1302	#define MSR_IA32_PRED_CMD 0x49
1303	/** IBPB - Indirect branch prediction barrie when written as 1. */
1304	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1305
1306	/** BIOS update trigger (microcode update). */
1307	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1308
1309	/** BIOS update signature (microcode). */
1310	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1311
1312	/** SMM monitor control. */
1313	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1314	/** SMM control - Valid. */
1315	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1316	/** SMM control - VMXOFF unblocks SMI. */
1317	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1318	/** SMM control - MSEG base physical address. */
1319	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1320
1321	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1322	#define MSR_IA32_SMBASE 0x9E
1323
1324	/** General performance counter no. 0. */
1325	#define MSR_IA32_PMC0 0xC1
1326	/** General performance counter no. 1. */
1327	#define MSR_IA32_PMC1 0xC2
1328	/** General performance counter no. 2. */
1329	#define MSR_IA32_PMC2 0xC3
1330	/** General performance counter no. 3. */
1331	#define MSR_IA32_PMC3 0xC4
1332	/** General performance counter no. 4. */
1333	#define MSR_IA32_PMC4 0xC5
1334	/** General performance counter no. 5. */
1335	#define MSR_IA32_PMC5 0xC6
1336	/** General performance counter no. 6. */
1337	#define MSR_IA32_PMC6 0xC7
1338	/** General performance counter no. 7. */
1339	#define MSR_IA32_PMC7 0xC8
1340
1341	/** Nehalem power control. */
1342	#define MSR_IA32_PLATFORM_INFO 0xCE
1343
1344	/** Get FSB clock status (Intel-specific). */
1345	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1346
1347	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1348	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1349
1350	/** C0 Maximum Frequency Clock Count */
1351	#define MSR_IA32_MPERF 0xE7
1352	/** C0 Actual Frequency Clock Count */
1353	#define MSR_IA32_APERF 0xE8
1354
1355	/** MTRR Capabilities. */
1356	#define MSR_IA32_MTRR_CAP 0xFE
1357
1358	/** Architecture capabilities (bugfixes). */
1359	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1360	/** CPU is no subject to meltdown problems. */
1361	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1362	/** CPU has better IBRS and you can leave it on all the time. */
1363	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1364	/** CPU has return stack buffer (RSB) override. */
1365	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1366	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1367	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1368	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1369	/** CPU does not suffer from MDS issues. */
1370	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1371
1372	/** Flush command register. */
1373	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1374	/** Flush the level 1 data cache when this bit is written. */
1375	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1376
1377	/** Cache control/info. */
1378	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1379
1380	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1381	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1382	* R0 SS == CS + 8
1383	* R3 CS == CS + 16
1384	* R3 SS == CS + 24
1385	*/
1386	#define MSR_IA32_SYSENTER_CS 0x174
1387	/** SYSENTER_ESP - the R0 ESP. */
1388	#define MSR_IA32_SYSENTER_ESP 0x175
1389	/** SYSENTER_EIP - the R0 EIP. */
1390	#define MSR_IA32_SYSENTER_EIP 0x176
1391	#endif
1392
1393	/** Machine Check Global Capabilities Register. */
1394	#define MSR_IA32_MCG_CAP 0x179
1395	/** Machine Check Global Status Register. */
1396	#define MSR_IA32_MCG_STATUS 0x17A
1397	/** Machine Check Global Control Register. */
1398	#define MSR_IA32_MCG_CTRL 0x17B
1399
1400	/** Page Attribute Table. */
1401	#define MSR_IA32_CR_PAT 0x277
1402	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1403	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1404	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1405
1406	/** Performance event select MSRs. (Intel only) */
1407	#define MSR_IA32_PERFEVTSEL0 0x186
1408	#define MSR_IA32_PERFEVTSEL1 0x187
1409	#define MSR_IA32_PERFEVTSEL2 0x188
1410	#define MSR_IA32_PERFEVTSEL3 0x189
1411
1412	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1413	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1414	* holds a ratio that Apple takes for TSC granularity.
1415	*
1416	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1417	#define MSR_FLEX_RATIO 0x194
1418	/** Performance state value and starting with Intel core more.
1419	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1420	#define MSR_IA32_PERF_STATUS 0x198
1421	#define MSR_IA32_PERF_CTL 0x199
1422	#define MSR_IA32_THERM_STATUS 0x19c
1423
1424	/** Offcore response event select registers. */
1425	#define MSR_OFFCORE_RSP_0 0x1a6
1426	#define MSR_OFFCORE_RSP_1 0x1a7
1427
1428	/** Enable misc. processor features (R/W). */
1429	#define MSR_IA32_MISC_ENABLE 0x1A0
1430	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1431	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1432	/** Automatic Thermal Control Circuit Enable (R/W). */
1433	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1434	/** Performance Monitoring Available (R). */
1435	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1436	/** Branch Trace Storage Unavailable (R/O). */
1437	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1438	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1439	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1440	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1441	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1442	/** If MONITOR/MWAIT is supported (R/W). */
1443	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1444	/** Limit CPUID Maxval to 3 leafs (R/W). */
1445	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1446	/** When set to 1, xTPR messages are disabled (R/W). */
1447	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1448	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1449	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1450
1451	/** Trace/Profile Resource Control (R/W) */
1452	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1453	/** Last branch record. */
1454	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1455	/** Branch trace flag (single step on branches). */
1456	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1457	/** Performance monitoring pin control (AMD only). */
1458	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1459	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1460	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1461	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1462	/** Trace message enable (Intel only). */
1463	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1464	/** Branch trace store (Intel only). */
1465	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1466	/** Branch trace interrupt (Intel only). */
1467	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1468	/** Branch trace off in privileged code (Intel only). */
1469	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1470	/** Branch trace off in user code (Intel only). */
1471	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1472	/** Freeze LBR on PMI flag (Intel only). */
1473	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1474	/** Freeze PERFMON on PMI flag (Intel only). */
1475	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1476	/** Freeze while SMM enabled (Intel only). */
1477	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1478	/** Advanced debugging of RTM regions (Intel only). */
1479	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1480	/** Debug control MSR valid bits (Intel only). */
1481	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1482	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1483	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1484	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1485	\| MSR_IA32_DEBUGCTL_RTM)
1486
1487	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1488	* @{ */
1489	#define MSR_P4_LASTBRANCH_0 0x1db
1490	#define MSR_P4_LASTBRANCH_1 0x1dc
1491	#define MSR_P4_LASTBRANCH_2 0x1dd
1492	#define MSR_P4_LASTBRANCH_3 0x1de
1493
1494	/** LBR Top-of-stack MSR (index to most recent record). */
1495	#define MSR_P4_LASTBRANCH_TOS 0x1da
1496	/** @} */
1497
1498	/** @name Last branch registers for Core 2 and related Xeons.
1499	* @{ */
1500	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1501	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1502	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1503	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1504
1505	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1506	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1507	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1508	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1509
1510	/** LBR Top-of-stack MSR (index to most recent record). */
1511	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1512	/** @} */
1513
1514	/** @name Last branch registers.
1515	* @{ */
1516	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1517	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1518	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1519	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1520	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1521	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1522	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1523	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1524	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1525	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1526	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1527	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1528	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1529	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1530	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1531	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1532	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1533	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1534	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1535	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1536	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1537	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1538	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1539	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1540	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1541	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1542	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1543	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1544	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1545	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1546	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1547	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1548
1549	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1550	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1551	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1552	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1553	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1554	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1555	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1556	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1557	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1558	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1559	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1560	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1561	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1562	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1563	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1564	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1565	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1566	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1567	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1568	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1569	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1570	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1571	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1572	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1573	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1574	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1575	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1576	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1577	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1578	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1579	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1580	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1581
1582	#define MSR_LASTBRANCH_0_INFO 0xdc0
1583	#define MSR_LASTBRANCH_1_INFO 0xdc1
1584	#define MSR_LASTBRANCH_2_INFO 0xdc2
1585	#define MSR_LASTBRANCH_3_INFO 0xdc3
1586	#define MSR_LASTBRANCH_4_INFO 0xdc4
1587	#define MSR_LASTBRANCH_5_INFO 0xdc5
1588	#define MSR_LASTBRANCH_6_INFO 0xdc6
1589	#define MSR_LASTBRANCH_7_INFO 0xdc7
1590	#define MSR_LASTBRANCH_8_INFO 0xdc8
1591	#define MSR_LASTBRANCH_9_INFO 0xdc9
1592	#define MSR_LASTBRANCH_10_INFO 0xdca
1593	#define MSR_LASTBRANCH_11_INFO 0xdcb
1594	#define MSR_LASTBRANCH_12_INFO 0xdcc
1595	#define MSR_LASTBRANCH_13_INFO 0xdcd
1596	#define MSR_LASTBRANCH_14_INFO 0xdce
1597	#define MSR_LASTBRANCH_15_INFO 0xdcf
1598	#define MSR_LASTBRANCH_16_INFO 0xdd0
1599	#define MSR_LASTBRANCH_17_INFO 0xdd1
1600	#define MSR_LASTBRANCH_18_INFO 0xdd2
1601	#define MSR_LASTBRANCH_19_INFO 0xdd3
1602	#define MSR_LASTBRANCH_20_INFO 0xdd4
1603	#define MSR_LASTBRANCH_21_INFO 0xdd5
1604	#define MSR_LASTBRANCH_22_INFO 0xdd6
1605	#define MSR_LASTBRANCH_23_INFO 0xdd7
1606	#define MSR_LASTBRANCH_24_INFO 0xdd8
1607	#define MSR_LASTBRANCH_25_INFO 0xdd9
1608	#define MSR_LASTBRANCH_26_INFO 0xdda
1609	#define MSR_LASTBRANCH_27_INFO 0xddb
1610	#define MSR_LASTBRANCH_28_INFO 0xddc
1611	#define MSR_LASTBRANCH_29_INFO 0xddd
1612	#define MSR_LASTBRANCH_30_INFO 0xdde
1613	#define MSR_LASTBRANCH_31_INFO 0xddf
1614
1615	/** LBR branch tracking selection MSR. */
1616	#define MSR_LASTBRANCH_SELECT 0x1c8
1617	/** LBR Top-of-stack MSR (index to most recent record). */
1618	#define MSR_LASTBRANCH_TOS 0x1c9
1619	/** @} */
1620
1621	/** @name Last event record registers.
1622	* @{ */
1623	/** Last event record source IP register. */
1624	#define MSR_LER_FROM_IP 0x1dd
1625	/** Last event record destination IP register. */
1626	#define MSR_LER_TO_IP 0x1de
1627	/** @} */
1628
1629	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1630	#define MSR_IA32_TSX_CTRL 0x122
1631
1632	/** Variable range MTRRs.
1633	* @{ */
1634	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1635	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1636	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1637	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1638	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1639	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1640	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1641	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1642	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1643	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1644	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1645	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1646	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1647	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1648	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1649	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1650	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1651	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1652	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1653	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1654	/** @} */
1655
1656	/** Fixed range MTRRs.
1657	* @{ */
1658	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1659	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1660	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1661	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1662	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1663	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1664	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1665	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1666	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1667	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1668	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1669	/** @} */
1670
1671	/** MTRR Default Range. */
1672	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1673
1674	/** Global performance counter control facilities (Intel only). */
1675	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1676	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1677	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1678
1679	/** Precise Event Based sampling (Intel only). */
1680	#define MSR_IA32_PEBS_ENABLE 0x3F1
1681
1682	#define MSR_IA32_MC0_CTL 0x400
1683	#define MSR_IA32_MC0_STATUS 0x401
1684
1685	/** Basic VMX information. */
1686	#define MSR_IA32_VMX_BASIC 0x480
1687	/** Allowed settings for pin-based VM execution controls. */
1688	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1689	/** Allowed settings for proc-based VM execution controls. */
1690	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1691	/** Allowed settings for the VM-exit controls. */
1692	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1693	/** Allowed settings for the VM-entry controls. */
1694	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1695	/** Misc VMX info. */
1696	#define MSR_IA32_VMX_MISC 0x485
1697	/** Fixed cleared bits in CR0. */
1698	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1699	/** Fixed set bits in CR0. */
1700	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1701	/** Fixed cleared bits in CR4. */
1702	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1703	/** Fixed set bits in CR4. */
1704	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1705	/** Information for enumerating fields in the VMCS. */
1706	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1707	/** Allowed settings for secondary processor-based VM-execution controls. */
1708	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1709	/** EPT capabilities. */
1710	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1711	/** Allowed settings of all pin-based VM execution controls. */
1712	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1713	/** Allowed settings of all proc-based VM execution controls. */
1714	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1715	/** Allowed settings of all VMX exit controls. */
1716	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1717	/** Allowed settings of all VMX entry controls. */
1718	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1719	/** Allowed settings for the VM-function controls. */
1720	#define MSR_IA32_VMX_VMFUNC 0x491
1721	/** Tertiary processor-based VM execution controls. */
1722	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1723	/** Secondary VM-exit controls. */
1724	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1725
1726	/** Intel PT - Enable and control for trace packet generation. */
1727	#define MSR_IA32_RTIT_CTL 0x570
1728
1729	/** DS Save Area (R/W). */
1730	#define MSR_IA32_DS_AREA 0x600
1731	/** Running Average Power Limit (RAPL) power units. */
1732	#define MSR_RAPL_POWER_UNIT 0x606
1733	/** Package C3 Interrupt Response Limit. */
1734	#define MSR_PKGC3_IRTL 0x60a
1735	/** Package C6/C7S Interrupt Response Limit 1. */
1736	#define MSR_PKGC_IRTL1 0x60b
1737	/** Package C6/C7S Interrupt Response Limit 2. */
1738	#define MSR_PKGC_IRTL2 0x60c
1739	/** Package C2 Residency Counter. */
1740	#define MSR_PKG_C2_RESIDENCY 0x60d
1741	/** PKG RAPL Power Limit Control. */
1742	#define MSR_PKG_POWER_LIMIT 0x610
1743	/** PKG Energy Status. */
1744	#define MSR_PKG_ENERGY_STATUS 0x611
1745	/** PKG Perf Status. */
1746	#define MSR_PKG_PERF_STATUS 0x613
1747	/** PKG RAPL Parameters. */
1748	#define MSR_PKG_POWER_INFO 0x614
1749	/** DRAM RAPL Power Limit Control. */
1750	#define MSR_DRAM_POWER_LIMIT 0x618
1751	/** DRAM Energy Status. */
1752	#define MSR_DRAM_ENERGY_STATUS 0x619
1753	/** DRAM Performance Throttling Status. */
1754	#define MSR_DRAM_PERF_STATUS 0x61b
1755	/** DRAM RAPL Parameters. */
1756	#define MSR_DRAM_POWER_INFO 0x61c
1757	/** Package C10 Residency Counter. */
1758	#define MSR_PKG_C10_RESIDENCY 0x632
1759	/** PP0 Energy Status. */
1760	#define MSR_PP0_ENERGY_STATUS 0x639
1761	/** PP1 Energy Status. */
1762	#define MSR_PP1_ENERGY_STATUS 0x641
1763	/** Turbo Activation Ratio. */
1764	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1765	/** Core Performance Limit Reasons. */
1766	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1767
1768	/** Userspace Control flow Enforcement Technology setting. */
1769	#define MSR_IA32_U_CET 0x6a0
1770	/** Supervisor space Control flow Enforcement Technology setting. */
1771	#define MSR_IA32_S_CET 0x6a2
1772	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1773	* @{ */
1774	/** Enables the Shadow stack. */
1775	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1776	/** Enables WRSS{D,Q}W instructions. */
1777	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1778	/** Enables indirect branch tracking. */
1779	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1780	/** Enable legacy compatibility treatment for indirect branch tracking. */
1781	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1782	/** Enables the use of no-track prefix for indirect branch tracking. */
1783	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1784	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1785	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1786	/** Suppresses indirect branch tracking. */
1787	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
1788	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
1789	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
1790	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
1791	* on a ENDBRANCH instruction. */
1792	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
1793	/** @} */
1794
1795	/** X2APIC MSR range start. */
1796	#define MSR_IA32_X2APIC_START 0x800
1797	/** X2APIC MSR - APIC ID Register. */
1798	#define MSR_IA32_X2APIC_ID 0x802
1799	/** X2APIC MSR - APIC Version Register. */
1800	#define MSR_IA32_X2APIC_VERSION 0x803
1801	/** X2APIC MSR - Task Priority Register. */
1802	#define MSR_IA32_X2APIC_TPR 0x808
1803	/** X2APIC MSR - Processor Priority register. */
1804	#define MSR_IA32_X2APIC_PPR 0x80A
1805	/** X2APIC MSR - End Of Interrupt register. */
1806	#define MSR_IA32_X2APIC_EOI 0x80B
1807	/** X2APIC MSR - Logical Destination Register. */
1808	#define MSR_IA32_X2APIC_LDR 0x80D
1809	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1810	#define MSR_IA32_X2APIC_SVR 0x80F
1811	/** X2APIC MSR - In-service Register (bits 31:0). */
1812	#define MSR_IA32_X2APIC_ISR0 0x810
1813	/** X2APIC MSR - In-service Register (bits 63:32). */
1814	#define MSR_IA32_X2APIC_ISR1 0x811
1815	/** X2APIC MSR - In-service Register (bits 95:64). */
1816	#define MSR_IA32_X2APIC_ISR2 0x812
1817	/** X2APIC MSR - In-service Register (bits 127:96). */
1818	#define MSR_IA32_X2APIC_ISR3 0x813
1819	/** X2APIC MSR - In-service Register (bits 159:128). */
1820	#define MSR_IA32_X2APIC_ISR4 0x814
1821	/** X2APIC MSR - In-service Register (bits 191:160). */
1822	#define MSR_IA32_X2APIC_ISR5 0x815
1823	/** X2APIC MSR - In-service Register (bits 223:192). */
1824	#define MSR_IA32_X2APIC_ISR6 0x816
1825	/** X2APIC MSR - In-service Register (bits 255:224). */
1826	#define MSR_IA32_X2APIC_ISR7 0x817
1827	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1828	#define MSR_IA32_X2APIC_TMR0 0x818
1829	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1830	#define MSR_IA32_X2APIC_TMR1 0x819
1831	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1832	#define MSR_IA32_X2APIC_TMR2 0x81A
1833	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1834	#define MSR_IA32_X2APIC_TMR3 0x81B
1835	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1836	#define MSR_IA32_X2APIC_TMR4 0x81C
1837	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1838	#define MSR_IA32_X2APIC_TMR5 0x81D
1839	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1840	#define MSR_IA32_X2APIC_TMR6 0x81E
1841	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1842	#define MSR_IA32_X2APIC_TMR7 0x81F
1843	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1844	#define MSR_IA32_X2APIC_IRR0 0x820
1845	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1846	#define MSR_IA32_X2APIC_IRR1 0x821
1847	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1848	#define MSR_IA32_X2APIC_IRR2 0x822
1849	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1850	#define MSR_IA32_X2APIC_IRR3 0x823
1851	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1852	#define MSR_IA32_X2APIC_IRR4 0x824
1853	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1854	#define MSR_IA32_X2APIC_IRR5 0x825
1855	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1856	#define MSR_IA32_X2APIC_IRR6 0x826
1857	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1858	#define MSR_IA32_X2APIC_IRR7 0x827
1859	/** X2APIC MSR - Error Status Register. */
1860	#define MSR_IA32_X2APIC_ESR 0x828
1861	/** X2APIC MSR - LVT CMCI Register. */
1862	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1863	/** X2APIC MSR - Interrupt Command Register. */
1864	#define MSR_IA32_X2APIC_ICR 0x830
1865	/** X2APIC MSR - LVT Timer Register. */
1866	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1867	/** X2APIC MSR - LVT Thermal Sensor Register. */
1868	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1869	/** X2APIC MSR - LVT Performance Counter Register. */
1870	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1871	/** X2APIC MSR - LVT LINT0 Register. */
1872	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1873	/** X2APIC MSR - LVT LINT1 Register. */
1874	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1875	/** X2APIC MSR - LVT Error Register . */
1876	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1877	/** X2APIC MSR - Timer Initial Count Register. */
1878	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1879	/** X2APIC MSR - Timer Current Count Register. */
1880	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1881	/** X2APIC MSR - Timer Divide Configuration Register. */
1882	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1883	/** X2APIC MSR - Self IPI. */
1884	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1885	/** X2APIC MSR range end. */
1886	#define MSR_IA32_X2APIC_END 0x8FF
1887	/** X2APIC MSR - LVT start range. */
1888	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1889	/** X2APIC MSR - LVT end range (inclusive). */
1890	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1891
1892	/** K6 EFER - Extended Feature Enable Register. */
1893	#define MSR_K6_EFER UINT32_C(0xc0000080)
1894	/** @todo document EFER */
1895	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1896	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1897	/** Bit 8 - LME - Long mode enabled. (R/W) */
1898	#define MSR_K6_EFER_LME RT_BIT_32(8)
1899	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1900	/** Bit 10 - LMA - Long mode active. (R) */
1901	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1902	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1903	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1904	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1905	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1906	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1907	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1908	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1909	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1910	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1911	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1912	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1913	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1914	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1915	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1916
1917	/** K6 STAR - SYSCALL/RET targets. */
1918	#define MSR_K6_STAR UINT32_C(0xc0000081)
1919	/** Shift value for getting the SYSRET CS and SS value. */
1920	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1921	/** Shift value for getting the SYSCALL CS and SS value. */
1922	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1923	/** Selector mask for use after shifting. */
1924	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1925	/** The mask which give the SYSCALL EIP. */
1926	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1927	/** K6 WHCR - Write Handling Control Register. */
1928	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1929	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1930	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1931	/** K6 PSOR - Processor State Observability Register. */
1932	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1933	/** K6 PFIR - Page Flush/Invalidate Register. */
1934	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1935
1936	/** Performance counter MSRs. (AMD only) */
1937	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1938	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1939	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1940	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1941	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1942	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1943	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1944	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1945
1946	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1947	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1948	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1949	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1950	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1951	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1952	/** K8 FS.base - The 64-bit base FS register. */
1953	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1954	/** K8 GS.base - The 64-bit base GS register. */
1955	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1956	/** K8 KernelGSbase - Used with SWAPGS. */
1957	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1958	/** K8 TSC_AUX - Used with RDTSCP. */
1959	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1960	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1961	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1962	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1963	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1964	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1965	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1966	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1967	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1968
1969	/** SMM MSRs. */
1970	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1971	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1972	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1973
1974	/** North bridge config? See BIOS & Kernel dev guides for
1975	* details. */
1976	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1977
1978	/** Hypertransport interrupt pending register.
1979	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1980	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1981
1982	/** SVM Control. */
1983	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1984	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1985	* features. */
1986	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1987	/** If set, non-intercepted INIT signals are converted to \#SX
1988	* exceptions. */
1989	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1990	/** Disables A20 masking. */
1991	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1992	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1993	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1994	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1995	* clear, EFER.SVME can be written normally. */
1996	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1997
1998	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1999	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2000	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2001	* host state during world switch. */
2002	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2003
2004	/** Virtualized speculation control for AMD processors.
2005	*
2006	* Unified interface among different CPU generations.
2007	* The VMM will set any architectural MSRs based on the CPU.
2008	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2009	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2010	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2011	/** Speculative Store Bypass Disable. */
2012	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2013
2014	/** @} */
2015
2016
2017	/** @name Page Table / Directory / Directory Pointers / L4.
2018	* @{
2019	*/
2020
2021	/** Page table/directory entry as an unsigned integer. */
2022	typedef uint32_t X86PGUINT;
2023	/** Pointer to a page table/directory table entry as an unsigned integer. */
2024	typedef X86PGUINT *PX86PGUINT;
2025	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2026	typedef X86PGUINT const *PCX86PGUINT;
2027
2028	/** Number of entries in a 32-bit PT/PD. */
2029	#define X86_PG_ENTRIES 1024
2030
2031
2032	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2033	typedef uint64_t X86PGPAEUINT;
2034	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2035	typedef X86PGPAEUINT *PX86PGPAEUINT;
2036	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2037	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2038
2039	/** Number of entries in a PAE PT/PD. */
2040	#define X86_PG_PAE_ENTRIES 512
2041	/** Number of entries in a PAE PDPT. */
2042	#define X86_PG_PAE_PDPE_ENTRIES 4
2043
2044	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2045	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2046	/** Number of entries in an AMD64 PDPT.
2047	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2048	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2049
2050	/** The size of a default page. */
2051	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2052	/** The page shift of a default page. */
2053	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2054	/** The default page offset mask. */
2055	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2056	/** The default page base mask for virtual addresses. */
2057	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2058	/** The default page base mask for virtual addresses - 32bit version. */
2059	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2060
2061	/** The size of a 4KB page. */
2062	#define X86_PAGE_4K_SIZE _4K
2063	/** The page shift of a 4KB page. */
2064	#define X86_PAGE_4K_SHIFT 12
2065	/** The 4KB page offset mask. */
2066	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2067	/** The 4KB page base mask for virtual addresses. */
2068	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2069	/** The 4KB page base mask for virtual addresses - 32bit version. */
2070	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2071
2072	/** The size of a 2MB page. */
2073	#define X86_PAGE_2M_SIZE _2M
2074	/** The page shift of a 2MB page. */
2075	#define X86_PAGE_2M_SHIFT 21
2076	/** The 2MB page offset mask. */
2077	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2078	/** The 2MB page base mask for virtual addresses. */
2079	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2080	/** The 2MB page base mask for virtual addresses - 32bit version. */
2081	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2082
2083	/** The size of a 4MB page. */
2084	#define X86_PAGE_4M_SIZE _4M
2085	/** The page shift of a 4MB page. */
2086	#define X86_PAGE_4M_SHIFT 22
2087	/** The 4MB page offset mask. */
2088	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2089	/** The 4MB page base mask for virtual addresses. */
2090	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2091	/** The 4MB page base mask for virtual addresses - 32bit version. */
2092	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2093
2094	/** The size of a 1GB page. */
2095	#define X86_PAGE_1G_SIZE _1G
2096	/** The page shift of a 1GB page. */
2097	#define X86_PAGE_1G_SHIFT 30
2098	/** The 1GB page offset mask. */
2099	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2100	/** The 1GB page base mask for virtual addresses. */
2101	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2102
2103	/**
2104	* Check if the given address is canonical.
2105	*/
2106	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2107
2108	/**
2109	* Gets the page base mask given the page shift.
2110	*/
2111	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2112
2113	/**
2114	* Gets the page offset mask given the page shift.
2115	*/
2116	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2117
2118
2119	/** @name Page Table Entry
2120	* @{
2121	*/
2122	/** Bit 0 - P - Present bit. */
2123	#define X86_PTE_BIT_P 0
2124	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2125	#define X86_PTE_BIT_RW 1
2126	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2127	#define X86_PTE_BIT_US 2
2128	/** Bit 3 - PWT - Page level write thru bit. */
2129	#define X86_PTE_BIT_PWT 3
2130	/** Bit 4 - PCD - Page level cache disable bit. */
2131	#define X86_PTE_BIT_PCD 4
2132	/** Bit 5 - A - Access bit. */
2133	#define X86_PTE_BIT_A 5
2134	/** Bit 6 - D - Dirty bit. */
2135	#define X86_PTE_BIT_D 6
2136	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2137	#define X86_PTE_BIT_PAT 7
2138	/** Bit 8 - G - Global flag. */
2139	#define X86_PTE_BIT_G 8
2140	/** Bits 63 - NX - PAE/LM - No execution flag. */
2141	#define X86_PTE_PAE_BIT_NX 63
2142
2143	/** Bit 0 - P - Present bit mask. */
2144	#define X86_PTE_P RT_BIT_32(0)
2145	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2146	#define X86_PTE_RW RT_BIT_32(1)
2147	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2148	#define X86_PTE_US RT_BIT_32(2)
2149	/** Bit 3 - PWT - Page level write thru bit mask. */
2150	#define X86_PTE_PWT RT_BIT_32(3)
2151	/** Bit 4 - PCD - Page level cache disable bit mask. */
2152	#define X86_PTE_PCD RT_BIT_32(4)
2153	/** Bit 5 - A - Access bit mask. */
2154	#define X86_PTE_A RT_BIT_32(5)
2155	/** Bit 6 - D - Dirty bit mask. */
2156	#define X86_PTE_D RT_BIT_32(6)
2157	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2158	#define X86_PTE_PAT RT_BIT_32(7)
2159	/** Bit 8 - G - Global bit mask. */
2160	#define X86_PTE_G RT_BIT_32(8)
2161
2162	/** Bits 9-11 - - Available for use to system software. */
2163	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2164	/** Bits 12-31 - - Physical Page number of the next level. */
2165	#define X86_PTE_PG_MASK ( 0xfffff000 )
2166
2167	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2168	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2169	/** Bits 63 - NX - PAE/LM - No execution flag. */
2170	#define X86_PTE_PAE_NX RT_BIT_64(63)
2171	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2172	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2173	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2174	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2175	/** No bits - - LM - MBZ bits when NX is active. */
2176	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2177	/** Bits 63 - - LM - MBZ bits when no NX. */
2178	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2179
2180	/**
2181	* Page table entry.
2182	*/
2183	typedef struct X86PTEBITS
2184	{
2185	/** Flags whether(=1) or not the page is present. */
2186	uint32_t u1Present : 1;
2187	/** Read(=0) / Write(=1) flag. */
2188	uint32_t u1Write : 1;
2189	/** User(=1) / Supervisor (=0) flag. */
2190	uint32_t u1User : 1;
2191	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2192	uint32_t u1WriteThru : 1;
2193	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2194	uint32_t u1CacheDisable : 1;
2195	/** Accessed flag.
2196	* Indicates that the page have been read or written to. */
2197	uint32_t u1Accessed : 1;
2198	/** Dirty flag.
2199	* Indicates that the page has been written to. */
2200	uint32_t u1Dirty : 1;
2201	/** Reserved / If PAT enabled, bit 2 of the index. */
2202	uint32_t u1PAT : 1;
2203	/** Global flag. (Ignored in all but final level.) */
2204	uint32_t u1Global : 1;
2205	/** Available for use to system software. */
2206	uint32_t u3Available : 3;
2207	/** Physical Page number of the next level. */
2208	uint32_t u20PageNo : 20;
2209	} X86PTEBITS;
2210	#ifndef VBOX_FOR_DTRACE_LIB
2211	AssertCompileSize(X86PTEBITS, 4);
2212	#endif
2213	/** Pointer to a page table entry. */
2214	typedef X86PTEBITS *PX86PTEBITS;
2215	/** Pointer to a const page table entry. */
2216	typedef const X86PTEBITS *PCX86PTEBITS;
2217
2218	/**
2219	* Page table entry.
2220	*/
2221	typedef union X86PTE
2222	{
2223	/** Unsigned integer view */
2224	X86PGUINT u;
2225	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2226	/** Bit field view. */
2227	X86PTEBITS n;
2228	#endif
2229	/** 32-bit view. */
2230	uint32_t au32[1];
2231	/** 16-bit view. */
2232	uint16_t au16[2];
2233	/** 8-bit view. */
2234	uint8_t au8[4];
2235	} X86PTE;
2236	#ifndef VBOX_FOR_DTRACE_LIB
2237	AssertCompileSize(X86PTE, 4);
2238	#endif
2239	/** Pointer to a page table entry. */
2240	typedef X86PTE *PX86PTE;
2241	/** Pointer to a const page table entry. */
2242	typedef const X86PTE *PCX86PTE;
2243
2244
2245	/**
2246	* PAE page table entry.
2247	*/
2248	typedef struct X86PTEPAEBITS
2249	{
2250	/** Flags whether(=1) or not the page is present. */
2251	uint32_t u1Present : 1;
2252	/** Read(=0) / Write(=1) flag. */
2253	uint32_t u1Write : 1;
2254	/** User(=1) / Supervisor(=0) flag. */
2255	uint32_t u1User : 1;
2256	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2257	uint32_t u1WriteThru : 1;
2258	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2259	uint32_t u1CacheDisable : 1;
2260	/** Accessed flag.
2261	* Indicates that the page have been read or written to. */
2262	uint32_t u1Accessed : 1;
2263	/** Dirty flag.
2264	* Indicates that the page has been written to. */
2265	uint32_t u1Dirty : 1;
2266	/** Reserved / If PAT enabled, bit 2 of the index. */
2267	uint32_t u1PAT : 1;
2268	/** Global flag. (Ignored in all but final level.) */
2269	uint32_t u1Global : 1;
2270	/** Available for use to system software. */
2271	uint32_t u3Available : 3;
2272	/** Physical Page number of the next level - Low Part. Don't use this. */
2273	uint32_t u20PageNoLow : 20;
2274	/** Physical Page number of the next level - High Part. Don't use this. */
2275	uint32_t u20PageNoHigh : 20;
2276	/** MBZ bits */
2277	uint32_t u11Reserved : 11;
2278	/** No Execute flag. */
2279	uint32_t u1NoExecute : 1;
2280	} X86PTEPAEBITS;
2281	#ifndef VBOX_FOR_DTRACE_LIB
2282	AssertCompileSize(X86PTEPAEBITS, 8);
2283	#endif
2284	/** Pointer to a page table entry. */
2285	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2286	/** Pointer to a page table entry. */
2287	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2288
2289	/**
2290	* PAE Page table entry.
2291	*/
2292	typedef union X86PTEPAE
2293	{
2294	/** Unsigned integer view */
2295	X86PGPAEUINT u;
2296	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2297	/** Bit field view. */
2298	X86PTEPAEBITS n;
2299	#endif
2300	/** 32-bit view. */
2301	uint32_t au32[2];
2302	/** 16-bit view. */
2303	uint16_t au16[4];
2304	/** 8-bit view. */
2305	uint8_t au8[8];
2306	} X86PTEPAE;
2307	#ifndef VBOX_FOR_DTRACE_LIB
2308	AssertCompileSize(X86PTEPAE, 8);
2309	#endif
2310	/** Pointer to a PAE page table entry. */
2311	typedef X86PTEPAE *PX86PTEPAE;
2312	/** Pointer to a const PAE page table entry. */
2313	typedef const X86PTEPAE *PCX86PTEPAE;
2314	/** @} */
2315
2316	/**
2317	* Page table.
2318	*/
2319	typedef struct X86PT
2320	{
2321	/** PTE Array. */
2322	X86PTE a[X86_PG_ENTRIES];
2323	} X86PT;
2324	#ifndef VBOX_FOR_DTRACE_LIB
2325	AssertCompileSize(X86PT, 4096);
2326	#endif
2327	/** Pointer to a page table. */
2328	typedef X86PT *PX86PT;
2329	/** Pointer to a const page table. */
2330	typedef const X86PT *PCX86PT;
2331
2332	/** The page shift to get the PT index. */
2333	#define X86_PT_SHIFT 12
2334	/** The PT index mask (apply to a shifted page address). */
2335	#define X86_PT_MASK 0x3ff
2336
2337
2338	/**
2339	* Page directory.
2340	*/
2341	typedef struct X86PTPAE
2342	{
2343	/** PTE Array. */
2344	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2345	} X86PTPAE;
2346	#ifndef VBOX_FOR_DTRACE_LIB
2347	AssertCompileSize(X86PTPAE, 4096);
2348	#endif
2349	/** Pointer to a page table. */
2350	typedef X86PTPAE *PX86PTPAE;
2351	/** Pointer to a const page table. */
2352	typedef const X86PTPAE *PCX86PTPAE;
2353
2354	/** The page shift to get the PA PTE index. */
2355	#define X86_PT_PAE_SHIFT 12
2356	/** The PAE PT index mask (apply to a shifted page address). */
2357	#define X86_PT_PAE_MASK 0x1ff
2358
2359
2360	/** @name 4KB Page Directory Entry
2361	* @{
2362	*/
2363	/** Bit 0 - P - Present bit. */
2364	#define X86_PDE_P RT_BIT_32(0)
2365	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2366	#define X86_PDE_RW RT_BIT_32(1)
2367	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2368	#define X86_PDE_US RT_BIT_32(2)
2369	/** Bit 3 - PWT - Page level write thru bit. */
2370	#define X86_PDE_PWT RT_BIT_32(3)
2371	/** Bit 4 - PCD - Page level cache disable bit. */
2372	#define X86_PDE_PCD RT_BIT_32(4)
2373	/** Bit 5 - A - Access bit. */
2374	#define X86_PDE_A RT_BIT_32(5)
2375	/** Bit 7 - PS - Page size attribute.
2376	* Clear mean 4KB pages, set means large pages (2/4MB). */
2377	#define X86_PDE_PS RT_BIT_32(7)
2378	/** Bits 9-11 - - Available for use to system software. */
2379	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2380	/** Bits 12-31 - - Physical Page number of the next level. */
2381	#define X86_PDE_PG_MASK ( 0xfffff000 )
2382
2383	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2384	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2385	/** Bits 63 - NX - PAE/LM - No execution flag. */
2386	#define X86_PDE_PAE_NX RT_BIT_64(63)
2387	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2388	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2389	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2390	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2391	/** Bit 7 - - LM - MBZ bits when NX is active. */
2392	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2393	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2394	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2395
2396	/**
2397	* Page directory entry.
2398	*/
2399	typedef struct X86PDEBITS
2400	{
2401	/** Flags whether(=1) or not the page is present. */
2402	uint32_t u1Present : 1;
2403	/** Read(=0) / Write(=1) flag. */
2404	uint32_t u1Write : 1;
2405	/** User(=1) / Supervisor (=0) flag. */
2406	uint32_t u1User : 1;
2407	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2408	uint32_t u1WriteThru : 1;
2409	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2410	uint32_t u1CacheDisable : 1;
2411	/** Accessed flag.
2412	* Indicates that the page has been read or written to. */
2413	uint32_t u1Accessed : 1;
2414	/** Reserved / Ignored (dirty bit). */
2415	uint32_t u1Reserved0 : 1;
2416	/** Size bit if PSE is enabled - in any event it's 0. */
2417	uint32_t u1Size : 1;
2418	/** Reserved / Ignored (global bit). */
2419	uint32_t u1Reserved1 : 1;
2420	/** Available for use to system software. */
2421	uint32_t u3Available : 3;
2422	/** Physical Page number of the next level. */
2423	uint32_t u20PageNo : 20;
2424	} X86PDEBITS;
2425	#ifndef VBOX_FOR_DTRACE_LIB
2426	AssertCompileSize(X86PDEBITS, 4);
2427	#endif
2428	/** Pointer to a page directory entry. */
2429	typedef X86PDEBITS *PX86PDEBITS;
2430	/** Pointer to a const page directory entry. */
2431	typedef const X86PDEBITS *PCX86PDEBITS;
2432
2433
2434	/**
2435	* PAE page directory entry.
2436	*/
2437	typedef struct X86PDEPAEBITS
2438	{
2439	/** Flags whether(=1) or not the page is present. */
2440	uint32_t u1Present : 1;
2441	/** Read(=0) / Write(=1) flag. */
2442	uint32_t u1Write : 1;
2443	/** User(=1) / Supervisor (=0) flag. */
2444	uint32_t u1User : 1;
2445	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2446	uint32_t u1WriteThru : 1;
2447	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2448	uint32_t u1CacheDisable : 1;
2449	/** Accessed flag.
2450	* Indicates that the page has been read or written to. */
2451	uint32_t u1Accessed : 1;
2452	/** Reserved / Ignored (dirty bit). */
2453	uint32_t u1Reserved0 : 1;
2454	/** Size bit if PSE is enabled - in any event it's 0. */
2455	uint32_t u1Size : 1;
2456	/** Reserved / Ignored (global bit). / */
2457	uint32_t u1Reserved1 : 1;
2458	/** Available for use to system software. */
2459	uint32_t u3Available : 3;
2460	/** Physical Page number of the next level - Low Part. Don't use! */
2461	uint32_t u20PageNoLow : 20;
2462	/** Physical Page number of the next level - High Part. Don't use! */
2463	uint32_t u20PageNoHigh : 20;
2464	/** MBZ bits */
2465	uint32_t u11Reserved : 11;
2466	/** No Execute flag. */
2467	uint32_t u1NoExecute : 1;
2468	} X86PDEPAEBITS;
2469	#ifndef VBOX_FOR_DTRACE_LIB
2470	AssertCompileSize(X86PDEPAEBITS, 8);
2471	#endif
2472	/** Pointer to a page directory entry. */
2473	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2474	/** Pointer to a const page directory entry. */
2475	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2476
2477	/** @} */
2478
2479
2480	/** @name 2/4MB Page Directory Entry
2481	* @{
2482	*/
2483	/** Bit 0 - P - Present bit. */
2484	#define X86_PDE4M_P RT_BIT_32(0)
2485	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2486	#define X86_PDE4M_RW RT_BIT_32(1)
2487	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2488	#define X86_PDE4M_US RT_BIT_32(2)
2489	/** Bit 3 - PWT - Page level write thru bit. */
2490	#define X86_PDE4M_PWT RT_BIT_32(3)
2491	/** Bit 4 - PCD - Page level cache disable bit. */
2492	#define X86_PDE4M_PCD RT_BIT_32(4)
2493	/** Bit 5 - A - Access bit. */
2494	#define X86_PDE4M_A RT_BIT_32(5)
2495	/** Bit 6 - D - Dirty bit. */
2496	#define X86_PDE4M_D RT_BIT_32(6)
2497	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2498	#define X86_PDE4M_PS RT_BIT_32(7)
2499	/** Bit 8 - G - Global flag. */
2500	#define X86_PDE4M_G RT_BIT_32(8)
2501	/** Bits 9-11 - AVL - Available for use to system software. */
2502	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2503	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2504	#define X86_PDE4M_PAT RT_BIT_32(12)
2505	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2506	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2507	/** Bits 22-31 - - Physical Page number. */
2508	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2509	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2510	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2511	/** The number of bits to the high part of the page number. */
2512	#define X86_PDE4M_PG_HIGH_SHIFT 19
2513	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2514	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2515
2516	/** Bits 21-51 - - PAE/LM - Physical Page number.
2517	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2518	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2519	/** Bits 63 - NX - PAE/LM - No execution flag. */
2520	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2521	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2522	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2523	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2524	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2525	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2526	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2527	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2528	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2529
2530	/**
2531	* 4MB page directory entry.
2532	*/
2533	typedef struct X86PDE4MBITS
2534	{
2535	/** Flags whether(=1) or not the page is present. */
2536	uint32_t u1Present : 1;
2537	/** Read(=0) / Write(=1) flag. */
2538	uint32_t u1Write : 1;
2539	/** User(=1) / Supervisor (=0) flag. */
2540	uint32_t u1User : 1;
2541	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2542	uint32_t u1WriteThru : 1;
2543	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2544	uint32_t u1CacheDisable : 1;
2545	/** Accessed flag.
2546	* Indicates that the page have been read or written to. */
2547	uint32_t u1Accessed : 1;
2548	/** Dirty flag.
2549	* Indicates that the page has been written to. */
2550	uint32_t u1Dirty : 1;
2551	/** Page size flag - always 1 for 4MB entries. */
2552	uint32_t u1Size : 1;
2553	/** Global flag. */
2554	uint32_t u1Global : 1;
2555	/** Available for use to system software. */
2556	uint32_t u3Available : 3;
2557	/** Reserved / If PAT enabled, bit 2 of the index. */
2558	uint32_t u1PAT : 1;
2559	/** Bits 32-39 of the page number on AMD64.
2560	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2561	uint32_t u8PageNoHigh : 8;
2562	/** Reserved. */
2563	uint32_t u1Reserved : 1;
2564	/** Physical Page number of the page. */
2565	uint32_t u10PageNo : 10;
2566	} X86PDE4MBITS;
2567	#ifndef VBOX_FOR_DTRACE_LIB
2568	AssertCompileSize(X86PDE4MBITS, 4);
2569	#endif
2570	/** Pointer to a page table entry. */
2571	typedef X86PDE4MBITS *PX86PDE4MBITS;
2572	/** Pointer to a const page table entry. */
2573	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2574
2575
2576	/**
2577	* 2MB PAE page directory entry.
2578	*/
2579	typedef struct X86PDE2MPAEBITS
2580	{
2581	/** Flags whether(=1) or not the page is present. */
2582	uint32_t u1Present : 1;
2583	/** Read(=0) / Write(=1) flag. */
2584	uint32_t u1Write : 1;
2585	/** User(=1) / Supervisor(=0) flag. */
2586	uint32_t u1User : 1;
2587	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2588	uint32_t u1WriteThru : 1;
2589	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2590	uint32_t u1CacheDisable : 1;
2591	/** Accessed flag.
2592	* Indicates that the page have been read or written to. */
2593	uint32_t u1Accessed : 1;
2594	/** Dirty flag.
2595	* Indicates that the page has been written to. */
2596	uint32_t u1Dirty : 1;
2597	/** Page size flag - always 1 for 2MB entries. */
2598	uint32_t u1Size : 1;
2599	/** Global flag. */
2600	uint32_t u1Global : 1;
2601	/** Available for use to system software. */
2602	uint32_t u3Available : 3;
2603	/** Reserved / If PAT enabled, bit 2 of the index. */
2604	uint32_t u1PAT : 1;
2605	/** Reserved. */
2606	uint32_t u9Reserved : 9;
2607	/** Physical Page number of the next level - Low part. Don't use! */
2608	uint32_t u10PageNoLow : 10;
2609	/** Physical Page number of the next level - High part. Don't use! */
2610	uint32_t u20PageNoHigh : 20;
2611	/** MBZ bits */
2612	uint32_t u11Reserved : 11;
2613	/** No Execute flag. */
2614	uint32_t u1NoExecute : 1;
2615	} X86PDE2MPAEBITS;
2616	#ifndef VBOX_FOR_DTRACE_LIB
2617	AssertCompileSize(X86PDE2MPAEBITS, 8);
2618	#endif
2619	/** Pointer to a 2MB PAE page table entry. */
2620	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2621	/** Pointer to a 2MB PAE page table entry. */
2622	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2623
2624	/** @} */
2625
2626	/**
2627	* Page directory entry.
2628	*/
2629	typedef union X86PDE
2630	{
2631	/** Unsigned integer view. */
2632	X86PGUINT u;
2633	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2634	/** Normal view. */
2635	X86PDEBITS n;
2636	/** 4MB view (big). */
2637	X86PDE4MBITS b;
2638	#endif
2639	/** 8 bit unsigned integer view. */
2640	uint8_t au8[4];
2641	/** 16 bit unsigned integer view. */
2642	uint16_t au16[2];
2643	/** 32 bit unsigned integer view. */
2644	uint32_t au32[1];
2645	} X86PDE;
2646	#ifndef VBOX_FOR_DTRACE_LIB
2647	AssertCompileSize(X86PDE, 4);
2648	#endif
2649	/** Pointer to a page directory entry. */
2650	typedef X86PDE *PX86PDE;
2651	/** Pointer to a const page directory entry. */
2652	typedef const X86PDE *PCX86PDE;
2653
2654	/**
2655	* PAE page directory entry.
2656	*/
2657	typedef union X86PDEPAE
2658	{
2659	/** Unsigned integer view. */
2660	X86PGPAEUINT u;
2661	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2662	/** Normal view. */
2663	X86PDEPAEBITS n;
2664	/** 2MB page view (big). */
2665	X86PDE2MPAEBITS b;
2666	#endif
2667	/** 8 bit unsigned integer view. */
2668	uint8_t au8[8];
2669	/** 16 bit unsigned integer view. */
2670	uint16_t au16[4];
2671	/** 32 bit unsigned integer view. */
2672	uint32_t au32[2];
2673	} X86PDEPAE;
2674	#ifndef VBOX_FOR_DTRACE_LIB
2675	AssertCompileSize(X86PDEPAE, 8);
2676	#endif
2677	/** Pointer to a page directory entry. */
2678	typedef X86PDEPAE *PX86PDEPAE;
2679	/** Pointer to a const page directory entry. */
2680	typedef const X86PDEPAE *PCX86PDEPAE;
2681
2682	/**
2683	* Page directory.
2684	*/
2685	typedef struct X86PD
2686	{
2687	/** PDE Array. */
2688	X86PDE a[X86_PG_ENTRIES];
2689	} X86PD;
2690	#ifndef VBOX_FOR_DTRACE_LIB
2691	AssertCompileSize(X86PD, 4096);
2692	#endif
2693	/** Pointer to a page directory. */
2694	typedef X86PD *PX86PD;
2695	/** Pointer to a const page directory. */
2696	typedef const X86PD *PCX86PD;
2697
2698	/** The page shift to get the PD index. */
2699	#define X86_PD_SHIFT 22
2700	/** The PD index mask (apply to a shifted page address). */
2701	#define X86_PD_MASK 0x3ff
2702
2703
2704	/**
2705	* PAE page directory.
2706	*/
2707	typedef struct X86PDPAE
2708	{
2709	/** PDE Array. */
2710	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2711	} X86PDPAE;
2712	#ifndef VBOX_FOR_DTRACE_LIB
2713	AssertCompileSize(X86PDPAE, 4096);
2714	#endif
2715	/** Pointer to a PAE page directory. */
2716	typedef X86PDPAE *PX86PDPAE;
2717	/** Pointer to a const PAE page directory. */
2718	typedef const X86PDPAE *PCX86PDPAE;
2719
2720	/** The page shift to get the PAE PD index. */
2721	#define X86_PD_PAE_SHIFT 21
2722	/** The PAE PD index mask (apply to a shifted page address). */
2723	#define X86_PD_PAE_MASK 0x1ff
2724
2725
2726	/** @name Page Directory Pointer Table Entry (PAE)
2727	* @{
2728	*/
2729	/** Bit 0 - P - Present bit. */
2730	#define X86_PDPE_P RT_BIT_32(0)
2731	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2732	#define X86_PDPE_RW RT_BIT_32(1)
2733	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2734	#define X86_PDPE_US RT_BIT_32(2)
2735	/** Bit 3 - PWT - Page level write thru bit. */
2736	#define X86_PDPE_PWT RT_BIT_32(3)
2737	/** Bit 4 - PCD - Page level cache disable bit. */
2738	#define X86_PDPE_PCD RT_BIT_32(4)
2739	/** Bit 5 - A - Access bit. Long Mode only. */
2740	#define X86_PDPE_A RT_BIT_32(5)
2741	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2742	#define X86_PDPE_LM_PS RT_BIT_32(7)
2743	/** Bits 9-11 - - Available for use to system software. */
2744	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2745	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2746	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2747	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2748	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2749	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2750	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2751	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2752	#define X86_PDPE_LM_NX RT_BIT_64(63)
2753	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2754	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2755	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2756	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2757	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2758	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2759	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2760	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2761
2762
2763	/**
2764	* Page directory pointer table entry.
2765	*/
2766	typedef struct X86PDPEBITS
2767	{
2768	/** Flags whether(=1) or not the page is present. */
2769	uint32_t u1Present : 1;
2770	/** Chunk of reserved bits. */
2771	uint32_t u2Reserved : 2;
2772	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2773	uint32_t u1WriteThru : 1;
2774	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2775	uint32_t u1CacheDisable : 1;
2776	/** Chunk of reserved bits. */
2777	uint32_t u4Reserved : 4;
2778	/** Available for use to system software. */
2779	uint32_t u3Available : 3;
2780	/** Physical Page number of the next level - Low Part. Don't use! */
2781	uint32_t u20PageNoLow : 20;
2782	/** Physical Page number of the next level - High Part. Don't use! */
2783	uint32_t u20PageNoHigh : 20;
2784	/** MBZ bits */
2785	uint32_t u12Reserved : 12;
2786	} X86PDPEBITS;
2787	#ifndef VBOX_FOR_DTRACE_LIB
2788	AssertCompileSize(X86PDPEBITS, 8);
2789	#endif
2790	/** Pointer to a page directory pointer table entry. */
2791	typedef X86PDPEBITS *PX86PTPEBITS;
2792	/** Pointer to a const page directory pointer table entry. */
2793	typedef const X86PDPEBITS *PCX86PTPEBITS;
2794
2795	/**
2796	* Page directory pointer table entry. AMD64 version
2797	*/
2798	typedef struct X86PDPEAMD64BITS
2799	{
2800	/** Flags whether(=1) or not the page is present. */
2801	uint32_t u1Present : 1;
2802	/** Read(=0) / Write(=1) flag. */
2803	uint32_t u1Write : 1;
2804	/** User(=1) / Supervisor (=0) flag. */
2805	uint32_t u1User : 1;
2806	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2807	uint32_t u1WriteThru : 1;
2808	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2809	uint32_t u1CacheDisable : 1;
2810	/** Accessed flag.
2811	* Indicates that the page have been read or written to. */
2812	uint32_t u1Accessed : 1;
2813	/** Chunk of reserved bits. */
2814	uint32_t u3Reserved : 3;
2815	/** Available for use to system software. */
2816	uint32_t u3Available : 3;
2817	/** Physical Page number of the next level - Low Part. Don't use! */
2818	uint32_t u20PageNoLow : 20;
2819	/** Physical Page number of the next level - High Part. Don't use! */
2820	uint32_t u20PageNoHigh : 20;
2821	/** MBZ bits */
2822	uint32_t u11Reserved : 11;
2823	/** No Execute flag. */
2824	uint32_t u1NoExecute : 1;
2825	} X86PDPEAMD64BITS;
2826	#ifndef VBOX_FOR_DTRACE_LIB
2827	AssertCompileSize(X86PDPEAMD64BITS, 8);
2828	#endif
2829	/** Pointer to a page directory pointer table entry. */
2830	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2831	/** Pointer to a const page directory pointer table entry. */
2832	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2833
2834	/**
2835	* Page directory pointer table entry for 1GB page. (AMD64 only)
2836	*/
2837	typedef struct X86PDPE1GB
2838	{
2839	/** 0: Flags whether(=1) or not the page is present. */
2840	uint32_t u1Present : 1;
2841	/** 1: Read(=0) / Write(=1) flag. */
2842	uint32_t u1Write : 1;
2843	/** 2: User(=1) / Supervisor (=0) flag. */
2844	uint32_t u1User : 1;
2845	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2846	uint32_t u1WriteThru : 1;
2847	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2848	uint32_t u1CacheDisable : 1;
2849	/** 5: Accessed flag.
2850	* Indicates that the page have been read or written to. */
2851	uint32_t u1Accessed : 1;
2852	/** 6: Dirty flag for 1GB pages. */
2853	uint32_t u1Dirty : 1;
2854	/** 7: Indicates 1GB page if set. */
2855	uint32_t u1Size : 1;
2856	/** 8: Global 1GB page. */
2857	uint32_t u1Global: 1;
2858	/** 9-11: Available for use to system software. */
2859	uint32_t u3Available : 3;
2860	/** 12: PAT bit for 1GB page. */
2861	uint32_t u1PAT : 1;
2862	/** 13-29: MBZ bits. */
2863	uint32_t u17Reserved : 17;
2864	/** 30-31: Physical page number - Low Part. Don't use! */
2865	uint32_t u2PageNoLow : 2;
2866	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2867	uint32_t u20PageNoHigh : 20;
2868	/** 52-62: MBZ bits */
2869	uint32_t u11Reserved : 11;
2870	/** 63: No Execute flag. */
2871	uint32_t u1NoExecute : 1;
2872	} X86PDPE1GB;
2873	#ifndef VBOX_FOR_DTRACE_LIB
2874	AssertCompileSize(X86PDPE1GB, 8);
2875	#endif
2876	/** Pointer to a page directory pointer table entry for a 1GB page. */
2877	typedef X86PDPE1GB *PX86PDPE1GB;
2878	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2879	typedef const X86PDPE1GB *PCX86PDPE1GB;
2880
2881	/**
2882	* Page directory pointer table entry.
2883	*/
2884	typedef union X86PDPE
2885	{
2886	/** Unsigned integer view. */
2887	X86PGPAEUINT u;
2888	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2889	/** Normal view. */
2890	X86PDPEBITS n;
2891	/** AMD64 view. */
2892	X86PDPEAMD64BITS lm;
2893	/** AMD64 big view. */
2894	X86PDPE1GB b;
2895	#endif
2896	/** 8 bit unsigned integer view. */
2897	uint8_t au8[8];
2898	/** 16 bit unsigned integer view. */
2899	uint16_t au16[4];
2900	/** 32 bit unsigned integer view. */
2901	uint32_t au32[2];
2902	} X86PDPE;
2903	#ifndef VBOX_FOR_DTRACE_LIB
2904	AssertCompileSize(X86PDPE, 8);
2905	#endif
2906	/** Pointer to a page directory pointer table entry. */
2907	typedef X86PDPE *PX86PDPE;
2908	/** Pointer to a const page directory pointer table entry. */
2909	typedef const X86PDPE *PCX86PDPE;
2910
2911
2912	/**
2913	* Page directory pointer table.
2914	*/
2915	typedef struct X86PDPT
2916	{
2917	/** PDE Array. */
2918	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2919	} X86PDPT;
2920	#ifndef VBOX_FOR_DTRACE_LIB
2921	AssertCompileSize(X86PDPT, 4096);
2922	#endif
2923	/** Pointer to a page directory pointer table. */
2924	typedef X86PDPT *PX86PDPT;
2925	/** Pointer to a const page directory pointer table. */
2926	typedef const X86PDPT *PCX86PDPT;
2927
2928	/** The page shift to get the PDPT index. */
2929	#define X86_PDPT_SHIFT 30
2930	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2931	#define X86_PDPT_MASK_PAE 0x3
2932	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2933	#define X86_PDPT_MASK_AMD64 0x1ff
2934
2935	/** @} */
2936
2937
2938	/** @name Page Map Level-4 Entry (Long Mode PAE)
2939	* @{
2940	*/
2941	/** Bit 0 - P - Present bit. */
2942	#define X86_PML4E_P RT_BIT_32(0)
2943	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2944	#define X86_PML4E_RW RT_BIT_32(1)
2945	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2946	#define X86_PML4E_US RT_BIT_32(2)
2947	/** Bit 3 - PWT - Page level write thru bit. */
2948	#define X86_PML4E_PWT RT_BIT_32(3)
2949	/** Bit 4 - PCD - Page level cache disable bit. */
2950	#define X86_PML4E_PCD RT_BIT_32(4)
2951	/** Bit 5 - A - Access bit. */
2952	#define X86_PML4E_A RT_BIT_32(5)
2953	/** Bits 9-11 - - Available for use to system software. */
2954	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2955	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2956	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2957	/** Bits 8, 7 - - MBZ bits when NX is active. */
2958	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2959	/** Bits 63, 7 - - MBZ bits when no NX. */
2960	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2961	/** Bits 63 - NX - PAE - No execution flag. */
2962	#define X86_PML4E_NX RT_BIT_64(63)
2963
2964	/**
2965	* Page Map Level-4 Entry
2966	*/
2967	typedef struct X86PML4EBITS
2968	{
2969	/** Flags whether(=1) or not the page is present. */
2970	uint32_t u1Present : 1;
2971	/** Read(=0) / Write(=1) flag. */
2972	uint32_t u1Write : 1;
2973	/** User(=1) / Supervisor (=0) flag. */
2974	uint32_t u1User : 1;
2975	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2976	uint32_t u1WriteThru : 1;
2977	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2978	uint32_t u1CacheDisable : 1;
2979	/** Accessed flag.
2980	* Indicates that the page have been read or written to. */
2981	uint32_t u1Accessed : 1;
2982	/** Chunk of reserved bits. */
2983	uint32_t u3Reserved : 3;
2984	/** Available for use to system software. */
2985	uint32_t u3Available : 3;
2986	/** Physical Page number of the next level - Low Part. Don't use! */
2987	uint32_t u20PageNoLow : 20;
2988	/** Physical Page number of the next level - High Part. Don't use! */
2989	uint32_t u20PageNoHigh : 20;
2990	/** MBZ bits */
2991	uint32_t u11Reserved : 11;
2992	/** No Execute flag. */
2993	uint32_t u1NoExecute : 1;
2994	} X86PML4EBITS;
2995	#ifndef VBOX_FOR_DTRACE_LIB
2996	AssertCompileSize(X86PML4EBITS, 8);
2997	#endif
2998	/** Pointer to a page map level-4 entry. */
2999	typedef X86PML4EBITS *PX86PML4EBITS;
3000	/** Pointer to a const page map level-4 entry. */
3001	typedef const X86PML4EBITS *PCX86PML4EBITS;
3002
3003	/**
3004	* Page Map Level-4 Entry.
3005	*/
3006	typedef union X86PML4E
3007	{
3008	/** Unsigned integer view. */
3009	X86PGPAEUINT u;
3010	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3011	/** Normal view. */
3012	X86PML4EBITS n;
3013	#endif
3014	/** 8 bit unsigned integer view. */
3015	uint8_t au8[8];
3016	/** 16 bit unsigned integer view. */
3017	uint16_t au16[4];
3018	/** 32 bit unsigned integer view. */
3019	uint32_t au32[2];
3020	} X86PML4E;
3021	#ifndef VBOX_FOR_DTRACE_LIB
3022	AssertCompileSize(X86PML4E, 8);
3023	#endif
3024	/** Pointer to a page map level-4 entry. */
3025	typedef X86PML4E *PX86PML4E;
3026	/** Pointer to a const page map level-4 entry. */
3027	typedef const X86PML4E *PCX86PML4E;
3028
3029
3030	/**
3031	* Page Map Level-4.
3032	*/
3033	typedef struct X86PML4
3034	{
3035	/** PDE Array. */
3036	X86PML4E a[X86_PG_PAE_ENTRIES];
3037	} X86PML4;
3038	#ifndef VBOX_FOR_DTRACE_LIB
3039	AssertCompileSize(X86PML4, 4096);
3040	#endif
3041	/** Pointer to a page map level-4. */
3042	typedef X86PML4 *PX86PML4;
3043	/** Pointer to a const page map level-4. */
3044	typedef const X86PML4 *PCX86PML4;
3045
3046	/** The page shift to get the PML4 index. */
3047	#define X86_PML4_SHIFT 39
3048	/** The PML4 index mask (apply to a shifted page address). */
3049	#define X86_PML4_MASK 0x1ff
3050
3051	/** @} */
3052
3053	/** @} */
3054
3055	/**
3056	* Intel PCID invalidation types.
3057	*/
3058	/** Individual address invalidation. */
3059	#define X86_INVPCID_TYPE_INDV_ADDR 0
3060	/** Single-context invalidation. */
3061	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3062	/** All-context including globals invalidation. */
3063	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3064	/** All-context excluding globals invalidation. */
3065	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3066	/** The maximum valid invalidation type value. */
3067	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3068
3069
3070	/** @name Special FPU integer values.
3071	* @{ */
3072	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3073	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3074	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3075	/** @} */
3076
3077	/**
3078	* 32-bit protected mode FSTENV image.
3079	*/
3080	typedef struct X86FSTENV32P
3081	{
3082	uint16_t FCW; /*< 0x00 /
3083	uint16_t padding1; /*< 0x02 /
3084	uint16_t FSW; /*< 0x04 /
3085	uint16_t padding2; /*< 0x06 /
3086	uint16_t FTW; /*< 0x08 /
3087	uint16_t padding3; /*< 0x0a /
3088	uint32_t FPUIP; /*< 0x0c /
3089	uint16_t FPUCS; /*< 0x10 /
3090	uint16_t FOP; /*< 0x12 /
3091	uint32_t FPUDP; /*< 0x14 /
3092	uint16_t FPUDS; /*< 0x18 /
3093	uint16_t padding4; /*< 0x1a /
3094	} X86FSTENV32P;
3095	#ifndef VBOX_FOR_DTRACE_LIB
3096	AssertCompileSize(X86FSTENV32P, 0x1c);
3097	#endif
3098	/** Pointer to a 32-bit protected mode FSTENV image. */
3099	typedef X86FSTENV32P *PX86FSTENV32P;
3100	/** Pointer to a const 32-bit protected mode FSTENV image. */
3101	typedef X86FSTENV32P const *PCX86FSTENV32P;
3102
3103
3104	/**
3105	* 80-bit MMX/FPU register type.
3106	*/
3107	typedef struct X86FPUMMX
3108	{
3109	uint8_t reg[10];
3110	} X86FPUMMX;
3111	#ifndef VBOX_FOR_DTRACE_LIB
3112	AssertCompileSize(X86FPUMMX, 10);
3113	#endif
3114	/** Pointer to a 80-bit MMX/FPU register type. */
3115	typedef X86FPUMMX *PX86FPUMMX;
3116	/** Pointer to a const 80-bit MMX/FPU register type. */
3117	typedef const X86FPUMMX *PCX86FPUMMX;
3118
3119	/** FPU (x87) register. */
3120	typedef union X86FPUREG
3121	{
3122	/** MMX view. */
3123	uint64_t mmx;
3124	/** FPU view - todo. */
3125	X86FPUMMX fpu;
3126	/** Extended precision floating point view. */
3127	RTFLOAT80U r80;
3128	/** Extended precision floating point view v2 */
3129	RTFLOAT80U2 r80Ex;
3130	/** 8-bit view. */
3131	uint8_t au8[16];
3132	/** 16-bit view. */
3133	uint16_t au16[8];
3134	/** 32-bit view. */
3135	uint32_t au32[4];
3136	/** 64-bit view. */
3137	uint64_t au64[2];
3138	/** 128-bit view. (yeah, very helpful) */
3139	uint128_t au128[1];
3140	} X86FPUREG;
3141	#ifndef VBOX_FOR_DTRACE_LIB
3142	AssertCompileSize(X86FPUREG, 16);
3143	#endif
3144	/** Pointer to a FPU register. */
3145	typedef X86FPUREG *PX86FPUREG;
3146	/** Pointer to a const FPU register. */
3147	typedef X86FPUREG const *PCX86FPUREG;
3148
3149	/** FPU (x87) register - v2 with correct size. */
3150	#pragma pack(1)
3151	typedef union X86FPUREG2
3152	{
3153	/** MMX view. */
3154	uint64_t mmx;
3155	/** FPU view - todo. */
3156	X86FPUMMX fpu;
3157	/** Extended precision floating point view. */
3158	RTFLOAT80U r80;
3159	/** 8-bit view. */
3160	uint8_t au8[10];
3161	/** 16-bit view. */
3162	uint16_t au16[5];
3163	/** 32-bit view. */
3164	uint32_t au32[2];
3165	/** 64-bit view. */
3166	uint64_t au64[1];
3167	} X86FPUREG2;
3168	#pragma pack()
3169	#ifndef VBOX_FOR_DTRACE_LIB
3170	AssertCompileSize(X86FPUREG2, 10);
3171	#endif
3172	/** Pointer to a FPU register - v2. */
3173	typedef X86FPUREG2 *PX86FPUREG2;
3174	/** Pointer to a const FPU register - v2. */
3175	typedef X86FPUREG2 const *PCX86FPUREG2;
3176
3177	/**
3178	* XMM register union.
3179	*/
3180	typedef union X86XMMREG
3181	{
3182	/** XMM Register view. */
3183	uint128_t xmm;
3184	/** 8-bit view. */
3185	uint8_t au8[16];
3186	/** 16-bit view. */
3187	uint16_t au16[8];
3188	/** 32-bit view. */
3189	uint32_t au32[4];
3190	/** 64-bit view. */
3191	uint64_t au64[2];
3192	/** Signed 8-bit view. */
3193	int8_t ai8[16];
3194	/** Signed 16-bit view. */
3195	int16_t ai16[8];
3196	/** Signed 32-bit view. */
3197	int32_t ai32[4];
3198	/** Signed 64-bit view. */
3199	int64_t ai64[2];
3200	/** 128-bit view. (yeah, very helpful) */
3201	uint128_t au128[1];
3202	/** Single precision floating point view. */
3203	RTFLOAT32U ar32[4];
3204	/** Double precision floating point view. */
3205	RTFLOAT64U ar64[2];
3206	#ifndef VBOX_FOR_DTRACE_LIB
3207	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3208	RTUINT128U uXmm;
3209	#endif
3210	} X86XMMREG;
3211	#ifndef VBOX_FOR_DTRACE_LIB
3212	AssertCompileSize(X86XMMREG, 16);
3213	#endif
3214	/** Pointer to an XMM register state. */
3215	typedef X86XMMREG *PX86XMMREG;
3216	/** Pointer to a const XMM register state. */
3217	typedef X86XMMREG const *PCX86XMMREG;
3218
3219	/**
3220	* YMM register union.
3221	*/
3222	typedef union X86YMMREG
3223	{
3224	/** YMM register view. */
3225	RTUINT256U ymm;
3226	/** 8-bit view. */
3227	uint8_t au8[32];
3228	/** 16-bit view. */
3229	uint16_t au16[16];
3230	/** 32-bit view. */
3231	uint32_t au32[8];
3232	/** 64-bit view. */
3233	uint64_t au64[4];
3234	/** 128-bit view. (yeah, very helpful) */
3235	uint128_t au128[2];
3236	/** Single precision floating point view. */
3237	RTFLOAT32U ar32[8];
3238	/** Double precision floating point view. */
3239	RTFLOAT64U ar64[4];
3240	/** XMM sub register view. */
3241	X86XMMREG aXmm[2];
3242	} X86YMMREG;
3243	#ifndef VBOX_FOR_DTRACE_LIB
3244	AssertCompileSize(X86YMMREG, 32);
3245	#endif
3246	/** Pointer to an YMM register state. */
3247	typedef X86YMMREG *PX86YMMREG;
3248	/** Pointer to a const YMM register state. */
3249	typedef X86YMMREG const *PCX86YMMREG;
3250
3251	/**
3252	* ZMM register union.
3253	*/
3254	typedef union X86ZMMREG
3255	{
3256	/** 8-bit view. */
3257	uint8_t au8[64];
3258	/** 16-bit view. */
3259	uint16_t au16[32];
3260	/** 32-bit view. */
3261	uint32_t au32[16];
3262	/** 64-bit view. */
3263	uint64_t au64[8];
3264	/** 128-bit view. (yeah, very helpful) */
3265	uint128_t au128[4];
3266	/** Single precision floating point view. */
3267	RTFLOAT32U ar32[16];
3268	/** Double precision floating point view. */
3269	RTFLOAT64U ar64[8];
3270	/** XMM sub register view. */
3271	X86XMMREG aXmm[4];
3272	/** YMM sub register view. */
3273	X86YMMREG aYmm[2];
3274	} X86ZMMREG;
3275	#ifndef VBOX_FOR_DTRACE_LIB
3276	AssertCompileSize(X86ZMMREG, 64);
3277	#endif
3278	/** Pointer to an ZMM register state. */
3279	typedef X86ZMMREG *PX86ZMMREG;
3280	/** Pointer to a const ZMM register state. */
3281	typedef X86ZMMREG const *PCX86ZMMREG;
3282
3283
3284	/**
3285	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3286	*/
3287	#pragma pack(1)
3288	typedef struct X86FPUSTATE
3289	{
3290	/** 0x00 - Control word. */
3291	uint16_t FCW;
3292	/** 0x02 - Alignment word */
3293	uint16_t Dummy1;
3294	/** 0x04 - Status word. */
3295	uint16_t FSW;
3296	/** 0x06 - Alignment word */
3297	uint16_t Dummy2;
3298	/** 0x08 - Tag word */
3299	uint16_t FTW;
3300	/** 0x0a - Alignment word */
3301	uint16_t Dummy3;
3302
3303	/** 0x0c - Instruction pointer. */
3304	uint32_t FPUIP;
3305	/** 0x10 - Code selector. */
3306	uint16_t CS;
3307	/** 0x12 - Opcode. */
3308	uint16_t FOP;
3309	/** 0x14 - Data pointer. */
3310	uint32_t FPUOO;
3311	/** 0x18 - FOS. */
3312	uint16_t FPUOS;
3313	/** 0x0a - Alignment word */
3314	uint16_t Dummy4;
3315	/** 0x1c - FPU register. */
3316	X86FPUREG2 regs[8];
3317	} X86FPUSTATE;
3318	#pragma pack()
3319	AssertCompileSize(X86FPUSTATE, 108);
3320	/** Pointer to a FPU state. */
3321	typedef X86FPUSTATE *PX86FPUSTATE;
3322	/** Pointer to a const FPU state. */
3323	typedef const X86FPUSTATE *PCX86FPUSTATE;
3324
3325	/**
3326	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3327	*/
3328	#pragma pack(1)
3329	typedef struct X86FXSTATE
3330	{
3331	/** 0x00 - Control word. */
3332	uint16_t FCW;
3333	/** 0x02 - Status word. */
3334	uint16_t FSW;
3335	/** 0x04 - Tag word. (The upper byte is always zero.) */
3336	uint16_t FTW;
3337	/** 0x06 - Opcode. */
3338	uint16_t FOP;
3339	/** 0x08 - Instruction pointer. */
3340	uint32_t FPUIP;
3341	/** 0x0c - Code selector. */
3342	uint16_t CS;
3343	uint16_t Rsrvd1;
3344	/** 0x10 - Data pointer. */
3345	uint32_t FPUDP;
3346	/** 0x14 - Data segment */
3347	uint16_t DS;
3348	/** 0x16 */
3349	uint16_t Rsrvd2;
3350	/** 0x18 */
3351	uint32_t MXCSR;
3352	/** 0x1c */
3353	uint32_t MXCSR_MASK;
3354	/** 0x20 - FPU registers. */
3355	X86FPUREG aRegs[8];
3356	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3357	X86XMMREG aXMM[16];
3358	/* - offset 416 - */
3359	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3360	/* - offset 464 - Software usable reserved bits. */
3361	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3362	} X86FXSTATE;
3363	#pragma pack()
3364	/** Pointer to a FPU Extended state. */
3365	typedef X86FXSTATE *PX86FXSTATE;
3366	/** Pointer to a const FPU Extended state. */
3367	typedef const X86FXSTATE *PCX86FXSTATE;
3368
3369	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3370	* magic. Don't forget to update x86.mac if you change this! */
3371	#define X86_OFF_FXSTATE_RSVD 0x1d0
3372	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3373	* forget to update x86.mac if you change this!
3374	* @todo r=bird: This has nothing what-so-ever to do here.... */
3375	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3376	#ifndef VBOX_FOR_DTRACE_LIB
3377	AssertCompileSize(X86FXSTATE, 512);
3378	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3379	#endif
3380
3381	/** @name FPU status word flags.
3382	* @{ */
3383	/** Exception Flag: Invalid operation. */
3384	#define X86_FSW_IE RT_BIT_32(0)
3385	#define X86_FSW_IE_BIT 0
3386	/** Exception Flag: Denormalized operand. */
3387	#define X86_FSW_DE RT_BIT_32(1)
3388	#define X86_FSW_DE_BIT 1
3389	/** Exception Flag: Zero divide. */
3390	#define X86_FSW_ZE RT_BIT_32(2)
3391	#define X86_FSW_ZE_BIT 2
3392	/** Exception Flag: Overflow. */
3393	#define X86_FSW_OE RT_BIT_32(3)
3394	#define X86_FSW_OE_BIT 3
3395	/** Exception Flag: Underflow. */
3396	#define X86_FSW_UE RT_BIT_32(4)
3397	#define X86_FSW_UE_BIT 4
3398	/** Exception Flag: Precision. */
3399	#define X86_FSW_PE RT_BIT_32(5)
3400	#define X86_FSW_PE_BIT 5
3401	/** Stack fault. */
3402	#define X86_FSW_SF RT_BIT_32(6)
3403	#define X86_FSW_SF_BIT 6
3404	/** Error summary status. */
3405	#define X86_FSW_ES RT_BIT_32(7)
3406	#define X86_FSW_ES_BIT 7
3407	/** Mask of exceptions flags, excluding the summary bit. */
3408	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3409	/** Mask of exceptions flags, including the summary bit. */
3410	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3411	/** Condition code 0. */
3412	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3413	#define X86_FSW_C0_BIT 8
3414	/** Condition code 1. */
3415	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3416	#define X86_FSW_C1_BIT 9
3417	/** Condition code 2. */
3418	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3419	#define X86_FSW_C2_BIT 10
3420	/** Top of the stack mask. */
3421	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3422	/** TOP shift value. */
3423	#define X86_FSW_TOP_SHIFT 11
3424	/** Mask for getting TOP value after shifting it right. */
3425	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3426	/** Get the TOP value. */
3427	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3428	/** Get the TOP value offsetted by a_iSt (0-7). */
3429	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3430	/** Condition code 3. */
3431	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3432	#define X86_FSW_C3_BIT 14
3433	/** Mask of exceptions flags, including the summary bit. */
3434	#define X86_FSW_C_MASK UINT16_C(0x4700)
3435	/** FPU busy. */
3436	#define X86_FSW_B RT_BIT_32(15)
3437	/** For use with FPREM and FPREM1. */
3438	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3439	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3440	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3441	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3442	/** For use with FPREM and FPREM1. */
3443	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3444	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3445	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3446	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3447	/** @} */
3448
3449
3450	/** @name FPU control word flags.
3451	* @{ */
3452	/** Exception Mask: Invalid operation. */
3453	#define X86_FCW_IM RT_BIT_32(0)
3454	#define X86_FCW_IM_BIT 0
3455	/** Exception Mask: Denormalized operand. */
3456	#define X86_FCW_DM RT_BIT_32(1)
3457	#define X86_FCW_DM_BIT 1
3458	/** Exception Mask: Zero divide. */
3459	#define X86_FCW_ZM RT_BIT_32(2)
3460	#define X86_FCW_ZM_BIT 2
3461	/** Exception Mask: Overflow. */
3462	#define X86_FCW_OM RT_BIT_32(3)
3463	#define X86_FCW_OM_BIT 3
3464	/** Exception Mask: Underflow. */
3465	#define X86_FCW_UM RT_BIT_32(4)
3466	#define X86_FCW_UM_BIT 4
3467	/** Exception Mask: Precision. */
3468	#define X86_FCW_PM RT_BIT_32(5)
3469	#define X86_FCW_PM_BIT 5
3470	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3471	* @remarks This includes reserved bit 6. */
3472	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3473	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3474	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3475	/** Precision control mask. */
3476	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3477	/** Precision control shift. */
3478	#define X86_FCW_PC_SHIFT 8
3479	/** Precision control: 24-bit. */
3480	#define X86_FCW_PC_24 UINT16_C(0x0000)
3481	/** Precision control: Reserved. */
3482	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3483	/** Precision control: 53-bit. */
3484	#define X86_FCW_PC_53 UINT16_C(0x0200)
3485	/** Precision control: 64-bit. */
3486	#define X86_FCW_PC_64 UINT16_C(0x0300)
3487	/** Rounding control mask. */
3488	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3489	/** Rounding control shift. */
3490	#define X86_FCW_RC_SHIFT 10
3491	/** Rounding control: To nearest. */
3492	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3493	/** Rounding control: Down. */
3494	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3495	/** Rounding control: Up. */
3496	#define X86_FCW_RC_UP UINT16_C(0x0800)
3497	/** Rounding control: Towards zero. */
3498	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3499	/** Infinity control mask - obsolete, 8087 & 287 only. */
3500	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3501	/** Infinity control: Affine - positive infinity is distictly different from
3502	* negative infinity.
3503	* @note 8087, 287 only */
3504	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3505	/** Infinity control: Projective - positive and negative infinity are the
3506	* same (sign ignored).
3507	* @note 8087, 287 only */
3508	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3509	/** Bits which should be zero, apparently. */
3510	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3511	/** @} */
3512
3513	/** @name SSE MXCSR
3514	* @{ */
3515	/** Exception Flag: Invalid operation. */
3516	#define X86_MXCSR_IE RT_BIT_32(0)
3517	/** Exception Flag: Denormalized operand. */
3518	#define X86_MXCSR_DE RT_BIT_32(1)
3519	/** Exception Flag: Zero divide. */
3520	#define X86_MXCSR_ZE RT_BIT_32(2)
3521	/** Exception Flag: Overflow. */
3522	#define X86_MXCSR_OE RT_BIT_32(3)
3523	/** Exception Flag: Underflow. */
3524	#define X86_MXCSR_UE RT_BIT_32(4)
3525	/** Exception Flag: Precision. */
3526	#define X86_MXCSR_PE RT_BIT_32(5)
3527	/** Exception Flags: mask */
3528	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3529
3530	/** Denormals are zero. */
3531	#define X86_MXCSR_DAZ RT_BIT_32(6)
3532
3533	/** Exception Mask: Invalid operation. */
3534	#define X86_MXCSR_IM RT_BIT_32(7)
3535	/** Exception Mask: Denormalized operand. */
3536	#define X86_MXCSR_DM RT_BIT_32(8)
3537	/** Exception Mask: Zero divide. */
3538	#define X86_MXCSR_ZM RT_BIT_32(9)
3539	/** Exception Mask: Overflow. */
3540	#define X86_MXCSR_OM RT_BIT_32(10)
3541	/** Exception Mask: Underflow. */
3542	#define X86_MXCSR_UM RT_BIT_32(11)
3543	/** Exception Mask: Precision. */
3544	#define X86_MXCSR_PM RT_BIT_32(12)
3545	/** Exception Mask: mask. */
3546	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3547	/** Exception Mask: shift. */
3548	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3549
3550	/** Rounding control mask. */
3551	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3552	/** Rounding control shift. */
3553	#define X86_MXCSR_RC_SHIFT 13
3554	/** Rounding control: To nearest. */
3555	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3556	/** Rounding control: Down. */
3557	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3558	/** Rounding control: Up. */
3559	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3560	/** Rounding control: Towards zero. */
3561	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3562
3563	/** Flush-to-zero for masked underflow. */
3564	#define X86_MXCSR_FZ RT_BIT_32(15)
3565
3566	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3567	#define X86_MXCSR_MM RT_BIT_32(17)
3568	/** Bits which should be zero, apparently. */
3569	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3570	/** @} */
3571
3572	/**
3573	* XSAVE header.
3574	*/
3575	typedef struct X86XSAVEHDR
3576	{
3577	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3578	uint64_t bmXState;
3579	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3580	uint64_t bmXComp;
3581	/** Reserved for furture extensions, probably MBZ. */
3582	uint64_t au64Reserved[6];
3583	} X86XSAVEHDR;
3584	#ifndef VBOX_FOR_DTRACE_LIB
3585	AssertCompileSize(X86XSAVEHDR, 64);
3586	#endif
3587	/** Pointer to an XSAVE header. */
3588	typedef X86XSAVEHDR *PX86XSAVEHDR;
3589	/** Pointer to a const XSAVE header. */
3590	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3591
3592
3593	/**
3594	* The high 128-bit YMM register state (XSAVE_C_YMM).
3595	* (The lower 128-bits being in X86FXSTATE.)
3596	*/
3597	typedef struct X86XSAVEYMMHI
3598	{
3599	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3600	X86XMMREG aYmmHi[16];
3601	} X86XSAVEYMMHI;
3602	#ifndef VBOX_FOR_DTRACE_LIB
3603	AssertCompileSize(X86XSAVEYMMHI, 256);
3604	#endif
3605	/** Pointer to a high 128-bit YMM register state. */
3606	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3607	/** Pointer to a const high 128-bit YMM register state. */
3608	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3609
3610	/**
3611	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3612	*/
3613	typedef struct X86XSAVEBNDREGS
3614	{
3615	/** Array of registers (BND0...BND3). */
3616	struct
3617	{
3618	/** Lower bound. */
3619	uint64_t uLowerBound;
3620	/** Upper bound. */
3621	uint64_t uUpperBound;
3622	} aRegs[4];
3623	} X86XSAVEBNDREGS;
3624	#ifndef VBOX_FOR_DTRACE_LIB
3625	AssertCompileSize(X86XSAVEBNDREGS, 64);
3626	#endif
3627	/** Pointer to a MPX bound register state. */
3628	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3629	/** Pointer to a const MPX bound register state. */
3630	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3631
3632	/**
3633	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3634	*/
3635	typedef struct X86XSAVEBNDCFG
3636	{
3637	uint64_t fConfig;
3638	uint64_t fStatus;
3639	} X86XSAVEBNDCFG;
3640	#ifndef VBOX_FOR_DTRACE_LIB
3641	AssertCompileSize(X86XSAVEBNDCFG, 16);
3642	#endif
3643	/** Pointer to a MPX bound config and status register state. */
3644	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3645	/** Pointer to a const MPX bound config and status register state. */
3646	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3647
3648	/**
3649	* AVX-512 opmask state (XSAVE_C_OPMASK).
3650	*/
3651	typedef struct X86XSAVEOPMASK
3652	{
3653	/** The K0..K7 values. */
3654	uint64_t aKRegs[8];
3655	} X86XSAVEOPMASK;
3656	#ifndef VBOX_FOR_DTRACE_LIB
3657	AssertCompileSize(X86XSAVEOPMASK, 64);
3658	#endif
3659	/** Pointer to a AVX-512 opmask state. */
3660	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3661	/** Pointer to a const AVX-512 opmask state. */
3662	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3663
3664	/**
3665	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3666	*/
3667	typedef struct X86XSAVEZMMHI256
3668	{
3669	/** Upper 256-bits of ZMM0-15. */
3670	X86YMMREG aHi256Regs[16];
3671	} X86XSAVEZMMHI256;
3672	#ifndef VBOX_FOR_DTRACE_LIB
3673	AssertCompileSize(X86XSAVEZMMHI256, 512);
3674	#endif
3675	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3676	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3677	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3678	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3679
3680	/**
3681	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3682	*/
3683	typedef struct X86XSAVEZMM16HI
3684	{
3685	/** ZMM16 thru ZMM31. */
3686	X86ZMMREG aRegs[16];
3687	} X86XSAVEZMM16HI;
3688	#ifndef VBOX_FOR_DTRACE_LIB
3689	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3690	#endif
3691	/** Pointer to a state comprising ZMM16-32. */
3692	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3693	/** Pointer to a const state comprising ZMM16-32. */
3694	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3695
3696	/**
3697	* AMD Light weight profiling state (XSAVE_C_LWP).
3698	*
3699	* We probably won't play with this as AMD seems to be dropping from their "zen"
3700	* processor micro architecture.
3701	*/
3702	typedef struct X86XSAVELWP
3703	{
3704	/** Details when needed. */
3705	uint64_t auLater[128/8];
3706	} X86XSAVELWP;
3707	#ifndef VBOX_FOR_DTRACE_LIB
3708	AssertCompileSize(X86XSAVELWP, 128);
3709	#endif
3710
3711
3712	/**
3713	* x86 FPU/SSE/AVX/XXXX state.
3714	*
3715	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3716	* changes to this structure.
3717	*/
3718	typedef struct X86XSAVEAREA
3719	{
3720	/** The x87 and SSE region (or legacy region if you like). */
3721	X86FXSTATE x87;
3722	/** The XSAVE header. */
3723	X86XSAVEHDR Hdr;
3724	/** Beyond the header, there isn't really a fixed layout, but we can
3725	generally assume the YMM (AVX) register extensions are present and
3726	follows immediately. */
3727	union
3728	{
3729	/** The high 128-bit AVX registers for easy access by IEM.
3730	* @note This ASSUMES they will always be here... */
3731	X86XSAVEYMMHI YmmHi;
3732
3733	/** This is a typical layout on intel CPUs (good for debuggers). */
3734	struct
3735	{
3736	X86XSAVEYMMHI YmmHi;
3737	X86XSAVEBNDREGS BndRegs;
3738	X86XSAVEBNDCFG BndCfg;
3739	uint8_t abFudgeToMatchDocs[0xB0];
3740	X86XSAVEOPMASK Opmask;
3741	X86XSAVEZMMHI256 ZmmHi256;
3742	X86XSAVEZMM16HI Zmm16Hi;
3743	} Intel;
3744
3745	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3746	struct
3747	{
3748	X86XSAVEYMMHI YmmHi;
3749	X86XSAVELWP Lwp;
3750	} AmdBd;
3751
3752	/** To enbling static deployments that have a reasonable chance of working for
3753	* the next 3-6 CPU generations without running short on space, we allocate a
3754	* lot of extra space here, making the structure a round 8KB in size. This
3755	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3756	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3757	uint8_t ab[8192 - 512 - 64];
3758	} u;
3759	} X86XSAVEAREA;
3760	#ifndef VBOX_FOR_DTRACE_LIB
3761	AssertCompileSize(X86XSAVEAREA, 8192);
3762	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3763	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3764	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3765	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3766	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3767	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3768	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3769	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3770	#endif
3771	/** Pointer to a XSAVE area. */
3772	typedef X86XSAVEAREA *PX86XSAVEAREA;
3773	/** Pointer to a const XSAVE area. */
3774	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3775
3776
3777	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3778	* @{ */
3779	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3780	#define XSAVE_C_X87_BIT 0
3781	/** Bit 0 - x87 - Legacy FPU state. */
3782	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3783	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3784	#define XSAVE_C_SSE_BIT 1
3785	/** Bit 1 - SSE - 128-bit SSE state. */
3786	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3787	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3788	#define XSAVE_C_YMM_BIT 2
3789	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3790	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3791	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3792	#define XSAVE_C_BNDREGS_BIT 3
3793	/** Bit 3 - BNDREGS - MPX bound register state. */
3794	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3795	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3796	#define XSAVE_C_BNDCSR_BIT 4
3797	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3798	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3799	/** Bit 5 - Opmask - opmask state (bit number). */
3800	#define XSAVE_C_OPMASK_BIT 5
3801	/** Bit 5 - Opmask - opmask state. */
3802	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3803	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3804	#define XSAVE_C_ZMM_HI256_BIT 6
3805	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3806	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3807	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3808	#define XSAVE_C_ZMM_16HI_BIT 7
3809	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3810	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3811	/** Bit 9 - PKRU - Protection-key state (bit number). */
3812	#define XSAVE_C_PKRU_BIT 9
3813	/** Bit 9 - PKRU - Protection-key state. */
3814	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3815	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3816	#define XSAVE_C_LWP_BIT 62
3817	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3818	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3819	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3820	#define XSAVE_C_X_BIT 63
3821	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3822	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3823	/** @} */
3824
3825
3826
3827	/** @name Selector Descriptor
3828	* @{
3829	*/
3830
3831	#ifndef VBOX_FOR_DTRACE_LIB
3832	/**
3833	* Descriptor attributes (as seen by VT-x).
3834	*/
3835	typedef struct X86DESCATTRBITS
3836	{
3837	/** 00 - Segment Type. */
3838	unsigned u4Type : 4;
3839	/** 04 - Descriptor Type. System(=0) or code/data selector */
3840	unsigned u1DescType : 1;
3841	/** 05 - Descriptor Privilege level. */
3842	unsigned u2Dpl : 2;
3843	/** 07 - Flags selector present(=1) or not. */
3844	unsigned u1Present : 1;
3845	/** 08 - Segment limit 16-19. */
3846	unsigned u4LimitHigh : 4;
3847	/** 0c - Available for system software. */
3848	unsigned u1Available : 1;
3849	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3850	unsigned u1Long : 1;
3851	/** 0e - This flags meaning depends on the segment type. Try make sense out
3852	* of the intel manual yourself. */
3853	unsigned u1DefBig : 1;
3854	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3855	* clear byte. */
3856	unsigned u1Granularity : 1;
3857	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3858	unsigned u1Unusable : 1;
3859	} X86DESCATTRBITS;
3860	#endif /* !VBOX_FOR_DTRACE_LIB */
3861
3862	/** @name X86DESCATTR masks
3863	* @{ */
3864	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3865	#define X86DESCATTR_DT UINT32_C(0x00000010)
3866	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3867	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3868	#define X86DESCATTR_P UINT32_C(0x00000080)
3869	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3870	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3871	#define X86DESCATTR_L UINT32_C(0x00002000)
3872	#define X86DESCATTR_D UINT32_C(0x00004000)
3873	#define X86DESCATTR_G UINT32_C(0x00008000)
3874	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3875	/** @} */
3876
3877	#pragma pack(1)
3878	typedef union X86DESCATTR
3879	{
3880	/** Unsigned integer view. */
3881	uint32_t u;
3882	#ifndef VBOX_FOR_DTRACE_LIB
3883	/** Normal view. */
3884	X86DESCATTRBITS n;
3885	#endif
3886	} X86DESCATTR;
3887	#pragma pack()
3888	/** Pointer to descriptor attributes. */
3889	typedef X86DESCATTR *PX86DESCATTR;
3890	/** Pointer to const descriptor attributes. */
3891	typedef const X86DESCATTR *PCX86DESCATTR;
3892
3893	#ifndef VBOX_FOR_DTRACE_LIB
3894
3895	/**
3896	* Generic descriptor table entry
3897	*/
3898	#pragma pack(1)
3899	typedef struct X86DESCGENERIC
3900	{
3901	/** 00 - Limit - Low word. */
3902	unsigned u16LimitLow : 16;
3903	/** 10 - Base address - low word.
3904	* Don't try set this to 24 because MSC is doing stupid things then. */
3905	unsigned u16BaseLow : 16;
3906	/** 20 - Base address - first 8 bits of high word. */
3907	unsigned u8BaseHigh1 : 8;
3908	/** 28 - Segment Type. */
3909	unsigned u4Type : 4;
3910	/** 2c - Descriptor Type. System(=0) or code/data selector */
3911	unsigned u1DescType : 1;
3912	/** 2d - Descriptor Privilege level. */
3913	unsigned u2Dpl : 2;
3914	/** 2f - Flags selector present(=1) or not. */
3915	unsigned u1Present : 1;
3916	/** 30 - Segment limit 16-19. */
3917	unsigned u4LimitHigh : 4;
3918	/** 34 - Available for system software. */
3919	unsigned u1Available : 1;
3920	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3921	unsigned u1Long : 1;
3922	/** 36 - This flags meaning depends on the segment type. Try make sense out
3923	* of the intel manual yourself. */
3924	unsigned u1DefBig : 1;
3925	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3926	* clear byte. */
3927	unsigned u1Granularity : 1;
3928	/** 38 - Base address - highest 8 bits. */
3929	unsigned u8BaseHigh2 : 8;
3930	} X86DESCGENERIC;
3931	#pragma pack()
3932	/** Pointer to a generic descriptor entry. */
3933	typedef X86DESCGENERIC *PX86DESCGENERIC;
3934	/** Pointer to a const generic descriptor entry. */
3935	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3936
3937	/** @name Bit offsets of X86DESCGENERIC members.
3938	* @{*/
3939	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3940	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3941	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3942	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3943	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3944	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3945	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3946	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3947	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3948	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3949	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3950	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3951	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3952	/** @} */
3953
3954
3955	/** @name LAR mask
3956	* @{ */
3957	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3958	#define X86LAR_F_DT UINT16_C( 0x1000)
3959	#define X86LAR_F_DPL UINT16_C( 0x6000)
3960	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3961	#define X86LAR_F_P UINT16_C( 0x8000)
3962	#define X86LAR_F_AVL UINT32_C(0x00100000)
3963	#define X86LAR_F_L UINT32_C(0x00200000)
3964	#define X86LAR_F_D UINT32_C(0x00400000)
3965	#define X86LAR_F_G UINT32_C(0x00800000)
3966	/** @} */
3967
3968
3969	/**
3970	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3971	*/
3972	typedef struct X86DESCGATE
3973	{
3974	/** 00 - Target code segment offset - Low word.
3975	* Ignored if task-gate. */
3976	unsigned u16OffsetLow : 16;
3977	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3978	* TSS selector if task-gate. */
3979	unsigned u16Sel : 16;
3980	/** 20 - Number of parameters for a call-gate.
3981	* Ignored if interrupt-, trap- or task-gate. */
3982	unsigned u5ParmCount : 5;
3983	/** 25 - Reserved / ignored. */
3984	unsigned u3Reserved : 3;
3985	/** 28 - Segment Type. */
3986	unsigned u4Type : 4;
3987	/** 2c - Descriptor Type (0 = system). */
3988	unsigned u1DescType : 1;
3989	/** 2d - Descriptor Privilege level. */
3990	unsigned u2Dpl : 2;
3991	/** 2f - Flags selector present(=1) or not. */
3992	unsigned u1Present : 1;
3993	/** 30 - Target code segment offset - High word.
3994	* Ignored if task-gate. */
3995	unsigned u16OffsetHigh : 16;
3996	} X86DESCGATE;
3997	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3998	typedef X86DESCGATE *PX86DESCGATE;
3999	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4000	typedef const X86DESCGATE *PCX86DESCGATE;
4001
4002	#endif /* VBOX_FOR_DTRACE_LIB */
4003
4004	/**
4005	* Descriptor table entry.
4006	*/
4007	#pragma pack(1)
4008	typedef union X86DESC
4009	{
4010	#ifndef VBOX_FOR_DTRACE_LIB
4011	/** Generic descriptor view. */
4012	X86DESCGENERIC Gen;
4013	/** Gate descriptor view. */
4014	X86DESCGATE Gate;
4015	#endif
4016
4017	/** 8 bit unsigned integer view. */
4018	uint8_t au8[8];
4019	/** 16 bit unsigned integer view. */
4020	uint16_t au16[4];
4021	/** 32 bit unsigned integer view. */
4022	uint32_t au32[2];
4023	/** 64 bit unsigned integer view. */
4024	uint64_t au64[1];
4025	/** Unsigned integer view. */
4026	uint64_t u;
4027	} X86DESC;
4028	#ifndef VBOX_FOR_DTRACE_LIB
4029	AssertCompileSize(X86DESC, 8);
4030	#endif
4031	#pragma pack()
4032	/** Pointer to descriptor table entry. */
4033	typedef X86DESC *PX86DESC;
4034	/** Pointer to const descriptor table entry. */
4035	typedef const X86DESC *PCX86DESC;
4036
4037	/** @def X86DESC_BASE
4038	* Return the base address of a descriptor.
4039	*/
4040	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4041	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4042	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4043	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4044
4045	/** @def X86DESC_LIMIT
4046	* Return the limit of a descriptor.
4047	*/
4048	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4049	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4050	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4051
4052	/** @def X86DESC_LIMIT_G
4053	* Return the limit of a descriptor with the granularity bit taken into account.
4054	* @returns Selector limit (uint32_t).
4055	* @param a_pDesc Pointer to the descriptor.
4056	*/
4057	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4058	( (a_pDesc)->Gen.u1Granularity \
4059	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4060	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4061	)
4062
4063	/** @def X86DESC_GET_HID_ATTR
4064	* Get the descriptor attributes for the hidden register.
4065	*/
4066	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4067	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4068
4069	#ifndef VBOX_FOR_DTRACE_LIB
4070
4071	/**
4072	* 64 bits generic descriptor table entry
4073	* Note: most of these bits have no meaning in long mode.
4074	*/
4075	#pragma pack(1)
4076	typedef struct X86DESC64GENERIC
4077	{
4078	/** Limit - Low word - IGNORED. */
4079	uint32_t u16LimitLow : 16;
4080	/** Base address - low word. - IGNORED
4081	* Don't try set this to 24 because MSC is doing stupid things then. */
4082	uint32_t u16BaseLow : 16;
4083	/** Base address - first 8 bits of high word. - IGNORED */
4084	uint32_t u8BaseHigh1 : 8;
4085	/** Segment Type. */
4086	uint32_t u4Type : 4;
4087	/** Descriptor Type. System(=0) or code/data selector */
4088	uint32_t u1DescType : 1;
4089	/** Descriptor Privilege level. */
4090	uint32_t u2Dpl : 2;
4091	/** Flags selector present(=1) or not. */
4092	uint32_t u1Present : 1;
4093	/** Segment limit 16-19. - IGNORED */
4094	uint32_t u4LimitHigh : 4;
4095	/** Available for system software. - IGNORED */
4096	uint32_t u1Available : 1;
4097	/** Long mode flag. */
4098	uint32_t u1Long : 1;
4099	/** This flags meaning depends on the segment type. Try make sense out
4100	* of the intel manual yourself. */
4101	uint32_t u1DefBig : 1;
4102	/** Granularity of the limit. If set 4KB granularity is used, if
4103	* clear byte. - IGNORED */
4104	uint32_t u1Granularity : 1;
4105	/** Base address - highest 8 bits. - IGNORED */
4106	uint32_t u8BaseHigh2 : 8;
4107	/** Base address - bits 63-32. */
4108	uint32_t u32BaseHigh3 : 32;
4109	uint32_t u8Reserved : 8;
4110	uint32_t u5Zeros : 5;
4111	uint32_t u19Reserved : 19;
4112	} X86DESC64GENERIC;
4113	#pragma pack()
4114	/** Pointer to a generic descriptor entry. */
4115	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4116	/** Pointer to a const generic descriptor entry. */
4117	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4118
4119	/**
4120	* System descriptor table entry (64 bits)
4121	*
4122	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4123	*/
4124	#pragma pack(1)
4125	typedef struct X86DESC64SYSTEM
4126	{
4127	/** Limit - Low word. */
4128	uint32_t u16LimitLow : 16;
4129	/** Base address - low word.
4130	* Don't try set this to 24 because MSC is doing stupid things then. */
4131	uint32_t u16BaseLow : 16;
4132	/** Base address - first 8 bits of high word. */
4133	uint32_t u8BaseHigh1 : 8;
4134	/** Segment Type. */
4135	uint32_t u4Type : 4;
4136	/** Descriptor Type. System(=0) or code/data selector */
4137	uint32_t u1DescType : 1;
4138	/** Descriptor Privilege level. */
4139	uint32_t u2Dpl : 2;
4140	/** Flags selector present(=1) or not. */
4141	uint32_t u1Present : 1;
4142	/** Segment limit 16-19. */
4143	uint32_t u4LimitHigh : 4;
4144	/** Available for system software. */
4145	uint32_t u1Available : 1;
4146	/** Reserved - 0. */
4147	uint32_t u1Reserved : 1;
4148	/** This flags meaning depends on the segment type. Try make sense out
4149	* of the intel manual yourself. */
4150	uint32_t u1DefBig : 1;
4151	/** Granularity of the limit. If set 4KB granularity is used, if
4152	* clear byte. */
4153	uint32_t u1Granularity : 1;
4154	/** Base address - bits 31-24. */
4155	uint32_t u8BaseHigh2 : 8;
4156	/** Base address - bits 63-32. */
4157	uint32_t u32BaseHigh3 : 32;
4158	uint32_t u8Reserved : 8;
4159	uint32_t u5Zeros : 5;
4160	uint32_t u19Reserved : 19;
4161	} X86DESC64SYSTEM;
4162	#pragma pack()
4163	/** Pointer to a system descriptor entry. */
4164	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4165	/** Pointer to a const system descriptor entry. */
4166	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4167
4168	/**
4169	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4170	*/
4171	typedef struct X86DESC64GATE
4172	{
4173	/** Target code segment offset - Low word. */
4174	uint32_t u16OffsetLow : 16;
4175	/** Target code segment selector. */
4176	uint32_t u16Sel : 16;
4177	/** Interrupt stack table for interrupt- and trap-gates.
4178	* Ignored by call-gates. */
4179	uint32_t u3IST : 3;
4180	/** Reserved / ignored. */
4181	uint32_t u5Reserved : 5;
4182	/** Segment Type. */
4183	uint32_t u4Type : 4;
4184	/** Descriptor Type (0 = system). */
4185	uint32_t u1DescType : 1;
4186	/** Descriptor Privilege level. */
4187	uint32_t u2Dpl : 2;
4188	/** Flags selector present(=1) or not. */
4189	uint32_t u1Present : 1;
4190	/** Target code segment offset - High word.
4191	* Ignored if task-gate. */
4192	uint32_t u16OffsetHigh : 16;
4193	/** Target code segment offset - Top dword.
4194	* Ignored if task-gate. */
4195	uint32_t u32OffsetTop : 32;
4196	/** Reserved / ignored / must be zero.
4197	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4198	uint32_t u32Reserved : 32;
4199	} X86DESC64GATE;
4200	AssertCompileSize(X86DESC64GATE, 16);
4201	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4202	typedef X86DESC64GATE *PX86DESC64GATE;
4203	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4204	typedef const X86DESC64GATE *PCX86DESC64GATE;
4205
4206	#endif /* VBOX_FOR_DTRACE_LIB */
4207
4208	/**
4209	* Descriptor table entry.
4210	*/
4211	#pragma pack(1)
4212	typedef union X86DESC64
4213	{
4214	#ifndef VBOX_FOR_DTRACE_LIB
4215	/** Generic descriptor view. */
4216	X86DESC64GENERIC Gen;
4217	/** System descriptor view. */
4218	X86DESC64SYSTEM System;
4219	/** Gate descriptor view. */
4220	X86DESC64GATE Gate;
4221	#endif
4222
4223	/** 8 bit unsigned integer view. */
4224	uint8_t au8[16];
4225	/** 16 bit unsigned integer view. */
4226	uint16_t au16[8];
4227	/** 32 bit unsigned integer view. */
4228	uint32_t au32[4];
4229	/** 64 bit unsigned integer view. */
4230	uint64_t au64[2];
4231	} X86DESC64;
4232	#ifndef VBOX_FOR_DTRACE_LIB
4233	AssertCompileSize(X86DESC64, 16);
4234	#endif
4235	#pragma pack()
4236	/** Pointer to descriptor table entry. */
4237	typedef X86DESC64 *PX86DESC64;
4238	/** Pointer to const descriptor table entry. */
4239	typedef const X86DESC64 *PCX86DESC64;
4240
4241	/** @def X86DESC64_BASE
4242	* Return the base of a 64-bit descriptor.
4243	*/
4244	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4245	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4246	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4247	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4248	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4249
4250
4251
4252	/** @name Host system descriptor table entry - Use with care!
4253	* @{ */
4254	/** Host system descriptor table entry. */
4255	#if HC_ARCH_BITS == 64
4256	typedef X86DESC64 X86DESCHC;
4257	#else
4258	typedef X86DESC X86DESCHC;
4259	#endif
4260	/** Pointer to a host system descriptor table entry. */
4261	#if HC_ARCH_BITS == 64
4262	typedef PX86DESC64 PX86DESCHC;
4263	#else
4264	typedef PX86DESC PX86DESCHC;
4265	#endif
4266	/** Pointer to a const host system descriptor table entry. */
4267	#if HC_ARCH_BITS == 64
4268	typedef PCX86DESC64 PCX86DESCHC;
4269	#else
4270	typedef PCX86DESC PCX86DESCHC;
4271	#endif
4272	/** @} */
4273
4274
4275	/** @name Selector Descriptor Types.
4276	* @{
4277	*/
4278
4279	/** @name Non-System Selector Types.
4280	* @{ */
4281	/** Code(=set)/Data(=clear) bit. */
4282	#define X86_SEL_TYPE_CODE 8
4283	/** Memory(=set)/System(=clear) bit. */
4284	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4285	/** Accessed bit. */
4286	#define X86_SEL_TYPE_ACCESSED 1
4287	/** Expand down bit (for data selectors only). */
4288	#define X86_SEL_TYPE_DOWN 4
4289	/** Conforming bit (for code selectors only). */
4290	#define X86_SEL_TYPE_CONF 4
4291	/** Write bit (for data selectors only). */
4292	#define X86_SEL_TYPE_WRITE 2
4293	/** Read bit (for code selectors only). */
4294	#define X86_SEL_TYPE_READ 2
4295	/** The bit number of the code segment read bit (relative to u4Type). */
4296	#define X86_SEL_TYPE_READ_BIT 1
4297
4298	/** Read only selector type. */
4299	#define X86_SEL_TYPE_RO 0
4300	/** Accessed read only selector type. */
4301	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4302	/** Read write selector type. */
4303	#define X86_SEL_TYPE_RW 2
4304	/** Accessed read write selector type. */
4305	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4306	/** Expand down read only selector type. */
4307	#define X86_SEL_TYPE_RO_DOWN 4
4308	/** Accessed expand down read only selector type. */
4309	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4310	/** Expand down read write selector type. */
4311	#define X86_SEL_TYPE_RW_DOWN 6
4312	/** Accessed expand down read write selector type. */
4313	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4314	/** Execute only selector type. */
4315	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4316	/** Accessed execute only selector type. */
4317	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4318	/** Execute and read selector type. */
4319	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4320	/** Accessed execute and read selector type. */
4321	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4322	/** Conforming execute only selector type. */
4323	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4324	/** Accessed Conforming execute only selector type. */
4325	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4326	/** Conforming execute and write selector type. */
4327	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4328	/** Accessed Conforming execute and write selector type. */
4329	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4330	/** @} */
4331
4332
4333	/** @name System Selector Types.
4334	* @{ */
4335	/** The TSS busy bit mask. */
4336	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4337
4338	/** Undefined system selector type. */
4339	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4340	/** 286 TSS selector. */
4341	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4342	/** LDT selector. */
4343	#define X86_SEL_TYPE_SYS_LDT 2
4344	/** 286 TSS selector - Busy. */
4345	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4346	/** 286 Callgate selector. */
4347	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4348	/** Taskgate selector. */
4349	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4350	/** 286 Interrupt gate selector. */
4351	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4352	/** 286 Trapgate selector. */
4353	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4354	/** Undefined system selector. */
4355	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4356	/** 386 TSS selector. */
4357	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4358	/** Undefined system selector. */
4359	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4360	/** 386 TSS selector - Busy. */
4361	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4362	/** 386 Callgate selector. */
4363	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4364	/** Undefined system selector. */
4365	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4366	/** 386 Interruptgate selector. */
4367	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4368	/** 386 Trapgate selector. */
4369	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4370	/** @} */
4371
4372	/** @name AMD64 System Selector Types.
4373	* @{ */
4374	/** LDT selector. */
4375	#define AMD64_SEL_TYPE_SYS_LDT 2
4376	/** TSS selector - Busy. */
4377	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4378	/** TSS selector - Busy. */
4379	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4380	/** Callgate selector. */
4381	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4382	/** Interruptgate selector. */
4383	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4384	/** Trapgate selector. */
4385	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4386	/** @} */
4387
4388	/** @} */
4389
4390
4391	/** @name Descriptor Table Entry Flag Masks.
4392	* These are for the 2nd 32-bit word of a descriptor.
4393	* @{ */
4394	/** Bits 8-11 - TYPE - Descriptor type mask. */
4395	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4396	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4397	#define X86_DESC_S RT_BIT_32(12)
4398	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4399	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4400	/** Bit 15 - P - Present. */
4401	#define X86_DESC_P RT_BIT_32(15)
4402	/** Bit 20 - AVL - Available for system software. */
4403	#define X86_DESC_AVL RT_BIT_32(20)
4404	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4405	#define X86_DESC_DB RT_BIT_32(22)
4406	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4407	* used, if clear byte. */
4408	#define X86_DESC_G RT_BIT_32(23)
4409	/** @} */
4410
4411	/** @} */
4412
4413
4414	/** @name Task Segments.
4415	* @{
4416	*/
4417
4418	/**
4419	* The minimum TSS descriptor limit for 286 tasks.
4420	*/
4421	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4422
4423	/**
4424	* The minimum TSS descriptor segment limit for 386 tasks.
4425	*/
4426	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4427
4428	/**
4429	* 16-bit Task Segment (TSS).
4430	*/
4431	#pragma pack(1)
4432	typedef struct X86TSS16
4433	{
4434	/** Back link to previous task. (static) */
4435	RTSEL selPrev;
4436	/** Ring-0 stack pointer. (static) */
4437	uint16_t sp0;
4438	/** Ring-0 stack segment. (static) */
4439	RTSEL ss0;
4440	/** Ring-1 stack pointer. (static) */
4441	uint16_t sp1;
4442	/** Ring-1 stack segment. (static) */
4443	RTSEL ss1;
4444	/** Ring-2 stack pointer. (static) */
4445	uint16_t sp2;
4446	/** Ring-2 stack segment. (static) */
4447	RTSEL ss2;
4448	/** IP before task switch. */
4449	uint16_t ip;
4450	/** FLAGS before task switch. */
4451	uint16_t flags;
4452	/** AX before task switch. */
4453	uint16_t ax;
4454	/** CX before task switch. */
4455	uint16_t cx;
4456	/** DX before task switch. */
4457	uint16_t dx;
4458	/** BX before task switch. */
4459	uint16_t bx;
4460	/** SP before task switch. */
4461	uint16_t sp;
4462	/** BP before task switch. */
4463	uint16_t bp;
4464	/** SI before task switch. */
4465	uint16_t si;
4466	/** DI before task switch. */
4467	uint16_t di;
4468	/** ES before task switch. */
4469	RTSEL es;
4470	/** CS before task switch. */
4471	RTSEL cs;
4472	/** SS before task switch. */
4473	RTSEL ss;
4474	/** DS before task switch. */
4475	RTSEL ds;
4476	/** LDTR before task switch. */
4477	RTSEL selLdt;
4478	} X86TSS16;
4479	#ifndef VBOX_FOR_DTRACE_LIB
4480	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4481	#endif
4482	#pragma pack()
4483	/** Pointer to a 16-bit task segment. */
4484	typedef X86TSS16 *PX86TSS16;
4485	/** Pointer to a const 16-bit task segment. */
4486	typedef const X86TSS16 *PCX86TSS16;
4487
4488
4489	/**
4490	* 32-bit Task Segment (TSS).
4491	*/
4492	#pragma pack(1)
4493	typedef struct X86TSS32
4494	{
4495	/** Back link to previous task. (static) */
4496	RTSEL selPrev;
4497	uint16_t padding1;
4498	/** Ring-0 stack pointer. (static) */
4499	uint32_t esp0;
4500	/** Ring-0 stack segment. (static) */
4501	RTSEL ss0;
4502	uint16_t padding_ss0;
4503	/** Ring-1 stack pointer. (static) */
4504	uint32_t esp1;
4505	/** Ring-1 stack segment. (static) */
4506	RTSEL ss1;
4507	uint16_t padding_ss1;
4508	/** Ring-2 stack pointer. (static) */
4509	uint32_t esp2;
4510	/** Ring-2 stack segment. (static) */
4511	RTSEL ss2;
4512	uint16_t padding_ss2;
4513	/** Page directory for the task. (static) */
4514	uint32_t cr3;
4515	/** EIP before task switch. */
4516	uint32_t eip;
4517	/** EFLAGS before task switch. */
4518	uint32_t eflags;
4519	/** EAX before task switch. */
4520	uint32_t eax;
4521	/** ECX before task switch. */
4522	uint32_t ecx;
4523	/** EDX before task switch. */
4524	uint32_t edx;
4525	/** EBX before task switch. */
4526	uint32_t ebx;
4527	/** ESP before task switch. */
4528	uint32_t esp;
4529	/** EBP before task switch. */
4530	uint32_t ebp;
4531	/** ESI before task switch. */
4532	uint32_t esi;
4533	/** EDI before task switch. */
4534	uint32_t edi;
4535	/** ES before task switch. */
4536	RTSEL es;
4537	uint16_t padding_es;
4538	/** CS before task switch. */
4539	RTSEL cs;
4540	uint16_t padding_cs;
4541	/** SS before task switch. */
4542	RTSEL ss;
4543	uint16_t padding_ss;
4544	/** DS before task switch. */
4545	RTSEL ds;
4546	uint16_t padding_ds;
4547	/** FS before task switch. */
4548	RTSEL fs;
4549	uint16_t padding_fs;
4550	/** GS before task switch. */
4551	RTSEL gs;
4552	uint16_t padding_gs;
4553	/** LDTR before task switch. */
4554	RTSEL selLdt;
4555	uint16_t padding_ldt;
4556	/** Debug trap flag */
4557	uint16_t fDebugTrap;
4558	/** Offset relative to the TSS of the start of the I/O Bitmap
4559	* and the end of the interrupt redirection bitmap. */
4560	uint16_t offIoBitmap;
4561	} X86TSS32;
4562	#pragma pack()
4563	/** Pointer to task segment. */
4564	typedef X86TSS32 *PX86TSS32;
4565	/** Pointer to const task segment. */
4566	typedef const X86TSS32 *PCX86TSS32;
4567	#ifndef VBOX_FOR_DTRACE_LIB
4568	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4569	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4570	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4571	#endif
4572
4573	/**
4574	* 64-bit Task segment.
4575	*/
4576	#pragma pack(1)
4577	typedef struct X86TSS64
4578	{
4579	/** Reserved. */
4580	uint32_t u32Reserved;
4581	/** Ring-0 stack pointer. (static) */
4582	uint64_t rsp0;
4583	/** Ring-1 stack pointer. (static) */
4584	uint64_t rsp1;
4585	/** Ring-2 stack pointer. (static) */
4586	uint64_t rsp2;
4587	/** Reserved. */
4588	uint32_t u32Reserved2[2];
4589	/* IST */
4590	uint64_t ist1;
4591	uint64_t ist2;
4592	uint64_t ist3;
4593	uint64_t ist4;
4594	uint64_t ist5;
4595	uint64_t ist6;
4596	uint64_t ist7;
4597	/* Reserved. */
4598	uint16_t u16Reserved[5];
4599	/** Offset relative to the TSS of the start of the I/O Bitmap
4600	* and the end of the interrupt redirection bitmap. */
4601	uint16_t offIoBitmap;
4602	} X86TSS64;
4603	#pragma pack()
4604	/** Pointer to a 64-bit task segment. */
4605	typedef X86TSS64 *PX86TSS64;
4606	/** Pointer to a const 64-bit task segment. */
4607	typedef const X86TSS64 *PCX86TSS64;
4608	#ifndef VBOX_FOR_DTRACE_LIB
4609	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4610	#endif
4611
4612	/** @} */
4613
4614
4615	/** @name Selectors.
4616	* @{
4617	*/
4618
4619	/**
4620	* The shift used to convert a selector from and to index an index (C).
4621	*/
4622	#define X86_SEL_SHIFT 3
4623
4624	/**
4625	* The mask used to mask off the table indicator and RPL of an selector.
4626	*/
4627	#define X86_SEL_MASK 0xfff8U
4628
4629	/**
4630	* The mask used to mask off the RPL of an selector.
4631	* This is suitable for checking for NULL selectors.
4632	*/
4633	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4634
4635	/**
4636	* The bit indicating that a selector is in the LDT and not in the GDT.
4637	*/
4638	#define X86_SEL_LDT 0x0004U
4639
4640	/**
4641	* The bit mask for getting the RPL of a selector.
4642	*/
4643	#define X86_SEL_RPL 0x0003U
4644
4645	/**
4646	* The mask covering both RPL and LDT.
4647	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4648	* checks.
4649	*/
4650	#define X86_SEL_RPL_LDT 0x0007U
4651
4652	/** @} */
4653
4654
4655	/**
4656	* x86 Exceptions/Faults/Traps.
4657	*/
4658	typedef enum X86XCPT
4659	{
4660	/** \#DE - Divide error. */
4661	X86_XCPT_DE = 0x00,
4662	/** \#DB - Debug event (single step, DRx, ..) */
4663	X86_XCPT_DB = 0x01,
4664	/** NMI - Non-Maskable Interrupt */
4665	X86_XCPT_NMI = 0x02,
4666	/** \#BP - Breakpoint (INT3). */
4667	X86_XCPT_BP = 0x03,
4668	/** \#OF - Overflow (INTO). */
4669	X86_XCPT_OF = 0x04,
4670	/** \#BR - Bound range exceeded (BOUND). */
4671	X86_XCPT_BR = 0x05,
4672	/** \#UD - Undefined opcode. */
4673	X86_XCPT_UD = 0x06,
4674	/** \#NM - Device not available (math coprocessor device). */
4675	X86_XCPT_NM = 0x07,
4676	/** \#DF - Double fault. */
4677	X86_XCPT_DF = 0x08,
4678	/** ??? - Coprocessor segment overrun (obsolete). */
4679	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4680	/** \#TS - Taskswitch (TSS). */
4681	X86_XCPT_TS = 0x0a,
4682	/** \#NP - Segment no present. */
4683	X86_XCPT_NP = 0x0b,
4684	/** \#SS - Stack segment fault. */
4685	X86_XCPT_SS = 0x0c,
4686	/** \#GP - General protection fault. */
4687	X86_XCPT_GP = 0x0d,
4688	/** \#PF - Page fault. */
4689	X86_XCPT_PF = 0x0e,
4690	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4691	/** \#MF - Math fault (FPU). */
4692	X86_XCPT_MF = 0x10,
4693	/** \#AC - Alignment check. */
4694	X86_XCPT_AC = 0x11,
4695	/** \#MC - Machine check. */
4696	X86_XCPT_MC = 0x12,
4697	/** \#XF - SIMD Floating-Point Exception. */
4698	X86_XCPT_XF = 0x13,
4699	/** \#VE - Virtualization Exception (Intel only). */
4700	X86_XCPT_VE = 0x14,
4701	/** \#CP - Control Protection Exception (Intel only). */
4702	X86_XCPT_CP = 0x15,
4703	/** \#VC - VMM Communication Exception (AMD only). */
4704	X86_XCPT_VC = 0x1d,
4705	/** \#SX - Security Exception (AMD only). */
4706	X86_XCPT_SX = 0x1e
4707	} X86XCPT;
4708	/** Pointer to a x86 exception code. */
4709	typedef X86XCPT *PX86XCPT;
4710	/** Pointer to a const x86 exception code. */
4711	typedef const X86XCPT *PCX86XCPT;
4712	/** The last valid (currently reserved) exception value. */
4713	#define X86_XCPT_LAST 0x1f
4714
4715
4716	/** @name Trap Error Codes
4717	* @{
4718	*/
4719	/** External indicator. */
4720	#define X86_TRAP_ERR_EXTERNAL 1
4721	/** IDT indicator. */
4722	#define X86_TRAP_ERR_IDT 2
4723	/** Descriptor table indicator - If set LDT, if clear GDT. */
4724	#define X86_TRAP_ERR_TI 4
4725	/** Mask for getting the selector. */
4726	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4727	/** Shift for getting the selector table index (C type index). */
4728	#define X86_TRAP_ERR_SEL_SHIFT 3
4729	/** @} */
4730
4731
4732	/** @name \#PF Trap Error Codes
4733	* @{
4734	*/
4735	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4736	#define X86_TRAP_PF_P RT_BIT_32(0)
4737	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4738	#define X86_TRAP_PF_RW RT_BIT_32(1)
4739	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4740	#define X86_TRAP_PF_US RT_BIT_32(2)
4741	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4742	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4743	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4744	#define X86_TRAP_PF_ID RT_BIT_32(4)
4745	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4746	#define X86_TRAP_PF_PK RT_BIT_32(5)
4747	/** @} */
4748
4749	#pragma pack(1)
4750	/**
4751	* 16-bit IDTR.
4752	*/
4753	typedef struct X86IDTR16
4754	{
4755	/** Offset. */
4756	uint16_t offSel;
4757	/** Selector. */
4758	uint16_t uSel;
4759	} X86IDTR16, *PX86IDTR16;
4760	#pragma pack()
4761
4762	#pragma pack(1)
4763	/**
4764	* 32-bit IDTR/GDTR.
4765	*/
4766	typedef struct X86XDTR32
4767	{
4768	/** Size of the descriptor table. */
4769	uint16_t cb;
4770	/** Address of the descriptor table. */
4771	#ifndef VBOX_FOR_DTRACE_LIB
4772	uint32_t uAddr;
4773	#else
4774	uint16_t au16Addr[2];
4775	#endif
4776	} X86XDTR32, *PX86XDTR32;
4777	#pragma pack()
4778
4779	#pragma pack(1)
4780	/**
4781	* 64-bit IDTR/GDTR.
4782	*/
4783	typedef struct X86XDTR64
4784	{
4785	/** Size of the descriptor table. */
4786	uint16_t cb;
4787	/** Address of the descriptor table. */
4788	#ifndef VBOX_FOR_DTRACE_LIB
4789	uint64_t uAddr;
4790	#else
4791	uint16_t au16Addr[4];
4792	#endif
4793	} X86XDTR64, *PX86XDTR64;
4794	#pragma pack()
4795
4796
4797	/** @name ModR/M
4798	* @{ */
4799	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4800	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4801	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4802	#define X86_MODRM_REG_SHIFT 3
4803	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4804	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4805	#define X86_MODRM_MOD_SHIFT 6
4806	#ifndef VBOX_FOR_DTRACE_LIB
4807	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4808	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4809	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4810	/** @def X86_MODRM_MAKE
4811	* @param a_Mod The mod value (0..3).
4812	* @param a_Reg The register value (0..7).
4813	* @param a_RegMem The register or memory value (0..7). */
4814	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4815	#endif
4816	/** @} */
4817
4818	/** @name SIB
4819	* @{ */
4820	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4821	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4822	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4823	#define X86_SIB_INDEX_SHIFT 3
4824	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4825	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4826	#define X86_SIB_SCALE_SHIFT 6
4827	#ifndef VBOX_FOR_DTRACE_LIB
4828	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4829	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4830	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4831	#endif
4832	/** @} */
4833
4834	/** @name General register indexes.
4835	* @{ */
4836	#define X86_GREG_xAX 0
4837	#define X86_GREG_xCX 1
4838	#define X86_GREG_xDX 2
4839	#define X86_GREG_xBX 3
4840	#define X86_GREG_xSP 4
4841	#define X86_GREG_xBP 5
4842	#define X86_GREG_xSI 6
4843	#define X86_GREG_xDI 7
4844	#define X86_GREG_x8 8
4845	#define X86_GREG_x9 9
4846	#define X86_GREG_x10 10
4847	#define X86_GREG_x11 11
4848	#define X86_GREG_x12 12
4849	#define X86_GREG_x13 13
4850	#define X86_GREG_x14 14
4851	#define X86_GREG_x15 15
4852	/** @} */
4853	/** General register count. */
4854	#define X86_GREG_COUNT 16
4855
4856	/** @name X86_SREG_XXX - Segment register indexes.
4857	* @{ */
4858	#define X86_SREG_ES 0
4859	#define X86_SREG_CS 1
4860	#define X86_SREG_SS 2
4861	#define X86_SREG_DS 3
4862	#define X86_SREG_FS 4
4863	#define X86_SREG_GS 5
4864	/** @} */
4865	/** Segment register count. */
4866	#define X86_SREG_COUNT 6
4867
4868
4869	/** @name X86_OP_XXX - Prefixes
4870	* @{ */
4871	#define X86_OP_PRF_CS UINT8_C(0x2e)
4872	#define X86_OP_PRF_SS UINT8_C(0x36)
4873	#define X86_OP_PRF_DS UINT8_C(0x3e)
4874	#define X86_OP_PRF_ES UINT8_C(0x26)
4875	#define X86_OP_PRF_FS UINT8_C(0x64)
4876	#define X86_OP_PRF_GS UINT8_C(0x65)
4877	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4878	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4879	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4880	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4881	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4882	#define X86_OP_REX_B UINT8_C(0x41)
4883	#define X86_OP_REX_X UINT8_C(0x42)
4884	#define X86_OP_REX_R UINT8_C(0x44)
4885	#define X86_OP_REX_W UINT8_C(0x48)
4886	/** @} */
4887
4888
4889	/** @} */
4890
4891	#endif /* !IPRT_INCLUDED_x86_h */
4892

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