x86.h

最後變更在這個檔案是 107854,由 vboxsync 提交於 8 週前
x86.h,VMM: More AMD CPUID bits; addressed some old todos related to these; fixed bugs in svn & vmx world switcher (sanity checks, ++). jiraref:VBP-947 bugref:10738
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 211.8 KB

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.alldomusa.eu.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# ifndef __ASSEMBLER__
46	# include <iprt/types.h>
47	# include <iprt/assert.h>
48	# else
49	# include <iprt/stdint.h>
50	# include <iprt/assertcompile.h>
51	# endif
52	#else
53	# pragma D depends_on library vbox-types.d
54	#endif
55
56	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58	#ifdef RT_OS_SOLARIS
59	# undef CS
60	# undef DS
61	# undef MSR_IA32_FLUSH_CMD
62	# undef MSR_AMD_VIRT_SPEC_CTL
63	#endif
64
65	/** @defgroup grp_rt_x86 x86 Types and Definitions
66	* @ingroup grp_rt
67	* @{
68	*/
69
70	#ifndef __ASSEMBLER__
71
72	# ifndef VBOX_FOR_DTRACE_LIB
73	/**
74	* EFLAGS Bits.
75	*/
76	typedef struct X86EFLAGSBITS
77	{
78	/** Bit 0 - CF - Carry flag - Status flag. */
79	unsigned u1CF : 1;
80	/** Bit 1 - 1 - Reserved flag. */
81	unsigned u1Reserved0 : 1;
82	/** Bit 2 - PF - Parity flag - Status flag. */
83	unsigned u1PF : 1;
84	/** Bit 3 - 0 - Reserved flag. */
85	unsigned u1Reserved1 : 1;
86	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87	unsigned u1AF : 1;
88	/** Bit 5 - 0 - Reserved flag. */
89	unsigned u1Reserved2 : 1;
90	/** Bit 6 - ZF - Zero flag - Status flag. */
91	unsigned u1ZF : 1;
92	/** Bit 7 - SF - Signed flag - Status flag. */
93	unsigned u1SF : 1;
94	/** Bit 8 - TF - Trap flag - System flag. */
95	unsigned u1TF : 1;
96	/** Bit 9 - IF - Interrupt flag - System flag. */
97	unsigned u1IF : 1;
98	/** Bit 10 - DF - Direction flag - Control flag. */
99	unsigned u1DF : 1;
100	/** Bit 11 - OF - Overflow flag - Status flag. */
101	unsigned u1OF : 1;
102	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103	unsigned u2IOPL : 2;
104	/** Bit 14 - NT - Nested task flag - System flag. */
105	unsigned u1NT : 1;
106	/** Bit 15 - 0 - Reserved flag. */
107	unsigned u1Reserved3 : 1;
108	/** Bit 16 - RF - Resume flag - System flag. */
109	unsigned u1RF : 1;
110	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
111	unsigned u1VM : 1;
112	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113	unsigned u1AC : 1;
114	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115	unsigned u1VIF : 1;
116	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117	unsigned u1VIP : 1;
118	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119	unsigned u1ID : 1;
120	/** Bit 22-31 - 0 - Reserved flag. */
121	unsigned u10Reserved4 : 10;
122	} X86EFLAGSBITS;
123	/** Pointer to EFLAGS bits. */
124	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125	/** Pointer to const EFLAGS bits. */
126	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127	# endif /* !VBOX_FOR_DTRACE_LIB */
128
129	/**
130	* EFLAGS.
131	*/
132	typedef union X86EFLAGS
133	{
134	/** The plain unsigned view. */
135	uint32_t u;
136	# ifndef VBOX_FOR_DTRACE_LIB
137	/** The bitfield view. */
138	X86EFLAGSBITS Bits;
139	# endif
140	/** The 8-bit view. */
141	uint8_t au8[4];
142	/** The 16-bit view. */
143	uint16_t au16[2];
144	/** The 32-bit view. */
145	uint32_t au32[1];
146	/** The 32-bit view. */
147	uint32_t u32;
148	} X86EFLAGS;
149	/** Pointer to EFLAGS. */
150	typedef X86EFLAGS *PX86EFLAGS;
151	/** Pointer to const EFLAGS. */
152	typedef const X86EFLAGS *PCX86EFLAGS;
153
154	/**
155	* RFLAGS (32 upper bits are reserved).
156	*/
157	typedef union X86RFLAGS
158	{
159	/** The plain unsigned view. */
160	uint64_t u;
161	# ifndef VBOX_FOR_DTRACE_LIB
162	/** The bitfield view. */
163	X86EFLAGSBITS Bits;
164	# endif
165	/** The 8-bit view. */
166	uint8_t au8[8];
167	/** The 16-bit view. */
168	uint16_t au16[4];
169	/** The 32-bit view. */
170	uint32_t au32[2];
171	/** The 64-bit view. */
172	uint64_t au64[1];
173	/** The 64-bit view. */
174	uint64_t u64;
175	} X86RFLAGS;
176	/** Pointer to RFLAGS. */
177	typedef X86RFLAGS *PX86RFLAGS;
178	/** Pointer to const RFLAGS. */
179	typedef const X86RFLAGS *PCX86RFLAGS;
180
181	#endif /* !__ASSEMBLER__ */
182
183
184	/** @name EFLAGS
185	* @{
186	*/
187	/** Bit 0 - CF - Carry flag - Status flag. */
188	#define X86_EFL_CF RT_BIT_32(0)
189	#define X86_EFL_CF_BIT 0
190	/** Bit 1 - Reserved, reads as 1. */
191	#define X86_EFL_1 RT_BIT_32(1)
192	#define X86_EFL_1_BIT 1
193	/** Bit 2 - PF - Parity flag - Status flag. */
194	#define X86_EFL_PF RT_BIT_32(2)
195	#define X86_EFL_PF_BIT 2
196	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
197	#define X86_EFL_AF RT_BIT_32(4)
198	#define X86_EFL_AF_BIT 4
199	/** Bit 6 - ZF - Zero flag - Status flag. */
200	#define X86_EFL_ZF RT_BIT_32(6)
201	#define X86_EFL_ZF_BIT 6
202	/** Bit 7 - SF - Signed flag - Status flag. */
203	#define X86_EFL_SF RT_BIT_32(7)
204	#define X86_EFL_SF_BIT 7
205	/** Bit 8 - TF - Trap flag - System flag. */
206	#define X86_EFL_TF RT_BIT_32(8)
207	#define X86_EFL_TF_BIT 8
208	/** Bit 9 - IF - Interrupt flag - System flag. */
209	#define X86_EFL_IF RT_BIT_32(9)
210	#define X86_EFL_IF_BIT 9
211	/** Bit 10 - DF - Direction flag - Control flag. */
212	#define X86_EFL_DF RT_BIT_32(10)
213	#define X86_EFL_DF_BIT 10
214	/** Bit 11 - OF - Overflow flag - Status flag. */
215	#define X86_EFL_OF RT_BIT_32(11)
216	#define X86_EFL_OF_BIT 11
217	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
218	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
219	/** Bit 14 - NT - Nested task flag - System flag. */
220	#define X86_EFL_NT RT_BIT_32(14)
221	#define X86_EFL_NT_BIT 14
222	/** Bit 16 - RF - Resume flag - System flag. */
223	#define X86_EFL_RF RT_BIT_32(16)
224	#define X86_EFL_RF_BIT 16
225	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
226	#define X86_EFL_VM RT_BIT_32(17)
227	#define X86_EFL_VM_BIT 17
228	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
229	#define X86_EFL_AC RT_BIT_32(18)
230	#define X86_EFL_AC_BIT 18
231	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
232	#define X86_EFL_VIF RT_BIT_32(19)
233	#define X86_EFL_VIF_BIT 19
234	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
235	#define X86_EFL_VIP RT_BIT_32(20)
236	#define X86_EFL_VIP_BIT 20
237	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
238	#define X86_EFL_ID RT_BIT_32(21)
239	#define X86_EFL_ID_BIT 21
240	/** All live bits. */
241	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
242	/** Read as 1 bits. */
243	#define X86_EFL_RA1_MASK RT_BIT_32(1)
244	/** Read as 0 bits, excluding bits 31:22.
245	* Bits 3, 5, 15, and 22 thru 31. */
246	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
247	/** Read as 0 bits, excluding bits 31:22.
248	* Bits 3, 5 and 15. */
249	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
250	/** IOPL shift. */
251	#define X86_EFL_IOPL_SHIFT 12
252	/** The IOPL level from the flags. */
253	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
254	/** Bits restored by popf */
255	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
256	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
257	/** Bits restored by popf */
258	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
259	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
260	/** The status bits commonly updated by arithmetic instructions. */
261	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
262	/** @} */
263
264
265	#ifndef __ASSEMBLER__
266
267	/** CPUID Feature information - ECX.
268	* CPUID query with EAX=1.
269	*/
270	# ifndef VBOX_FOR_DTRACE_LIB
271	typedef struct X86CPUIDFEATECX
272	{
273	/** Bit 0 - SSE3 - Supports SSE3 or not. */
274	unsigned u1SSE3 : 1;
275	/** Bit 1 - PCLMULQDQ. */
276	unsigned u1PCLMULQDQ : 1;
277	/** Bit 2 - DS Area 64-bit layout. */
278	unsigned u1DTE64 : 1;
279	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
280	unsigned u1Monitor : 1;
281	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
282	unsigned u1CPLDS : 1;
283	/** Bit 5 - VMX - Virtual Machine Technology. */
284	unsigned u1VMX : 1;
285	/** Bit 6 - SMX: Safer Mode Extensions. */
286	unsigned u1SMX : 1;
287	/** Bit 7 - EST - Enh. SpeedStep Tech. */
288	unsigned u1EST : 1;
289	/** Bit 8 - TM2 - Terminal Monitor 2. */
290	unsigned u1TM2 : 1;
291	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
292	unsigned u1SSSE3 : 1;
293	/** Bit 10 - CNTX-ID - L1 Context ID. */
294	unsigned u1CNTXID : 1;
295	/** Bit 11 - Reserved. */
296	unsigned u1Reserved1 : 1;
297	/** Bit 12 - FMA. */
298	unsigned u1FMA : 1;
299	/** Bit 13 - CX16 - CMPXCHG16B. */
300	unsigned u1CX16 : 1;
301	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
302	unsigned u1TPRUpdate : 1;
303	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
304	unsigned u1PDCM : 1;
305	/** Bit 16 - Reserved. */
306	unsigned u1Reserved2 : 1;
307	/** Bit 17 - PCID - Process-context identifiers. */
308	unsigned u1PCID : 1;
309	/** Bit 18 - Direct Cache Access. */
310	unsigned u1DCA : 1;
311	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
312	unsigned u1SSE4_1 : 1;
313	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
314	unsigned u1SSE4_2 : 1;
315	/** Bit 21 - x2APIC. */
316	unsigned u1x2APIC : 1;
317	/** Bit 22 - MOVBE - Supports MOVBE. */
318	unsigned u1MOVBE : 1;
319	/** Bit 23 - POPCNT - Supports POPCNT. */
320	unsigned u1POPCNT : 1;
321	/** Bit 24 - TSC-Deadline. */
322	unsigned u1TSCDEADLINE : 1;
323	/** Bit 25 - AES. */
324	unsigned u1AES : 1;
325	/** Bit 26 - XSAVE - Supports XSAVE. */
326	unsigned u1XSAVE : 1;
327	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
328	unsigned u1OSXSAVE : 1;
329	/** Bit 28 - AVX - Supports AVX instruction extensions. */
330	unsigned u1AVX : 1;
331	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
332	unsigned u1F16C : 1;
333	/** Bit 30 - RDRAND - Supports RDRAND. */
334	unsigned u1RDRAND : 1;
335	/** Bit 31 - Hypervisor present (we're a guest). */
336	unsigned u1HVP : 1;
337	} X86CPUIDFEATECX;
338	# else /* VBOX_FOR_DTRACE_LIB */
339	typedef uint32_t X86CPUIDFEATECX;
340	# endif /* VBOX_FOR_DTRACE_LIB */
341	/** Pointer to CPUID Feature Information - ECX. */
342	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
343	/** Pointer to const CPUID Feature Information - ECX. */
344	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
345
346
347	/** CPUID Feature Information - EDX.
348	* CPUID query with EAX=1.
349	*/
350	# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
351	typedef struct X86CPUIDFEATEDX
352	{
353	/** Bit 0 - FPU - x87 FPU on Chip. */
354	unsigned u1FPU : 1;
355	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
356	unsigned u1VME : 1;
357	/** Bit 2 - DE - Debugging extensions. */
358	unsigned u1DE : 1;
359	/** Bit 3 - PSE - Page Size Extension. */
360	unsigned u1PSE : 1;
361	/** Bit 4 - TSC - Time Stamp Counter. */
362	unsigned u1TSC : 1;
363	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
364	unsigned u1MSR : 1;
365	/** Bit 6 - PAE - Physical Address Extension. */
366	unsigned u1PAE : 1;
367	/** Bit 7 - MCE - Machine Check Exception. */
368	unsigned u1MCE : 1;
369	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
370	unsigned u1CX8 : 1;
371	/** Bit 9 - APIC - APIC On-Chip. */
372	unsigned u1APIC : 1;
373	/** Bit 10 - Reserved. */
374	unsigned u1Reserved1 : 1;
375	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
376	unsigned u1SEP : 1;
377	/** Bit 12 - MTRR - Memory Type Range Registers. */
378	unsigned u1MTRR : 1;
379	/** Bit 13 - PGE - PTE Global Bit. */
380	unsigned u1PGE : 1;
381	/** Bit 14 - MCA - Machine Check Architecture. */
382	unsigned u1MCA : 1;
383	/** Bit 15 - CMOV - Conditional Move Instructions. */
384	unsigned u1CMOV : 1;
385	/** Bit 16 - PAT - Page Attribute Table. */
386	unsigned u1PAT : 1;
387	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
388	unsigned u1PSE36 : 1;
389	/** Bit 18 - PSN - Processor Serial Number. */
390	unsigned u1PSN : 1;
391	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
392	unsigned u1CLFSH : 1;
393	/** Bit 20 - Reserved. */
394	unsigned u1Reserved2 : 1;
395	/** Bit 21 - DS - Debug Store. */
396	unsigned u1DS : 1;
397	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
398	unsigned u1ACPI : 1;
399	/** Bit 23 - MMX - Intel MMX 'Technology'. */
400	unsigned u1MMX : 1;
401	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
402	unsigned u1FXSR : 1;
403	/** Bit 25 - SSE - SSE Support. */
404	unsigned u1SSE : 1;
405	/** Bit 26 - SSE2 - SSE2 Support. */
406	unsigned u1SSE2 : 1;
407	/** Bit 27 - SS - Self Snoop. */
408	unsigned u1SS : 1;
409	/** Bit 28 - HTT - Hyper-Threading Technology. */
410	unsigned u1HTT : 1;
411	/** Bit 29 - TM - Thermal Monitor. */
412	unsigned u1TM : 1;
413	/** Bit 30 - Reserved - . */
414	unsigned u1Reserved3 : 1;
415	/** Bit 31 - PBE - Pending Break Enabled. */
416	unsigned u1PBE : 1;
417	} X86CPUIDFEATEDX;
418	# else /* VBOX_FOR_DTRACE_LIB */
419	typedef uint32_t X86CPUIDFEATEDX;
420	# endif /* VBOX_FOR_DTRACE_LIB */
421	/** Pointer to CPUID Feature Information - EDX. */
422	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
423	/** Pointer to const CPUID Feature Information - EDX. */
424	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
425
426	#endif /* !__ASSEMBLER__ */
427
428
429	/** @name CPUID Vendor information.
430	* CPUID query with EAX=0.
431	* @{
432	*/
433	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
434	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
435	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
436
437	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
438	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
439	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
440
441	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
442	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
443	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
444
445	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
446	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
447	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
448
449	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
450	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
451	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
452	/** @} */
453
454
455	/** @name CPUID Feature information.
456	* CPUID query with EAX=1.
457	* @{
458	*/
459	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
460	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
461	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
462	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
463	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
464	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
465	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
466	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
467	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
468	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
469	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
470	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
471	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
472	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
473	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
474	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
475	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
476	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
477	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
478	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
479	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
480	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
481	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
482	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
483	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
484	/** ECX Bit 12 - FMA. */
485	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
486	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
487	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
488	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
489	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
490	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
491	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
492	/** ECX Bit 17 - PCID - Process-context identifiers. */
493	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
494	/** ECX Bit 18 - DCA - Direct Cache Access. */
495	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
496	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
497	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
498	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
499	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
500	/** ECX Bit 21 - x2APIC support. */
501	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
502	/** ECX Bit 22 - MOVBE instruction. */
503	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
504	/** ECX Bit 23 - POPCNT instruction. */
505	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
506	/** ECX Bir 24 - TSC-Deadline. */
507	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
508	/** ECX Bit 25 - AES instructions. */
509	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
510	/** ECX Bit 26 - XSAVE instruction. */
511	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
512	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
513	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
514	/** ECX Bit 28 - AVX. */
515	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
516	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
517	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
518	/** ECX Bit 30 - RDRAND instruction. */
519	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
520	/** ECX Bit 31 - Hypervisor Present (software only). */
521	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
522
523
524	/** Bit 0 - FPU - x87 FPU on Chip. */
525	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
526	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
527	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
528	/** Bit 2 - DE - Debugging extensions. */
529	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
530	/** Bit 3 - PSE - Page Size Extension. */
531	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
532	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
533	/** Bit 4 - TSC - Time Stamp Counter. */
534	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
535	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
536	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
537	/** Bit 6 - PAE - Physical Address Extension. */
538	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
539	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
540	/** Bit 7 - MCE - Machine Check Exception. */
541	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
542	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
543	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
544	/** Bit 9 - APIC - APIC On-Chip. */
545	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
546	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
547	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
548	/** Bit 12 - MTRR - Memory Type Range Registers. */
549	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
550	/** Bit 13 - PGE - PTE Global Bit. */
551	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
552	/** Bit 14 - MCA - Machine Check Architecture. */
553	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
554	/** Bit 15 - CMOV - Conditional Move Instructions. */
555	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
556	/** Bit 16 - PAT - Page Attribute Table. */
557	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
558	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
559	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
560	/** Bit 18 - PSN - Processor Serial Number. */
561	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
562	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
563	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
564	/** Bit 21 - DS - Debug Store. */
565	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
566	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
567	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
568	/** Bit 23 - MMX - Intel MMX Technology. */
569	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
570	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
571	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
572	/** Bit 25 - SSE - SSE Support. */
573	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
574	/** Bit 26 - SSE2 - SSE2 Support. */
575	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
576	/** Bit 27 - SS - Self Snoop. */
577	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
578	/** Bit 28 - HTT - Hyper-Threading Technology. */
579	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
580	/** Bit 29 - TM - Therm. Monitor. */
581	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
582	/** Bit 31 - PBE - Pending Break Enabled. */
583	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
584	/** @} */
585
586	/** @name CPUID mwait/monitor information.
587	* CPUID query with EAX=5.
588	* @{
589	*/
590	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
591	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
592	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
593	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
594	/** @} */
595
596
597	/** @name CPUID Thermal and Power Management information.
598	* Generally Intel only unless noted otherwise.
599	* CPUID query with EAX=5. @{
600	*/
601	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
602	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
603	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
604	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
605	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
606	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
607	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
608	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
609	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
610	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
611	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
612	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
613	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
614	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
615	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
616	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
617	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
618	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
619	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
620	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
621	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
622	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
623	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
624	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
625	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
626	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
627	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
628	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
629	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
630	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
631	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
632	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
633
634	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
635	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
636	/** @} */
637
638
639	/** @name CPUID Structured Extended Feature information, \#0.
640	* CPUID query with EAX=7 and ECX=0.
641	* @{
642	*/
643	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
644	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
645	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
646	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
647	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
648	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
649	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
650	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
651	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
652	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
653	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
654	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
655	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
656	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
657	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
658	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
659	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
660	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
661	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
662	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
663	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
664	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
665	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
666	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
667	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
668	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
669	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
670	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
671	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
672	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
673	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
674	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
675	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
676	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
677	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
678	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
679	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
680	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
681	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
682	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
683	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
684	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
685	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
686	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
687	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
688	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
689	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
690	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
691	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
692	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
693	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
694	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
695
696	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
697	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
698	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
699	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
700	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
701	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
702	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
703	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
704	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
705	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
706	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
707	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
708	/** ECX Bit 22 - RDPID - Support pread process ID. */
709	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
710	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
711	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
712
713	/** EDX bit 9 - SRBDS_CTRL - (Special Register Buffer Data Sample Control)
714	* Supports IA32_MCU_OPT_CTRL and IA32_MCU_OPT_CTRL.RNGDS_MITG_DIS. */
715	#define X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL RT_BIT_32(9)
716	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
717	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
718	/** EDX Bit 11 - TSX_FORCE_ABORT - Supports for IA32_TSX_FORCE_ABORT MSR. */
719	#define X86_CPUID_STEXT_FEATURE_EDX_TSX_FORCE_ABORT RT_BIT_32(11)
720	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
721	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
722	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
723	* IBPB command in IA32_PRED_CMD. */
724	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
725	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
726	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
727	/** EDX Bit 28 - FLUSH_CMD - Supports the IA32_FLUSH_CMD.L1D_FLUSH command. */
728	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
729	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
730	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
731	/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
732	#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
733	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
734	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
735	/** @} */
736
737	/** @name CPUID Structured Extended Feature information, \#2.
738	* CPUID query with EAX=7 and ECX=2.
739	* @{
740	*/
741	/** EDX Bit 0 - PSFD - IA32_SPEC_CTRL[7] (PSFD) supported. */
742	#define X86_CPUID_STEXT_FEATURE_2_EDX_PSFD RT_BIT_32(0)
743	/** EDX Bit 1 - IPRED_CTRL - IA32_SPEC_CTRL[4:3] (IPRED_DIS_S/U) supported. */
744	#define X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL RT_BIT_32(1)
745	/** EDX Bit 2 - RRSBA_CTRL - IA32_SPEC_CTRL[6:5] (RRSBA_DIS_S/U) supported. */
746	#define X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL RT_BIT_32(2)
747	/** EDX Bit 3 - DDPD_U - IA32_SPEC_CTRL[8] (DDPD_U) supported. */
748	#define X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U RT_BIT_32(3)
749	/** EDX Bit 4 - BHI_CTRL - IA32_SPEC_CTRL[10] (BHI_DIS_S) supported. */
750	#define X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL RT_BIT_32(4)
751	/** EDX Bit 5 - MCDT_NO - No MXCSR Configuration Dependent Timing issues. */
752	#define X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO RT_BIT_32(5)
753	/** EDX Bit 6 - UC_LOCK_DIS - Supports UC-lock disable and causing \#AC. */
754	#define X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS RT_BIT_32(6)
755	/** EDX Bit 7 - MONITOR_MITG_NO - No need for MONITOR/UMONITOR power mitigrations. */
756	#define X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO RT_BIT_32(7)
757	/** @} */
758
759
760	/** @name CPUID Extended Feature information.
761	* CPUID query with EAX=0x80000001.
762	* @{
763	*/
764	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
765	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
766
767	/** EDX Bit 11 - SYSCALL/SYSRET. */
768	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
769	/** EDX Bit 20 - No-Execute/Execute-Disable. */
770	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
771	/** EDX Bit 26 - 1 GB large page. */
772	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
773	/** EDX Bit 27 - RDTSCP. */
774	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
775	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
776	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
777	/** @}*/
778
779	/** @name CPUID AMD Feature information.
780	* CPUID query with EAX=0x80000001.
781	* @{
782	*/
783	/** Bit 0 - FPU - x87 FPU on Chip. */
784	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
785	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
786	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
787	/** Bit 2 - DE - Debugging extensions. */
788	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
789	/** Bit 3 - PSE - Page Size Extension. */
790	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
791	/** Bit 4 - TSC - Time Stamp Counter. */
792	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
793	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
794	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
795	/** Bit 6 - PAE - Physical Address Extension. */
796	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
797	/** Bit 7 - MCE - Machine Check Exception. */
798	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
799	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
800	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
801	/** Bit 9 - APIC - APIC On-Chip. */
802	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
803	/** Bit 12 - MTRR - Memory Type Range Registers. */
804	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
805	/** Bit 13 - PGE - PTE Global Bit. */
806	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
807	/** Bit 14 - MCA - Machine Check Architecture. */
808	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
809	/** Bit 15 - CMOV - Conditional Move Instructions. */
810	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
811	/** Bit 16 - PAT - Page Attribute Table. */
812	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
813	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
814	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
815	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
816	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
817	/** Bit 23 - MMX - Intel MMX Technology. */
818	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
819	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
820	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
821	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
822	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
823	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
824	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
825	/** Bit 31 - 3DNOW - AMD 3DNow. */
826	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
827
828	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
829	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
830	/** Bit 2 - SVM - AMD VM extensions. */
831	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
832	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
833	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
834	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
835	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
836	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
837	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
838	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
839	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
840	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
841	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
842	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
843	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
844	/** Bit 9 - OSVW - AMD OS visible workaround. */
845	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
846	/** Bit 10 - IBS - Instruct based sampling. */
847	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
848	/** Bit 11 - XOP - Extended operation support (see APM6). */
849	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
850	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
851	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
852	/** Bit 13 - WDT - AMD Watchdog timer support. */
853	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
854	/** Bit 15 - LWP - Lightweight profiling support. */
855	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
856	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
857	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
858	/** Bit 19 - NodeId - Indicates support for
859	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
860	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
861	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
862	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
863	/** Bit 22 - TopologyExtensions - . */
864	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
865	/** @} */
866
867
868	/** @name CPUID AMD Feature information.
869	* CPUID query with EAX=0x80000007.
870	* @{
871	*/
872	/** Bit 0 - TS - Temperature Sensor. */
873	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
874	/** Bit 1 - FID - Frequency ID Control. */
875	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
876	/** Bit 2 - VID - Voltage ID Control. */
877	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
878	/** Bit 3 - TTP - THERMTRIP. */
879	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
880	/** Bit 4 - TM - Hardware Thermal Control. */
881	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
882	/** Bit 5 - STC - Software Thermal Control. */
883	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
884	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
885	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
886	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
887	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
888	/** Bit 8 - TSCINVAR - TSC Invariant. */
889	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
890	/** Bit 9 - CPB - TSC Invariant. */
891	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
892	/** Bit 10 - EffFreqRO - MPERF/APERF. */
893	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
894	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
895	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
896	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
897	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
898	/** @} */
899
900
901	/** @name CPUID AMD extended feature extensions ID (EBX).
902	* CPUID query with EAX=0x80000008.
903	* @{
904	*/
905	/** Bit 0 - CLZERO - Clear zero instruction. */
906	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
907	/** Bit 1 - IRPerf - Instructions retired count support. */
908	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
909	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
910	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
911	/** Bit 3 - INVLPGB - Supports the INVLPGB instruction. */
912	#define X86_CPUID_AMD_EFEID_EBX_INVLPGB RT_BIT_32(3)
913	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
914	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
915	/** Bit 6 - BE - Has bandwidth enforcement extension. */
916	#define X86_CPUID_AMD_EFEID_EBX_BE RT_BIT_32(6)
917	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
918	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
919	/* AMD pipeline length: 9 feature bits ;-) */
920	/** Bit 12 - IBPB - Supports IA32_PRED_CMD.IBPB. */
921	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
922	/** Bit 13 - INT_WBINVD - WBINVD/WBNOINVD are interruptible. */
923	#define X86_CPUID_AMD_EFEID_EBX_INT_WBINVD RT_BIT_32(13)
924	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
925	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
926	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
927	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
928	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
929	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
930	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
931	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
932	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
933	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
934	/** Bit 19 - IBRS same mode - IBRS provides same mode speculation limits. */
935	#define X86_CPUID_AMD_EFEID_EBX_IBRS_SAME_MODE RT_BIT_32(19)
936	/** Bit 20 - EferLmsleUnsupported - The EFER.LMSLE bit is not supported. */
937	#define X86_CPUID_AMD_EFEID_EBX_NO_EFER_LMSLE RT_BIT_32(20)
938	/** Bit 21 - INVLPGBnestedPages - The INVLPGB instruction supports
939	* invalidating nested translations. */
940	#define X86_CPUID_AMD_EFEID_EBX_INVLPGB_NESTED_PAGES RT_BIT_32(21)
941	/** Bit 23 - PPIN - protected process inventory number. */
942	#define X86_CPUID_AMD_EFEID_EBX_PPIN RT_BIT_32(23)
943	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
944	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
945	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
946	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
947	/** Bit 26 - Speculative Store Bypass Disable not required. */
948	#define X86_CPUID_AMD_EFEID_EBX_SSBD_NOT_REQUIRED RT_BIT_32(26)
949	/** Bit 27 - CPPC - Supports collaborative processor performance control. */
950	#define X86_CPUID_AMD_EFEID_EBX_CPPC RT_BIT_32(27)
951	/** Bit 28 - PSFD - Supports IA32_SPEC_CTRL.PSFD (bit 7). */
952	#define X86_CPUID_AMD_EFEID_EBX_PSFD RT_BIT_32(28)
953	/** Bit 29 - BTC_NO - CPU not subject to branch type confusion. */
954	#define X86_CPUID_AMD_EFEID_EBX_BTC_NO RT_BIT_32(29)
955	/** Bit 30 - IBPB_RET - Supports returns type with IA32_PRED_CMD.IBPB? */
956	#define X86_CPUID_AMD_EFEID_EBX_IBPB_RET RT_BIT_32(30)
957	/** Bit 31 - BRS - Branch sampling. */
958	#define X86_CPUID_AMD_EFEID_EBX_BRS RT_BIT_32(31)
959	/** @} */
960
961
962	/** @name CPUID AMD SVM Feature information.
963	* CPUID query with EAX=0x8000000a.
964	* @{
965	*/
966	/** Bit 0 - NP - Nested Paging supported. */
967	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
968	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
969	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
970	/** Bit 2 - SVML - SVM locking bit supported. */
971	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
972	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
973	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
974	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
975	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
976	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
977	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
978	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
979	* VMCB.TLB_Control is supported. */
980	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
981	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
982	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
983	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
984	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
985	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
986	* intercept filter cycle count threshold. */
987	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
988	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
989	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
990	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
991	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
992	/** Bit 16 - VGIF - Supports virtualized GIF. */
993	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
994	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
995	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
996	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
997	* mode. */
998	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
999	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
1000	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
1001	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
1002	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
1003	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
1004	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
1005	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
1006	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
1007	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
1008	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
1009	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
1010	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
1011	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
1012	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
1013	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
1014	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
1015	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
1016	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
1017	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
1018	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
1019	/** @} */
1020
1021	/** @name CPUID AMD Fn8000_0021
1022	* CPUID query with EAX=0x80000021.
1023	* @{
1024	*/
1025	/** Bit 27 - SBPB - Supports IA32_PRED_CMD[7(SBPB)] - selective branch
1026	* predictor barrier. */
1027	#define X86_CPUID_AMD_21_EAX_SBPB RT_BIT(27)
1028	/** Bit 28 - IBPB_BRTYPE - IA32_PRED_CMD.IBPB flushes all branch types. */
1029	#define X86_CPUID_AMD_21_EAX_IBPB_BRTYPE RT_BIT(28)
1030	/** Bit 29 - SRSO_NO - CPU not affected by SRSO. */
1031	#define X86_CPUID_AMD_21_EAX_SRSO_NO RT_BIT(29)
1032	/** Bit 30 - SRSO_USER_KERNEL_NO - CPU not affected by SRSO crossing user/kernel
1033	* boundraries. */
1034	#define X86_CPUID_AMD_21_EAX_SRSO_USER_KERNEL_NO RT_BIT(30)
1035	/** Bit 31 - SRSO_MSR_FIX - Supports BP_CFG[BpSpecReduce(4)] for SRSO fixing. */
1036	#define X86_CPUID_AMD_21_EAX_SRSO_MSR_FIX RT_BIT(31)
1037
1038	/** @} */
1039
1040
1041
1042	/** @name CR0
1043	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
1044	* reserved flags.
1045	* @{ */
1046	/** Bit 0 - PE - Protection Enabled */
1047	#define X86_CR0_PE RT_BIT_32(0)
1048	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
1049	#define X86_CR0_PE_BIT 0
1050	/** Bit 1 - MP - Monitor Coprocessor */
1051	#define X86_CR0_MP RT_BIT_32(1)
1052	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
1053	#define X86_CR0_MP_BIT 1
1054	/** Bit 2 - EM - Emulation. */
1055	#define X86_CR0_EM RT_BIT_32(2)
1056	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
1057	#define X86_CR0_EM_BIT 2
1058	/** Bit 3 - TS - Task Switch. */
1059	#define X86_CR0_TS RT_BIT_32(3)
1060	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
1061	#define X86_CR0_TS_BIT 3
1062	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
1063	#define X86_CR0_ET RT_BIT_32(4)
1064	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
1065	#define X86_CR0_ET_BIT 4
1066	/** Bit 5 - NE - Numeric error (486+). */
1067	#define X86_CR0_NE RT_BIT_32(5)
1068	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
1069	#define X86_CR0_NE_BIT 5
1070	/** Bit 16 - WP - Write Protect (486+). */
1071	#define X86_CR0_WP RT_BIT_32(16)
1072	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
1073	#define X86_CR0_WP_BIT 16
1074	/** Bit 18 - AM - Alignment Mask (486+). */
1075	#define X86_CR0_AM RT_BIT_32(18)
1076	#define X86_CR0_ALIGNMENT_MASK RT_BIT_32(18)
1077	#define X86_CR0_AM_BIT 18
1078	/** Bit 29 - NW - Not Write-though (486+). */
1079	#define X86_CR0_NW RT_BIT_32(29)
1080	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1081	#define X86_CR0_NW_BIT 29
1082	/** Bit 30 - WP - Cache Disable (486+). */
1083	#define X86_CR0_CD RT_BIT_32(30)
1084	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1085	#define X86_CR0_CD_BIT 30
1086	/** Bit 31 - PG - Paging. */
1087	#define X86_CR0_PG RT_BIT_32(31)
1088	#define X86_CR0_PAGING RT_BIT_32(31)
1089	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
1090	/** @} */
1091
1092
1093	/** @name CR3
1094	* @{ */
1095	/** Bit 3 - PWT - Page-level Writes Transparent. */
1096	#define X86_CR3_PWT RT_BIT_32(3)
1097	#define X86_CR3_PWT_BIT 3
1098	/** Bit 4 - PCD - Page-level Cache Disable. */
1099	#define X86_CR3_PCD RT_BIT_32(4)
1100	#define X86_CR3_PCD_BIT 4
1101	/** Bits 12-31 - - Page directory page number. */
1102	#define X86_CR3_PAGE_MASK (0xfffff000)
1103	/** Bits 5-31 - - PAE Page directory page number. */
1104	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1105	/** Bits 12-51 - - AMD64 PML4 page number.
1106	* @note This is a maxed out mask, the actual acceptable CR3 value can
1107	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1108	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1109	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1110	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1111	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1112	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1113	/** @} */
1114
1115
1116	/** @name CR4
1117	* @{ */
1118	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1119	#define X86_CR4_VME RT_BIT_32(0)
1120	#define X86_CR4_VME_BIT 0
1121	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1122	#define X86_CR4_PVI RT_BIT_32(1)
1123	#define X86_CR4_PVI_BIT 1
1124	/** Bit 2 - TSD - Time Stamp Disable. */
1125	#define X86_CR4_TSD RT_BIT_32(2)
1126	#define X86_CR4_TSD_BIT 2
1127	/** Bit 3 - DE - Debugging Extensions. */
1128	#define X86_CR4_DE RT_BIT_32(3)
1129	#define X86_CR4_DE_BIT 3
1130	/** Bit 4 - PSE - Page Size Extension. */
1131	#define X86_CR4_PSE RT_BIT_32(4)
1132	#define X86_CR4_PSE_BIT 4
1133	/** Bit 5 - PAE - Physical Address Extension. */
1134	#define X86_CR4_PAE RT_BIT_32(5)
1135	#define X86_CR4_PAE_BIT 5
1136	/** Bit 6 - MCE - Machine-Check Enable. */
1137	#define X86_CR4_MCE RT_BIT_32(6)
1138	#define X86_CR4_MCE_BIT 6
1139	/** Bit 7 - PGE - Page Global Enable. */
1140	#define X86_CR4_PGE RT_BIT_32(7)
1141	#define X86_CR4_PGE_BIT 7
1142	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1143	#define X86_CR4_PCE RT_BIT_32(8)
1144	#define X86_CR4_PCE_BIT 8
1145	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1146	#define X86_CR4_OSFXSR RT_BIT_32(9)
1147	#define X86_CR4_OSFXSR_BIT 9
1148	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1149	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1150	#define X86_CR4_OSXMMEEXCPT_BIT 10
1151	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1152	#define X86_CR4_UMIP RT_BIT_32(11)
1153	#define X86_CR4_UMIP_BIT 11
1154	/** Bit 13 - VMXE - VMX mode is enabled. */
1155	#define X86_CR4_VMXE RT_BIT_32(13)
1156	#define X86_CR4_VMXE_BIT 13
1157	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1158	#define X86_CR4_SMXE RT_BIT_32(14)
1159	#define X86_CR4_SMXE_BIT 14
1160	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1161	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1162	#define X86_CR4_FSGSBASE_BIT 16
1163	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1164	#define X86_CR4_PCIDE RT_BIT_32(17)
1165	#define X86_CR4_PCIDE_BIT 17
1166	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1167	* extended states. */
1168	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1169	#define X86_CR4_OSXSAVE_BIT 18
1170	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1171	#define X86_CR4_SMEP RT_BIT_32(20)
1172	#define X86_CR4_SMEP_BIt 20
1173	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1174	#define X86_CR4_SMAP RT_BIT_32(21)
1175	#define X86_CR4_SMAP_BIT 21
1176	/** Bit 22 - PKE - Protection Key Enable. */
1177	#define X86_CR4_PKE RT_BIT_32(22)
1178	#define X86_CR4_PKE_BIT 22
1179	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1180	#define X86_CR4_CET RT_BIT_32(23)
1181	#define X86_CR4_CET_BIT 23
1182	/** @} */
1183
1184
1185	/** @name DR6
1186	* @{ */
1187	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1188	#define X86_DR6_B0 RT_BIT_32(0)
1189	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1190	#define X86_DR6_B1 RT_BIT_32(1)
1191	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1192	#define X86_DR6_B2 RT_BIT_32(2)
1193	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1194	#define X86_DR6_B3 RT_BIT_32(3)
1195	/** Mask of all the Bx bits. */
1196	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1197	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1198	#define X86_DR6_BD RT_BIT_32(13)
1199	/** Bit 14 - BS - Single step */
1200	#define X86_DR6_BS RT_BIT_32(14)
1201	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1202	#define X86_DR6_BT RT_BIT_32(15)
1203	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1204	#define X86_DR6_RTM RT_BIT_32(16)
1205	/** Value of DR6 after powerup/reset. */
1206	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1207	/** Bits which must be 1s in DR6. */
1208	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1209	/** Bits which must be 1s in DR6, when RTM is supported. */
1210	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1211	/** Bits which must be 0s in DR6. */
1212	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1213	/** Bits which must be 0s on writes to DR6. */
1214	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1215	/** @} */
1216
1217	/** Get the DR6.Bx bit for a the given breakpoint. */
1218	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1219
1220
1221	/** @name DR7
1222	* @{ */
1223	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1224	#define X86_DR7_L0 RT_BIT_32(0)
1225	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1226	#define X86_DR7_G0 RT_BIT_32(1)
1227	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1228	#define X86_DR7_L1 RT_BIT_32(2)
1229	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1230	#define X86_DR7_G1 RT_BIT_32(3)
1231	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1232	#define X86_DR7_L2 RT_BIT_32(4)
1233	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1234	#define X86_DR7_G2 RT_BIT_32(5)
1235	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1236	#define X86_DR7_L3 RT_BIT_32(6)
1237	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1238	#define X86_DR7_G3 RT_BIT_32(7)
1239	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1240	#define X86_DR7_LE RT_BIT_32(8)
1241	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1242	#define X86_DR7_GE RT_BIT_32(9)
1243
1244	/** L0, L1, L2, and L3. */
1245	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1246	/** L0, L1, L2, and L3. */
1247	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1248
1249	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1250	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1251	#define X86_DR7_RTM RT_BIT_32(11)
1252	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1253	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1254	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1255	* instruction is executed.
1256	* @see http://www.rcollins.org/secrets/DR7.html */
1257	#define X86_DR7_ICE_IR RT_BIT_32(12)
1258	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1259	* any DR register is accessed. */
1260	#define X86_DR7_GD RT_BIT_32(13)
1261	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1262	* Pentium. */
1263	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1264	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1265	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1266	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1267	#define X86_DR7_RW0_MASK (3 << 16)
1268	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1269	#define X86_DR7_LEN0_MASK (3 << 18)
1270	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1271	#define X86_DR7_RW1_MASK (3 << 20)
1272	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1273	#define X86_DR7_LEN1_MASK (3 << 22)
1274	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1275	#define X86_DR7_RW2_MASK (3 << 24)
1276	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1277	#define X86_DR7_LEN2_MASK (3 << 26)
1278	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1279	#define X86_DR7_RW3_MASK (3 << 28)
1280	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1281	#define X86_DR7_LEN3_MASK (3 << 30)
1282
1283	/** Bits which reads as 1s. */
1284	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1285	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1286	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1287	/** Bits which must be 0s when writing to DR7. */
1288	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1289
1290	/** Calcs the L bit of Nth breakpoint.
1291	* @param iBp The breakpoint number [0..3].
1292	*/
1293	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1294
1295	/** Calcs the G bit of Nth breakpoint.
1296	* @param iBp The breakpoint number [0..3].
1297	*/
1298	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1299
1300	/** Calcs the L and G bits of Nth breakpoint.
1301	* @param iBp The breakpoint number [0..3].
1302	*/
1303	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1304
1305	/** @name Read/Write values.
1306	* @{ */
1307	/** Break on instruction fetch only. */
1308	#define X86_DR7_RW_EO UINT32_C(0)
1309	/** Break on write only. */
1310	#define X86_DR7_RW_WO UINT32_C(1)
1311	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1312	#define X86_DR7_RW_IO UINT32_C(2)
1313	/** Break on read or write (but not instruction fetches). */
1314	#define X86_DR7_RW_RW UINT32_C(3)
1315	/** @} */
1316
1317	/** Shifts a X86_DR7_RW_* value to its right place.
1318	* @param iBp The breakpoint number [0..3].
1319	* @param fRw One of the X86_DR7_RW_* value.
1320	*/
1321	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1322
1323	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1324	* one of the X86_DR7_RW_XXX constants).
1325	*
1326	* @returns X86_DR7_RW_XXX
1327	* @param uDR7 DR7 value
1328	* @param iBp The breakpoint number [0..3].
1329	*/
1330	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1331
1332	/** R/W0, R/W1, R/W2, and R/W3. */
1333	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1334
1335	#ifndef VBOX_FOR_DTRACE_LIB
1336	/** Checks if the RW and LEN fields are set up for an instruction breakpoint.
1337	* @note This does not check if it's enabled. */
1338	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1339	/** Checks if an instruction breakpoint is enabled and configured correctly.
1340	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1341	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1342	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1343	/** Checks if there are any instruction fetch breakpoint types configured in
1344	* the RW and LEN registers and enabled in the Lx/Gx bits.
1345	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1346	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1347	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1348	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1349	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1350	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1351
1352	/** Checks if the RW field is set up for a read-write data breakpoint.
1353	* @note This does not check if it's enabled. */
1354	# define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp) ( ~((a_uDR7) & (UINT32_C(0x00030000) << ((a_iBp) * 4))) == 0)
1355
1356	/** Checks if there are any read-write data breakpoint types configured in the
1357	* RW registers and enabled in the Lx/Gx bits.
1358	*
1359	* @note We don't consider the LEN registers here, even if qword isn't
1360	* techincally valid for older processors - see
1361	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1362	*/
1363	# define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
1364	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
1365	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
1366	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
1367	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
1368
1369	/** Checks if the RW field is set up for a write-only or read-write data
1370	* breakpoint.
1371	* @note This does not check if it's enabled. */
1372	# define X86_DR7_IS_W_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x00010000) << ((a_iBp) * 4))) != 0)
1373
1374	/** Checks if there are any read-write or write-only data breakpoint types
1375	* configured in the the RW registers and enabled in the Lx/Gx bits.
1376	*
1377	* @note We don't consider the LEN registers here, even if qword isn't
1378	* techincally valid for older processors - see
1379	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1380	*/
1381	# define X86_DR7_ANY_W_ENABLED(a_uDR7) \
1382	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
1383	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
1384	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
1385	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
1386
1387	/** Checks if there are any I/O breakpoint types configured in the RW
1388	* registers. Does NOT check if these are enabled, sorry. */
1389	# define X86_DR7_ANY_RW_IO(uDR7) \
1390	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1391	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1392	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1393	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1394	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1395	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1396	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1397	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1398	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1399	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1400	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1401
1402	#endif /* !VBOX_FOR_DTRACE_LIB */
1403
1404	/** @name Length values.
1405	* @{ */
1406	#define X86_DR7_LEN_BYTE UINT32_C(0)
1407	#define X86_DR7_LEN_WORD UINT32_C(1)
1408	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1409	#define X86_DR7_LEN_DWORD UINT32_C(3)
1410	/** @} */
1411
1412	/** Shifts a X86_DR7_LEN_* value to its right place.
1413	* @param iBp The breakpoint number [0..3].
1414	* @param cb One of the X86_DR7_LEN_* values.
1415	*/
1416	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1417
1418	/** Fetch the breakpoint length bits from the DR7 value.
1419	* @param uDR7 DR7 value
1420	* @param iBp The breakpoint number [0..3].
1421	*/
1422	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1423
1424	/** Mask used to check if any breakpoints are enabled. */
1425	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1426
1427	/** LEN0, LEN1, LEN2, and LEN3. */
1428	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1429	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1430	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1431
1432	/** Value of DR7 after powerup/reset. */
1433	#define X86_DR7_INIT_VAL 0x400
1434	/** @} */
1435
1436
1437	/** @name Machine Specific Registers
1438	* @{
1439	*/
1440	/** Machine check address register (P5). */
1441	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1442	/** Machine check type register (P5). */
1443	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1444	/** Time Stamp Counter. */
1445	#define MSR_IA32_TSC 0x10
1446	#define MSR_IA32_CESR UINT32_C(0x00000011)
1447	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1448	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1449
1450	#define MSR_IA32_PLATFORM_ID 0x17
1451
1452	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1453	# define MSR_IA32_APICBASE 0x1b
1454	/** Local APIC enabled. */
1455	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1456	/** X2APIC enabled (requires the EN bit to be set). */
1457	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1458	/** The processor is the boot strap processor (BSP). */
1459	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1460	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1461	* width. */
1462	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1463	/** The default physical base address of the APIC. */
1464	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1465	/** Gets the physical base address from the MSR. */
1466	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1467	#endif
1468
1469	/** Memory Control (Intel-specific). */
1470	#define MSR_MEMORY_CTRL 0x33
1471	/** Memory Control - UC-store throttle. */
1472	#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1473	/** Memory Control - UC-lock disable. */
1474	#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1475	/** Memory Control - Split-lock disable. */
1476	#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1477
1478	/** Undocumented intel MSR for reporting thread and core counts.
1479	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1480	* first 16 bits is the thread count. The next 16 bits the core count, except
1481	* on Westmere where it seems it's only the next 4 bits for some reason. */
1482	#define MSR_CORE_THREAD_COUNT 0x35
1483
1484	/** CPU Feature control. */
1485	#define MSR_IA32_FEATURE_CONTROL 0x3A
1486	/** Feature control - Lock MSR from writes (R/W0). */
1487	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1488	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1489	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1490	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1491	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1492	/** Feature control - SENTER local functions enable (R/WL). */
1493	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1494	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1495	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1496	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1497	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1498	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1499	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1500	/** Feature control - SENTER global enable (R/WL). */
1501	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1502	/** Feature control - SGX launch control enable (R/WL). */
1503	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1504	/** Feature control - SGX global enable (R/WL). */
1505	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1506	/** Feature control - LMCE on (R/WL). */
1507	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1508
1509	/** Per-processor TSC adjust MSR. */
1510	#define MSR_IA32_TSC_ADJUST 0x3B
1511
1512	/** Spectre control register.
1513	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1514	#define MSR_IA32_SPEC_CTRL 0x48
1515	/** @name MSR_IA32_SPEC_CTRL bits
1516	* @{ */
1517	/** IBRS - Indirect branch restricted speculation. */
1518	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_64(0)
1519	/** STIBP - Single thread indirect branch predictors. */
1520	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_64(1)
1521	/** SSBD - Speculative Store Bypass Disable. */
1522	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_64(2)
1523	#define MSR_IA32_SPEC_CTRL_F_IPRED_DIS_U RT_BIT_64(3)
1524	#define MSR_IA32_SPEC_CTRL_F_IPRED_DIS_S RT_BIT_64(4)
1525	#define MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_U RT_BIT_64(5)
1526	#define MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_S RT_BIT_64(6)
1527	#define MSR_IA32_SPEC_CTRL_F_PSFD RT_BIT_64(7)
1528	#define MSR_IA32_SPEC_CTRL_F_DDPD_U RT_BIT_64(8)
1529	/* 9 is reserved (for DDPD_S?) */
1530	#define MSR_IA32_SPEC_CTRL_F_BHI_DIS_S RT_BIT_64(10)
1531	/** @} */
1532
1533	/** Prediction command register.
1534	* Write only, logical processor scope, no state since write only. */
1535	#define MSR_IA32_PRED_CMD 0x49
1536	/** IBPB - Indirect branch prediction barrier when written as 1. */
1537	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_64(0)
1538	/** SBPB - Selective branch prediction barrier when written as 1. */
1539	#define MSR_IA32_PRED_CMD_F_SBPB RT_BIT_64(7)
1540
1541	/** BIOS update trigger (microcode update). */
1542	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1543
1544	/** BIOS update signature (microcode). */
1545	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1546
1547	/** SMM monitor control. */
1548	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1549	/** SMM control - Valid. */
1550	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1551	/** SMM control - VMXOFF unblocks SMI. */
1552	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1553	/** SMM control - MSEG base physical address. */
1554	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1555
1556	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1557	#define MSR_IA32_SMBASE 0x9E
1558
1559	/** General performance counter no. 0. */
1560	#define MSR_IA32_PMC0 0xC1
1561	/** General performance counter no. 1. */
1562	#define MSR_IA32_PMC1 0xC2
1563	/** General performance counter no. 2. */
1564	#define MSR_IA32_PMC2 0xC3
1565	/** General performance counter no. 3. */
1566	#define MSR_IA32_PMC3 0xC4
1567	/** General performance counter no. 4. */
1568	#define MSR_IA32_PMC4 0xC5
1569	/** General performance counter no. 5. */
1570	#define MSR_IA32_PMC5 0xC6
1571	/** General performance counter no. 6. */
1572	#define MSR_IA32_PMC6 0xC7
1573	/** General performance counter no. 7. */
1574	#define MSR_IA32_PMC7 0xC8
1575
1576	/** Nehalem power control. */
1577	#define MSR_IA32_PLATFORM_INFO 0xCE
1578
1579	/** Core Capabilities (Intel-specific). */
1580	#define MSR_IA32_CORE_CAPABILITIES 0xCF
1581	/** STLB QoS feature supported. */
1582	#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1583	/** FUSA feature supported. */
1584	#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1585	/** RSM instruction only allowed in CPL 0. */
1586	#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1587	/** UC lock disable supported. */
1588	#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1589	/** Split-lock disable supported. */
1590	#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1591	/** Snoop filter QoS Mask MSRs supported. */
1592	#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1593	/** UC store throttling supported. */
1594	#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1595
1596	/** Get FSB clock status (Intel-specific). */
1597	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1598
1599	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1600	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1601
1602	/** C0 Maximum Frequency Clock Count */
1603	#define MSR_IA32_MPERF 0xE7
1604	/** C0 Actual Frequency Clock Count */
1605	#define MSR_IA32_APERF 0xE8
1606
1607	/** MTRR Capabilities. */
1608	#define MSR_IA32_MTRR_CAP 0xFE
1609	/** Bits 0-7 - VCNT - Variable range registers count. */
1610	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1611	/** Bit 8 - FIX - Fixed range registers supported. */
1612	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1613	/** Bit 10 - WC - Write-Combining memory type supported. */
1614	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1615	/** Bit 11 - SMRR - System Management Range Register supported. */
1616	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1617	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1618	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1619
1620
1621	#ifndef __ASSEMBLER__
1622	/**
1623	* Variable-range MTRR MSR pair.
1624	*/
1625	typedef struct X86MTRRVAR
1626	{
1627	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1628	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1629	} X86MTRRVAR;
1630	# ifndef VBOX_FOR_DTRACE_LIB
1631	AssertCompileSize(X86MTRRVAR, 16);
1632	# endif
1633	/** Pointer to a variable-range MTRR MSR pair. */
1634	typedef X86MTRRVAR *PX86MTRRVAR;
1635	/** Pointer to a const variable-range MTRR MSR pair. */
1636	typedef const X86MTRRVAR *PCX86MTRRVAR;
1637	#endif /* __ASSEMBLER__ */
1638
1639
1640	/** Memory types that can be encoded in MTRRs.
1641	* @{ */
1642	/** Uncacheable. */
1643	#define X86_MTRR_MT_UC 0
1644	/** Write Combining. */
1645	#define X86_MTRR_MT_WC 1
1646	/** Write-through. */
1647	#define X86_MTRR_MT_WT 4
1648	/** Write-protected. */
1649	#define X86_MTRR_MT_WP 5
1650	/** Writeback. */
1651	#define X86_MTRR_MT_WB 6
1652	/** @}*/
1653
1654	/** Architecture capabilities (bugfixes). */
1655	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1656	/** @name MSR_IA32_ARCH_CAPABILITIES bits
1657	* @{ */
1658	/** CPU is no subject to meltdown problems. */
1659	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_64(0)
1660	/** CPU has better IBRS and you can leave it on all the time. */
1661	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_64(1)
1662	/** CPU has return stack buffer (RSB) override. */
1663	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_64(2)
1664	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1665	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1666	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_64(3)
1667	/** CPU does not suffer from speculative store bypass (SSB) issues. */
1668	#define MSR_IA32_ARCH_CAP_F_SSB_NO RT_BIT_64(4)
1669	/** CPU does not suffer from microarchitectural data sampling (MDS) issues. */
1670	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_64(5)
1671	/** CPU does not suffer MCE after change code page size w/o invlpg issues. */
1672	#define MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO RT_BIT_64(6)
1673	/** CPU has RTM_DISABLE and TXS_CPUID_CLEAR support. */
1674	#define MSR_IA32_ARCH_CAP_F_TSX_CTRL RT_BIT_64(7)
1675	/** CPU does not suffer from transaction synchronization extensions (TSX)
1676	* asyncrhonous abort (TAA) issues. */
1677	#define MSR_IA32_ARCH_CAP_F_TAA_NO RT_BIT_64(8)
1678	/* 9 is 'reserved' */
1679	#define MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS RT_BIT_64(10)
1680	#define MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL RT_BIT_64(11)
1681	#define MSR_IA32_ARCH_CAP_F_DOITM RT_BIT_64(12)
1682	#define MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO RT_BIT_64(13)
1683	#define MSR_IA32_ARCH_CAP_F_FBSDP_NO RT_BIT_64(14)
1684	#define MSR_IA32_ARCH_CAP_F_PSDP_NO RT_BIT_64(15)
1685	/* 16 is 'reserved' */
1686	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR RT_BIT_64(17)
1687	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL RT_BIT_64(18)
1688	#define MSR_IA32_ARCH_CAP_F_RRSBA RT_BIT_64(19)
1689	#define MSR_IA32_ARCH_CAP_F_BHI_NO RT_BIT_64(20)
1690	#define MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS RT_BIT_64(21)
1691	/* 22 is 'reserved' */
1692	#define MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS RT_BIT_64(23)
1693	#define MSR_IA32_ARCH_CAP_F_PBRSB_NO RT_BIT_64(24)
1694	#define MSR_IA32_ARCH_CAP_F_GDS_CTRL RT_BIT_64(25)
1695	#define MSR_IA32_ARCH_CAP_F_GDS_NO RT_BIT_64(26)
1696	#define MSR_IA32_ARCH_CAP_F_RFDS_NO RT_BIT_64(27)
1697	#define MSR_IA32_ARCH_CAP_F_RFDS_CLEAR RT_BIT_64(28)
1698	#define MSR_IA32_ARCH_CAP_F_IGN_UMONITOR_SUPPORT RT_BIT_64(29)
1699	#define MSR_IA32_ARCH_CAP_F_MON_UMON_MITIG_SUPPORT RT_BIT_64(30)
1700	/** @} */
1701
1702	/** Flush command register.
1703	* Introduced for mitigating CVE-2018-3615 (Foreshadow), CVE-2018-3620 (NG),
1704	* CVE-2018-3646 (NG) - intel only. */
1705	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1706	/** Flush the level 1 data cache when this bit is written. */
1707	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_64(0)
1708
1709	/** Cache control/info. */
1710	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1711
1712	/** Microcode Update Option Control (R/W). */
1713	#define MSR_IA32_MCU_OPT_CTRL 0x123
1714	/** MSR_IA32_MCU_OPT_CTRL[0]: RNGDS_MITG_DIS - disable SRBDS mitigations
1715	* for RDRAND & RDSEED when set. */
1716	#define MSR_IA32_MCU_OPT_CTRL_RNGDS_MITG_DIS RT_BIT_64(0)
1717	/** MSR_IA32_MCU_OPT_CTRL[1]: RTM_ALLOW - Allow TXS according to IA32_TSX_CTRL. */
1718	#define MSR_IA32_MCU_OPT_CTRL_RTM_ALLOW RT_BIT_64(1)
1719	/** MSR_IA32_MCU_OPT_CTRL[2]: RTM_LOCKED - Lock RTM_ALLOW at zero. */
1720	#define MSR_IA32_MCU_OPT_CTRL_RTM_LOCKED RT_BIT_64(2)
1721	/** MSR_IA32_MCU_OPT_CTRL[3]: FB_CLEAR_DIS - Disables FB_CLEAR part of VERW. */
1722	#define MSR_IA32_MCU_OPT_CTRL_FB_CLEAR_DIS RT_BIT_64(3)
1723	/** MSR_IA32_MCU_OPT_CTRL[4]: GDS_MITG_DIS - Disables GDS mitigation on core. */
1724	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_DIS RT_BIT_64(4)
1725	/** MSR_IA32_MCU_OPT_CTRL[5]: GDS_MITG_DIS - Disables GDS mitigation on core. */
1726	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_LOCK RT_BIT_64(5)
1727	/** MSR_IA32_MCU_OPT_CTRL[6]: IGN_UMONITOR - Ignore UMONITOR & fail UMWAIT. */
1728	#define MSR_IA32_MCU_OPT_CTRL_IGN_UMONITOR RT_BIT_64(6)
1729	/** MSR_IA32_MCU_OPT_CTRL[7]: MON_UMON_MITG - UMONITOR/MONITOR mitigation
1730	* (may affect sibling hyperthreads). */
1731	#define MSR_IA32_MCU_OPT_CTRL_MON_UMON_MITG RT_BIT_64(7)
1732	/* Bits 63:7 reserved. */
1733	#define MSR_IA32_MCU_OPT_CTRL_RSVD_MASK UINT64_C(0xffffffffffffff80)
1734
1735	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1736	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1737	* R0 SS == CS + 8
1738	* R3 CS == CS + 16
1739	* R3 SS == CS + 24
1740	*/
1741	#define MSR_IA32_SYSENTER_CS 0x174
1742	/** SYSENTER_ESP - the R0 ESP. */
1743	#define MSR_IA32_SYSENTER_ESP 0x175
1744	/** SYSENTER_EIP - the R0 EIP. */
1745	#define MSR_IA32_SYSENTER_EIP 0x176
1746	#endif
1747
1748	/** Machine Check Global Capabilities Register. */
1749	#define MSR_IA32_MCG_CAP 0x179
1750	/** Machine Check Global Status Register. */
1751	#define MSR_IA32_MCG_STATUS 0x17A
1752	/** Machine Check Global Control Register. */
1753	#define MSR_IA32_MCG_CTRL 0x17B
1754
1755	/** Page Attribute Table. */
1756	#define MSR_IA32_CR_PAT 0x277
1757	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1758	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1759	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1760
1761	/** Memory types that can be encoded in the IA32_PAT MSR.
1762	* @{ */
1763	/** Uncacheable. */
1764	#define MSR_IA32_PAT_MT_UC 0
1765	/** Write Combining. */
1766	#define MSR_IA32_PAT_MT_WC 1
1767	/** Reserved value 2. */
1768	#define MSR_IA32_PAT_MT_RSVD_2 2
1769	/** Reserved value 3. */
1770	#define MSR_IA32_PAT_MT_RSVD_3 3
1771	/** Write-through. */
1772	#define MSR_IA32_PAT_MT_WT 4
1773	/** Write-protected. */
1774	#define MSR_IA32_PAT_MT_WP 5
1775	/** Writeback. */
1776	#define MSR_IA32_PAT_MT_WB 6
1777	/** Uncached (UC-). */
1778	#define MSR_IA32_PAT_MT_UCD 7
1779	/** @}*/
1780
1781
1782	/** Performance event select MSRs. (Intel only) */
1783	#define MSR_IA32_PERFEVTSEL0 0x186
1784	#define MSR_IA32_PERFEVTSEL1 0x187
1785	#define MSR_IA32_PERFEVTSEL2 0x188
1786	#define MSR_IA32_PERFEVTSEL3 0x189
1787
1788	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1789	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1790	* holds a ratio that Apple takes for TSC granularity.
1791	*
1792	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1793	#define MSR_FLEX_RATIO 0x194
1794	/** Performance state value and starting with Intel core more.
1795	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1796	#define MSR_IA32_PERF_STATUS 0x198
1797	#define MSR_IA32_PERF_CTL 0x199
1798	#define MSR_IA32_THERM_STATUS 0x19c
1799
1800	/** Offcore response event select registers. */
1801	#define MSR_OFFCORE_RSP_0 0x1a6
1802	#define MSR_OFFCORE_RSP_1 0x1a7
1803
1804	/** Enable misc. processor features (R/W). */
1805	#define MSR_IA32_MISC_ENABLE 0x1A0
1806	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1807	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1808	/** Automatic Thermal Control Circuit Enable (R/W). */
1809	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1810	/** Performance Monitoring Available (R). */
1811	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1812	/** Branch Trace Storage Unavailable (R/O). */
1813	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1814	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1815	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1816	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1817	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1818	/** If MONITOR/MWAIT is supported (R/W). */
1819	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1820	/** Limit CPUID Maxval to 3 leafs (R/W). */
1821	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1822	/** When set to 1, xTPR messages are disabled (R/W). */
1823	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1824	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1825	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1826
1827	/** Trace/Profile Resource Control (R/W) */
1828	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1829	/** Last branch record. */
1830	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1831	/** Branch trace flag (single step on branches). */
1832	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1833	/** Performance monitoring pin control (AMD only). */
1834	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1835	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1836	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1837	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1838	/** Trace message enable (Intel only). */
1839	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1840	/** Branch trace store (Intel only). */
1841	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1842	/** Branch trace interrupt (Intel only). */
1843	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1844	/** Branch trace off in privileged code (Intel only). */
1845	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1846	/** Branch trace off in user code (Intel only). */
1847	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1848	/** Freeze LBR on PMI flag (Intel only). */
1849	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1850	/** Freeze PERFMON on PMI flag (Intel only). */
1851	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1852	/** Freeze while SMM enabled (Intel only). */
1853	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1854	/** Advanced debugging of RTM regions (Intel only). */
1855	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1856	/** Debug control MSR valid bits (Intel only). */
1857	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1858	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1859	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1860	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1861	\| MSR_IA32_DEBUGCTL_RTM)
1862
1863	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1864	* @{ */
1865	#define MSR_P4_LASTBRANCH_0 0x1db
1866	#define MSR_P4_LASTBRANCH_1 0x1dc
1867	#define MSR_P4_LASTBRANCH_2 0x1dd
1868	#define MSR_P4_LASTBRANCH_3 0x1de
1869
1870	/** LBR Top-of-stack MSR (index to most recent record). */
1871	#define MSR_P4_LASTBRANCH_TOS 0x1da
1872	/** @} */
1873
1874	/** @name Last branch registers for Core 2 and related Xeons.
1875	* @{ */
1876	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1877	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1878	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1879	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1880
1881	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1882	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1883	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1884	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1885
1886	/** LBR Top-of-stack MSR (index to most recent record). */
1887	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1888	/** @} */
1889
1890	/** @name Last branch registers.
1891	* @{ */
1892	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1893	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1894	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1895	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1896	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1897	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1898	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1899	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1900	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1901	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1902	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1903	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1904	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1905	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1906	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1907	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1908	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1909	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1910	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1911	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1912	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1913	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1914	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1915	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1916	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1917	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1918	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1919	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1920	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1921	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1922	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1923	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1924
1925	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1926	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1927	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1928	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1929	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1930	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1931	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1932	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1933	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1934	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1935	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1936	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1937	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1938	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1939	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1940	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1941	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1942	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1943	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1944	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1945	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1946	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1947	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1948	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1949	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1950	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1951	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1952	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1953	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1954	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1955	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1956	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1957
1958	#define MSR_LASTBRANCH_0_INFO 0xdc0
1959	#define MSR_LASTBRANCH_1_INFO 0xdc1
1960	#define MSR_LASTBRANCH_2_INFO 0xdc2
1961	#define MSR_LASTBRANCH_3_INFO 0xdc3
1962	#define MSR_LASTBRANCH_4_INFO 0xdc4
1963	#define MSR_LASTBRANCH_5_INFO 0xdc5
1964	#define MSR_LASTBRANCH_6_INFO 0xdc6
1965	#define MSR_LASTBRANCH_7_INFO 0xdc7
1966	#define MSR_LASTBRANCH_8_INFO 0xdc8
1967	#define MSR_LASTBRANCH_9_INFO 0xdc9
1968	#define MSR_LASTBRANCH_10_INFO 0xdca
1969	#define MSR_LASTBRANCH_11_INFO 0xdcb
1970	#define MSR_LASTBRANCH_12_INFO 0xdcc
1971	#define MSR_LASTBRANCH_13_INFO 0xdcd
1972	#define MSR_LASTBRANCH_14_INFO 0xdce
1973	#define MSR_LASTBRANCH_15_INFO 0xdcf
1974	#define MSR_LASTBRANCH_16_INFO 0xdd0
1975	#define MSR_LASTBRANCH_17_INFO 0xdd1
1976	#define MSR_LASTBRANCH_18_INFO 0xdd2
1977	#define MSR_LASTBRANCH_19_INFO 0xdd3
1978	#define MSR_LASTBRANCH_20_INFO 0xdd4
1979	#define MSR_LASTBRANCH_21_INFO 0xdd5
1980	#define MSR_LASTBRANCH_22_INFO 0xdd6
1981	#define MSR_LASTBRANCH_23_INFO 0xdd7
1982	#define MSR_LASTBRANCH_24_INFO 0xdd8
1983	#define MSR_LASTBRANCH_25_INFO 0xdd9
1984	#define MSR_LASTBRANCH_26_INFO 0xdda
1985	#define MSR_LASTBRANCH_27_INFO 0xddb
1986	#define MSR_LASTBRANCH_28_INFO 0xddc
1987	#define MSR_LASTBRANCH_29_INFO 0xddd
1988	#define MSR_LASTBRANCH_30_INFO 0xdde
1989	#define MSR_LASTBRANCH_31_INFO 0xddf
1990
1991	/** LBR branch tracking selection MSR. */
1992	#define MSR_LASTBRANCH_SELECT 0x1c8
1993	/** LBR Top-of-stack MSR (index to most recent record). */
1994	#define MSR_LASTBRANCH_TOS 0x1c9
1995	/** @} */
1996
1997	/** @name Last event record registers.
1998	* @{ */
1999	/** Last event record source IP register. */
2000	#define MSR_LER_FROM_IP 0x1dd
2001	/** Last event record destination IP register. */
2002	#define MSR_LER_TO_IP 0x1de
2003	/** @} */
2004
2005	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
2006	#define MSR_IA32_TSX_CTRL 0x122
2007
2008	/** Variable range MTRRs.
2009	* @{ */
2010	#define MSR_IA32_MTRR_PHYSBASE0 0x200
2011	#define MSR_IA32_MTRR_PHYSMASK0 0x201
2012	#define MSR_IA32_MTRR_PHYSBASE1 0x202
2013	#define MSR_IA32_MTRR_PHYSMASK1 0x203
2014	#define MSR_IA32_MTRR_PHYSBASE2 0x204
2015	#define MSR_IA32_MTRR_PHYSMASK2 0x205
2016	#define MSR_IA32_MTRR_PHYSBASE3 0x206
2017	#define MSR_IA32_MTRR_PHYSMASK3 0x207
2018	#define MSR_IA32_MTRR_PHYSBASE4 0x208
2019	#define MSR_IA32_MTRR_PHYSMASK4 0x209
2020	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
2021	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
2022	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
2023	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
2024	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
2025	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
2026	#define MSR_IA32_MTRR_PHYSBASE8 0x210
2027	#define MSR_IA32_MTRR_PHYSMASK8 0x211
2028	#define MSR_IA32_MTRR_PHYSBASE9 0x212
2029	#define MSR_IA32_MTRR_PHYSMASK9 0x213
2030	/** @} */
2031
2032	/** Fixed range MTRRs.
2033	* @{ */
2034	#define MSR_IA32_MTRR_FIX64K_00000 0x250
2035	#define MSR_IA32_MTRR_FIX16K_80000 0x258
2036	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
2037	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
2038	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
2039	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
2040	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
2041	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
2042	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
2043	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
2044	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
2045	/** @} */
2046
2047	/** MTRR Default Type.
2048	* @{ */
2049	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
2050	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
2051	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
2052	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
2053	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
2054	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
2055	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
2056	/** @} */
2057
2058	/** Variable-range MTRR physical mask valid. */
2059	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
2060
2061	/** Variable-range MTRR memory type mask. */
2062	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
2063
2064	/** Global performance counter control facilities (Intel only). */
2065	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
2066	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
2067	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
2068
2069	/** Precise Event Based sampling (Intel only). */
2070	#define MSR_IA32_PEBS_ENABLE 0x3F1
2071
2072	#define MSR_IA32_MC0_CTL 0x400
2073	#define MSR_IA32_MC0_STATUS 0x401
2074
2075	/** Basic VMX information. */
2076	#define MSR_IA32_VMX_BASIC 0x480
2077	/** Allowed settings for pin-based VM execution controls. */
2078	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
2079	/** Allowed settings for proc-based VM execution controls. */
2080	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
2081	/** Allowed settings for the VM-exit controls. */
2082	#define MSR_IA32_VMX_EXIT_CTLS 0x483
2083	/** Allowed settings for the VM-entry controls. */
2084	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
2085	/** Misc VMX info. */
2086	#define MSR_IA32_VMX_MISC 0x485
2087	/** Fixed cleared bits in CR0. */
2088	#define MSR_IA32_VMX_CR0_FIXED0 0x486
2089	/** Fixed set bits in CR0. */
2090	#define MSR_IA32_VMX_CR0_FIXED1 0x487
2091	/** Fixed cleared bits in CR4. */
2092	#define MSR_IA32_VMX_CR4_FIXED0 0x488
2093	/** Fixed set bits in CR4. */
2094	#define MSR_IA32_VMX_CR4_FIXED1 0x489
2095	/** Information for enumerating fields in the VMCS. */
2096	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
2097	/** Allowed settings for secondary processor-based VM-execution controls. */
2098	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
2099	/** EPT capabilities. */
2100	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
2101	/** Allowed settings of all pin-based VM execution controls. */
2102	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
2103	/** Allowed settings of all proc-based VM execution controls. */
2104	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
2105	/** Allowed settings of all VMX exit controls. */
2106	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
2107	/** Allowed settings of all VMX entry controls. */
2108	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
2109	/** Allowed settings for the VM-function controls. */
2110	#define MSR_IA32_VMX_VMFUNC 0x491
2111	/** Tertiary processor-based VM execution controls. */
2112	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
2113	/** Secondary VM-exit controls. */
2114	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
2115
2116	/** Intel PT - Enable and control for trace packet generation. */
2117	#define MSR_IA32_RTIT_CTL 0x570
2118
2119	/** DS Save Area (R/W). */
2120	#define MSR_IA32_DS_AREA 0x600
2121	/** Running Average Power Limit (RAPL) power units. */
2122	#define MSR_RAPL_POWER_UNIT 0x606
2123	/** Package C3 Interrupt Response Limit. */
2124	#define MSR_PKGC3_IRTL 0x60a
2125	/** Package C6/C7S Interrupt Response Limit 1. */
2126	#define MSR_PKGC_IRTL1 0x60b
2127	/** Package C6/C7S Interrupt Response Limit 2. */
2128	#define MSR_PKGC_IRTL2 0x60c
2129	/** Package C2 Residency Counter. */
2130	#define MSR_PKG_C2_RESIDENCY 0x60d
2131	/** PKG RAPL Power Limit Control. */
2132	#define MSR_PKG_POWER_LIMIT 0x610
2133	/** PKG Energy Status. */
2134	#define MSR_PKG_ENERGY_STATUS 0x611
2135	/** PKG Perf Status. */
2136	#define MSR_PKG_PERF_STATUS 0x613
2137	/** PKG RAPL Parameters. */
2138	#define MSR_PKG_POWER_INFO 0x614
2139	/** DRAM RAPL Power Limit Control. */
2140	#define MSR_DRAM_POWER_LIMIT 0x618
2141	/** DRAM Energy Status. */
2142	#define MSR_DRAM_ENERGY_STATUS 0x619
2143	/** DRAM Performance Throttling Status. */
2144	#define MSR_DRAM_PERF_STATUS 0x61b
2145	/** DRAM RAPL Parameters. */
2146	#define MSR_DRAM_POWER_INFO 0x61c
2147	/** Package C10 Residency Counter. */
2148	#define MSR_PKG_C10_RESIDENCY 0x632
2149	/** PP0 Energy Status. */
2150	#define MSR_PP0_ENERGY_STATUS 0x639
2151	/** PP1 Energy Status. */
2152	#define MSR_PP1_ENERGY_STATUS 0x641
2153	/** Turbo Activation Ratio. */
2154	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
2155	/** Core Performance Limit Reasons. */
2156	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
2157
2158	/** Userspace Control flow Enforcement Technology setting. */
2159	#define MSR_IA32_U_CET 0x6a0
2160	/** Supervisor space Control flow Enforcement Technology setting. */
2161	#define MSR_IA32_S_CET 0x6a2
2162	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
2163	* @{ */
2164	/** Enables the Shadow stack. */
2165	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
2166	/** Enables WRSS{D,Q}W instructions. */
2167	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
2168	/** Enables indirect branch tracking. */
2169	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
2170	/** Enable legacy compatibility treatment for indirect branch tracking. */
2171	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
2172	/** Enables the use of no-track prefix for indirect branch tracking. */
2173	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
2174	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
2175	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
2176	/** Suppresses indirect branch tracking. */
2177	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
2178	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
2179	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
2180	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
2181	* on a ENDBRANCH instruction. */
2182	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
2183	/** @} */
2184
2185	/** X2APIC MSR range start. */
2186	#define MSR_IA32_X2APIC_START 0x800
2187	/** X2APIC MSR - APIC ID Register. */
2188	#define MSR_IA32_X2APIC_ID 0x802
2189	/** X2APIC MSR - APIC Version Register. */
2190	#define MSR_IA32_X2APIC_VERSION 0x803
2191	/** X2APIC MSR - Task Priority Register. */
2192	#define MSR_IA32_X2APIC_TPR 0x808
2193	/** X2APIC MSR - Processor Priority register. */
2194	#define MSR_IA32_X2APIC_PPR 0x80A
2195	/** X2APIC MSR - End Of Interrupt register. */
2196	#define MSR_IA32_X2APIC_EOI 0x80B
2197	/** X2APIC MSR - Logical Destination Register. */
2198	#define MSR_IA32_X2APIC_LDR 0x80D
2199	/** X2APIC MSR - Spurious Interrupt Vector Register. */
2200	#define MSR_IA32_X2APIC_SVR 0x80F
2201	/** X2APIC MSR - In-service Register (bits 31:0). */
2202	#define MSR_IA32_X2APIC_ISR0 0x810
2203	/** X2APIC MSR - In-service Register (bits 63:32). */
2204	#define MSR_IA32_X2APIC_ISR1 0x811
2205	/** X2APIC MSR - In-service Register (bits 95:64). */
2206	#define MSR_IA32_X2APIC_ISR2 0x812
2207	/** X2APIC MSR - In-service Register (bits 127:96). */
2208	#define MSR_IA32_X2APIC_ISR3 0x813
2209	/** X2APIC MSR - In-service Register (bits 159:128). */
2210	#define MSR_IA32_X2APIC_ISR4 0x814
2211	/** X2APIC MSR - In-service Register (bits 191:160). */
2212	#define MSR_IA32_X2APIC_ISR5 0x815
2213	/** X2APIC MSR - In-service Register (bits 223:192). */
2214	#define MSR_IA32_X2APIC_ISR6 0x816
2215	/** X2APIC MSR - In-service Register (bits 255:224). */
2216	#define MSR_IA32_X2APIC_ISR7 0x817
2217	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2218	#define MSR_IA32_X2APIC_TMR0 0x818
2219	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2220	#define MSR_IA32_X2APIC_TMR1 0x819
2221	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2222	#define MSR_IA32_X2APIC_TMR2 0x81A
2223	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2224	#define MSR_IA32_X2APIC_TMR3 0x81B
2225	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2226	#define MSR_IA32_X2APIC_TMR4 0x81C
2227	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2228	#define MSR_IA32_X2APIC_TMR5 0x81D
2229	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2230	#define MSR_IA32_X2APIC_TMR6 0x81E
2231	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2232	#define MSR_IA32_X2APIC_TMR7 0x81F
2233	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2234	#define MSR_IA32_X2APIC_IRR0 0x820
2235	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2236	#define MSR_IA32_X2APIC_IRR1 0x821
2237	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2238	#define MSR_IA32_X2APIC_IRR2 0x822
2239	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2240	#define MSR_IA32_X2APIC_IRR3 0x823
2241	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2242	#define MSR_IA32_X2APIC_IRR4 0x824
2243	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2244	#define MSR_IA32_X2APIC_IRR5 0x825
2245	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2246	#define MSR_IA32_X2APIC_IRR6 0x826
2247	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2248	#define MSR_IA32_X2APIC_IRR7 0x827
2249	/** X2APIC MSR - Error Status Register. */
2250	#define MSR_IA32_X2APIC_ESR 0x828
2251	/** X2APIC MSR - LVT CMCI Register. */
2252	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2253	/** X2APIC MSR - Interrupt Command Register. */
2254	#define MSR_IA32_X2APIC_ICR 0x830
2255	/** X2APIC MSR - LVT Timer Register. */
2256	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2257	/** X2APIC MSR - LVT Thermal Sensor Register. */
2258	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2259	/** X2APIC MSR - LVT Performance Counter Register. */
2260	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2261	/** X2APIC MSR - LVT LINT0 Register. */
2262	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2263	/** X2APIC MSR - LVT LINT1 Register. */
2264	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2265	/** X2APIC MSR - LVT Error Register . */
2266	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2267	/** X2APIC MSR - Timer Initial Count Register. */
2268	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2269	/** X2APIC MSR - Timer Current Count Register. */
2270	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2271	/** X2APIC MSR - Timer Divide Configuration Register. */
2272	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2273	/** X2APIC MSR - Self IPI. */
2274	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2275	/** X2APIC MSR range end. */
2276	#define MSR_IA32_X2APIC_END 0x8FF
2277	/** X2APIC MSR - LVT start range. */
2278	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2279	/** X2APIC MSR - LVT end range (inclusive). */
2280	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2281
2282	/** K6 EFER - Extended Feature Enable Register. */
2283	#define MSR_K6_EFER UINT32_C(0xc0000080)
2284	/** @todo document EFER */
2285	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2286	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2287	/** Bit 8 - LME - Long mode enabled. (R/W) */
2288	#define MSR_K6_EFER_LME RT_BIT_32(8)
2289	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2290	/** Bit 10 - LMA - Long mode active. (R) */
2291	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2292	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2293	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2294	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2295	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2296	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2297	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2298	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2299	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2300	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2301	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2302	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2303	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2304	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2305	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2306
2307	/** K6 STAR - SYSCALL/RET targets. */
2308	#define MSR_K6_STAR UINT32_C(0xc0000081)
2309	/** Shift value for getting the SYSRET CS and SS value. */
2310	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2311	/** Shift value for getting the SYSCALL CS and SS value. */
2312	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2313	/** Selector mask for use after shifting. */
2314	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2315	/** The mask which give the SYSCALL EIP. */
2316	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2317	/** K6 WHCR - Write Handling Control Register. */
2318	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2319	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2320	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2321	/** K6 PSOR - Processor State Observability Register. */
2322	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2323	/** K6 PFIR - Page Flush/Invalidate Register. */
2324	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2325
2326	/** Performance counter MSRs. (AMD only) */
2327	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2328	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2329	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2330	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2331	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2332	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2333	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2334	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2335
2336	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2337	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2338	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2339	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2340	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2341	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2342	/** K8 FS.base - The 64-bit base FS register. */
2343	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2344	/** K8 GS.base - The 64-bit base GS register. */
2345	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2346	/** K8 KernelGSbase - Used with SWAPGS. */
2347	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2348	/** K8 TSC_AUX - Used with RDTSCP. */
2349	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2350	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2351	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2352	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2353	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2354	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2355	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2356	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2357	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2358
2359	/** SMM MSRs. */
2360	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2361	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2362	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2363
2364	/** North bridge config? See BIOS & Kernel dev guides for
2365	* details. */
2366	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2367
2368	/** Hypertransport interrupt pending register.
2369	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2370	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2371
2372	/** SVM Control. */
2373	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2374	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2375	* features. */
2376	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2377	/** If set, non-intercepted INIT signals are converted to \#SX
2378	* exceptions. */
2379	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2380	/** Disables A20 masking. */
2381	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2382	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2383	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2384	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2385	* clear, EFER.SVME can be written normally. */
2386	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2387
2388	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2389	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2390	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2391	* host state during world switch. */
2392	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2393
2394	/** Virtualized speculation control for AMD processors.
2395	*
2396	* Unified interface among different CPU generations.
2397	* The VMM will set any architectural MSRs based on the CPU.
2398	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2399	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2400	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2401	/** Speculative Store Bypass Disable. */
2402	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2403
2404	/** @} */
2405
2406
2407	/** @name Page Table / Directory / Directory Pointers / L4.
2408	* @{
2409	*/
2410
2411	#ifndef __ASSEMBLER__
2412	/** Page table/directory entry as an unsigned integer. */
2413	typedef uint32_t X86PGUINT;
2414	/** Pointer to a page table/directory table entry as an unsigned integer. */
2415	typedef X86PGUINT *PX86PGUINT;
2416	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2417	typedef X86PGUINT const *PCX86PGUINT;
2418	#endif
2419
2420	/** Number of entries in a 32-bit PT/PD. */
2421	#define X86_PG_ENTRIES 1024
2422
2423
2424	#ifndef __ASSEMBLER__
2425	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2426	typedef uint64_t X86PGPAEUINT;
2427	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2428	typedef X86PGPAEUINT *PX86PGPAEUINT;
2429	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2430	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2431	#endif
2432
2433	/** Number of entries in a PAE PT/PD. */
2434	#define X86_PG_PAE_ENTRIES 512
2435	/** Number of entries in a PAE PDPT. */
2436	#define X86_PG_PAE_PDPE_ENTRIES 4
2437
2438	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2439	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2440	/** Number of entries in an AMD64 PDPT.
2441	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2442	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2443
2444	/** The size of a default page. */
2445	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2446	/** The page shift of a default page. */
2447	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2448	/** The default page offset mask. */
2449	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2450	/** The default page base mask for virtual addresses. */
2451	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2452	/** The default page base mask for virtual addresses - 32bit version. */
2453	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2454
2455	/** The size of a 4KB page. */
2456	#define X86_PAGE_4K_SIZE _4K
2457	/** The page shift of a 4KB page. */
2458	#define X86_PAGE_4K_SHIFT 12
2459	/** The 4KB page offset mask. */
2460	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2461	/** The 4KB page base mask for virtual addresses. */
2462	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2463	/** The 4KB page base mask for virtual addresses - 32bit version. */
2464	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2465
2466	/** The size of a 2MB page. */
2467	#define X86_PAGE_2M_SIZE _2M
2468	/** The page shift of a 2MB page. */
2469	#define X86_PAGE_2M_SHIFT 21
2470	/** The 2MB page offset mask. */
2471	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2472	/** The 2MB page base mask for virtual addresses. */
2473	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2474	/** The 2MB page base mask for virtual addresses - 32bit version. */
2475	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2476
2477	/** The size of a 4MB page. */
2478	#define X86_PAGE_4M_SIZE _4M
2479	/** The page shift of a 4MB page. */
2480	#define X86_PAGE_4M_SHIFT 22
2481	/** The 4MB page offset mask. */
2482	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2483	/** The 4MB page base mask for virtual addresses. */
2484	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2485	/** The 4MB page base mask for virtual addresses - 32bit version. */
2486	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2487
2488	/** The size of a 1GB page. */
2489	#define X86_PAGE_1G_SIZE _1G
2490	/** The page shift of a 1GB page. */
2491	#define X86_PAGE_1G_SHIFT 30
2492	/** The 1GB page offset mask. */
2493	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2494	/** The 1GB page base mask for virtual addresses. */
2495	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2496
2497	/**
2498	* Check if the given address is canonical.
2499	*/
2500	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2501
2502	/**
2503	* Gets the page base mask given the page shift.
2504	*/
2505	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2506
2507	/**
2508	* Gets the page offset mask given the page shift.
2509	*/
2510	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2511
2512
2513	/** @name Page Table Entry
2514	* @{
2515	*/
2516	/** Bit 0 - P - Present bit. */
2517	#define X86_PTE_BIT_P 0
2518	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2519	#define X86_PTE_BIT_RW 1
2520	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2521	#define X86_PTE_BIT_US 2
2522	/** Bit 3 - PWT - Page level write thru bit. */
2523	#define X86_PTE_BIT_PWT 3
2524	/** Bit 4 - PCD - Page level cache disable bit. */
2525	#define X86_PTE_BIT_PCD 4
2526	/** Bit 5 - A - Access bit. */
2527	#define X86_PTE_BIT_A 5
2528	/** Bit 6 - D - Dirty bit. */
2529	#define X86_PTE_BIT_D 6
2530	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2531	#define X86_PTE_BIT_PAT 7
2532	/** Bit 8 - G - Global flag. */
2533	#define X86_PTE_BIT_G 8
2534	/** Bits 63 - NX - PAE/LM - No execution flag. */
2535	#define X86_PTE_PAE_BIT_NX 63
2536
2537	/** Bit 0 - P - Present bit mask. */
2538	#define X86_PTE_P RT_BIT_32(0)
2539	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2540	#define X86_PTE_RW RT_BIT_32(1)
2541	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2542	#define X86_PTE_US RT_BIT_32(2)
2543	/** Bit 3 - PWT - Page level write thru bit mask. */
2544	#define X86_PTE_PWT RT_BIT_32(3)
2545	/** Bit 4 - PCD - Page level cache disable bit mask. */
2546	#define X86_PTE_PCD RT_BIT_32(4)
2547	/** Bit 5 - A - Access bit mask. */
2548	#define X86_PTE_A RT_BIT_32(5)
2549	/** Bit 6 - D - Dirty bit mask. */
2550	#define X86_PTE_D RT_BIT_32(6)
2551	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2552	#define X86_PTE_PAT RT_BIT_32(7)
2553	/** Bit 8 - G - Global bit mask. */
2554	#define X86_PTE_G RT_BIT_32(8)
2555
2556	/** Bits 9-11 - - Available for use to system software. */
2557	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2558	/** Bits 12-31 - - Physical Page number of the next level. */
2559	#define X86_PTE_PG_MASK ( 0xfffff000 )
2560
2561	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2562	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2563	/** Bits 63 - NX - PAE/LM - No execution flag. */
2564	#define X86_PTE_PAE_NX RT_BIT_64(63)
2565	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2566	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2567	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2568	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2569	/** No bits - - LM - MBZ bits when NX is active. */
2570	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2571	/** Bits 63 - - LM - MBZ bits when no NX. */
2572	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2573
2574	#ifndef __ASSEMBLER__
2575
2576	/**
2577	* Page table entry.
2578	*/
2579	typedef struct X86PTEBITS
2580	{
2581	/** Flags whether(=1) or not the page is present. */
2582	uint32_t u1Present : 1;
2583	/** Read(=0) / Write(=1) flag. */
2584	uint32_t u1Write : 1;
2585	/** User(=1) / Supervisor (=0) flag. */
2586	uint32_t u1User : 1;
2587	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2588	uint32_t u1WriteThru : 1;
2589	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2590	uint32_t u1CacheDisable : 1;
2591	/** Accessed flag.
2592	* Indicates that the page have been read or written to. */
2593	uint32_t u1Accessed : 1;
2594	/** Dirty flag.
2595	* Indicates that the page has been written to. */
2596	uint32_t u1Dirty : 1;
2597	/** Reserved / If PAT enabled, bit 2 of the index. */
2598	uint32_t u1PAT : 1;
2599	/** Global flag. (Ignored in all but final level.) */
2600	uint32_t u1Global : 1;
2601	/** Available for use to system software. */
2602	uint32_t u3Available : 3;
2603	/** Physical Page number of the next level. */
2604	uint32_t u20PageNo : 20;
2605	} X86PTEBITS;
2606	# ifndef VBOX_FOR_DTRACE_LIB
2607	AssertCompileSize(X86PTEBITS, 4);
2608	# endif
2609	/** Pointer to a page table entry. */
2610	typedef X86PTEBITS *PX86PTEBITS;
2611	/** Pointer to a const page table entry. */
2612	typedef const X86PTEBITS *PCX86PTEBITS;
2613
2614	/**
2615	* Page table entry.
2616	*/
2617	typedef union X86PTE
2618	{
2619	/** Unsigned integer view */
2620	X86PGUINT u;
2621	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2622	/** Bit field view. */
2623	X86PTEBITS n;
2624	# endif
2625	/** 32-bit view. */
2626	uint32_t au32[1];
2627	/** 16-bit view. */
2628	uint16_t au16[2];
2629	/** 8-bit view. */
2630	uint8_t au8[4];
2631	} X86PTE;
2632	# ifndef VBOX_FOR_DTRACE_LIB
2633	AssertCompileSize(X86PTE, 4);
2634	# endif
2635	/** Pointer to a page table entry. */
2636	typedef X86PTE *PX86PTE;
2637	/** Pointer to a const page table entry. */
2638	typedef const X86PTE *PCX86PTE;
2639
2640
2641	/**
2642	* PAE page table entry.
2643	*/
2644	typedef struct X86PTEPAEBITS
2645	{
2646	/** Flags whether(=1) or not the page is present. */
2647	uint32_t u1Present : 1;
2648	/** Read(=0) / Write(=1) flag. */
2649	uint32_t u1Write : 1;
2650	/** User(=1) / Supervisor(=0) flag. */
2651	uint32_t u1User : 1;
2652	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2653	uint32_t u1WriteThru : 1;
2654	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2655	uint32_t u1CacheDisable : 1;
2656	/** Accessed flag.
2657	* Indicates that the page have been read or written to. */
2658	uint32_t u1Accessed : 1;
2659	/** Dirty flag.
2660	* Indicates that the page has been written to. */
2661	uint32_t u1Dirty : 1;
2662	/** Reserved / If PAT enabled, bit 2 of the index. */
2663	uint32_t u1PAT : 1;
2664	/** Global flag. (Ignored in all but final level.) */
2665	uint32_t u1Global : 1;
2666	/** Available for use to system software. */
2667	uint32_t u3Available : 3;
2668	/** Physical Page number of the next level - Low Part. Don't use this. */
2669	uint32_t u20PageNoLow : 20;
2670	/** Physical Page number of the next level - High Part. Don't use this. */
2671	uint32_t u20PageNoHigh : 20;
2672	/** MBZ bits */
2673	uint32_t u11Reserved : 11;
2674	/** No Execute flag. */
2675	uint32_t u1NoExecute : 1;
2676	} X86PTEPAEBITS;
2677	# ifndef VBOX_FOR_DTRACE_LIB
2678	AssertCompileSize(X86PTEPAEBITS, 8);
2679	# endif
2680	/** Pointer to a page table entry. */
2681	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2682	/** Pointer to a page table entry. */
2683	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2684
2685	/**
2686	* PAE Page table entry.
2687	*/
2688	typedef union X86PTEPAE
2689	{
2690	/** Unsigned integer view */
2691	X86PGPAEUINT u;
2692	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2693	/** Bit field view. */
2694	X86PTEPAEBITS n;
2695	# endif
2696	/** 32-bit view. */
2697	uint32_t au32[2];
2698	/** 16-bit view. */
2699	uint16_t au16[4];
2700	/** 8-bit view. */
2701	uint8_t au8[8];
2702	} X86PTEPAE;
2703	# ifndef VBOX_FOR_DTRACE_LIB
2704	AssertCompileSize(X86PTEPAE, 8);
2705	# endif
2706	/** Pointer to a PAE page table entry. */
2707	typedef X86PTEPAE *PX86PTEPAE;
2708	/** Pointer to a const PAE page table entry. */
2709	typedef const X86PTEPAE *PCX86PTEPAE;
2710	/** @} */
2711
2712	/**
2713	* Page table.
2714	*/
2715	typedef struct X86PT
2716	{
2717	/** PTE Array. */
2718	X86PTE a[X86_PG_ENTRIES];
2719	} X86PT;
2720	# ifndef VBOX_FOR_DTRACE_LIB
2721	AssertCompileSize(X86PT, 4096);
2722	# endif
2723	/** Pointer to a page table. */
2724	typedef X86PT *PX86PT;
2725	/** Pointer to a const page table. */
2726	typedef const X86PT *PCX86PT;
2727
2728	#endif /* !__ASSEMBLER__ */
2729
2730	/** The page shift to get the PT index. */
2731	#define X86_PT_SHIFT 12
2732	/** The PT index mask (apply to a shifted page address). */
2733	#define X86_PT_MASK 0x3ff
2734
2735
2736	#ifndef __ASSEMBLER__
2737	/**
2738	* Page directory.
2739	*/
2740	typedef struct X86PTPAE
2741	{
2742	/** PTE Array. */
2743	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2744	} X86PTPAE;
2745	# ifndef VBOX_FOR_DTRACE_LIB
2746	AssertCompileSize(X86PTPAE, 4096);
2747	# endif
2748	/** Pointer to a page table. */
2749	typedef X86PTPAE *PX86PTPAE;
2750	/** Pointer to a const page table. */
2751	typedef const X86PTPAE *PCX86PTPAE;
2752	#endif /* !__ASSEMBLER__ */
2753
2754	/** The page shift to get the PA PTE index. */
2755	#define X86_PT_PAE_SHIFT 12
2756	/** The PAE PT index mask (apply to a shifted page address). */
2757	#define X86_PT_PAE_MASK 0x1ff
2758
2759
2760	/** @name 4KB Page Directory Entry
2761	* @{
2762	*/
2763	/** Bit 0 - P - Present bit. */
2764	#define X86_PDE_P RT_BIT_32(0)
2765	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2766	#define X86_PDE_RW RT_BIT_32(1)
2767	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2768	#define X86_PDE_US RT_BIT_32(2)
2769	/** Bit 3 - PWT - Page level write thru bit. */
2770	#define X86_PDE_PWT RT_BIT_32(3)
2771	/** Bit 4 - PCD - Page level cache disable bit. */
2772	#define X86_PDE_PCD RT_BIT_32(4)
2773	/** Bit 5 - A - Access bit. */
2774	#define X86_PDE_A RT_BIT_32(5)
2775	/** Bit 7 - PS - Page size attribute.
2776	* Clear mean 4KB pages, set means large pages (2/4MB). */
2777	#define X86_PDE_PS RT_BIT_32(7)
2778	/** Bits 9-11 - - Available for use to system software. */
2779	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2780	/** Bits 12-31 - - Physical Page number of the next level. */
2781	#define X86_PDE_PG_MASK ( 0xfffff000 )
2782
2783	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2784	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2785	/** Bits 63 - NX - PAE/LM - No execution flag. */
2786	#define X86_PDE_PAE_NX RT_BIT_64(63)
2787	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2788	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2789	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2790	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2791	/** Bit 7 - - LM - MBZ bits when NX is active. */
2792	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2793	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2794	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2795
2796	#ifndef __ASSEMBLER__
2797
2798	/**
2799	* Page directory entry.
2800	*/
2801	typedef struct X86PDEBITS
2802	{
2803	/** Flags whether(=1) or not the page is present. */
2804	uint32_t u1Present : 1;
2805	/** Read(=0) / Write(=1) flag. */
2806	uint32_t u1Write : 1;
2807	/** User(=1) / Supervisor (=0) flag. */
2808	uint32_t u1User : 1;
2809	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2810	uint32_t u1WriteThru : 1;
2811	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2812	uint32_t u1CacheDisable : 1;
2813	/** Accessed flag.
2814	* Indicates that the page has been read or written to. */
2815	uint32_t u1Accessed : 1;
2816	/** Reserved / Ignored (dirty bit). */
2817	uint32_t u1Reserved0 : 1;
2818	/** Size bit if PSE is enabled - in any event it's 0. */
2819	uint32_t u1Size : 1;
2820	/** Reserved / Ignored (global bit). */
2821	uint32_t u1Reserved1 : 1;
2822	/** Available for use to system software. */
2823	uint32_t u3Available : 3;
2824	/** Physical Page number of the next level. */
2825	uint32_t u20PageNo : 20;
2826	} X86PDEBITS;
2827	# ifndef VBOX_FOR_DTRACE_LIB
2828	AssertCompileSize(X86PDEBITS, 4);
2829	# endif
2830	/** Pointer to a page directory entry. */
2831	typedef X86PDEBITS *PX86PDEBITS;
2832	/** Pointer to a const page directory entry. */
2833	typedef const X86PDEBITS *PCX86PDEBITS;
2834
2835
2836	/**
2837	* PAE page directory entry.
2838	*/
2839	typedef struct X86PDEPAEBITS
2840	{
2841	/** Flags whether(=1) or not the page is present. */
2842	uint32_t u1Present : 1;
2843	/** Read(=0) / Write(=1) flag. */
2844	uint32_t u1Write : 1;
2845	/** User(=1) / Supervisor (=0) flag. */
2846	uint32_t u1User : 1;
2847	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2848	uint32_t u1WriteThru : 1;
2849	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2850	uint32_t u1CacheDisable : 1;
2851	/** Accessed flag.
2852	* Indicates that the page has been read or written to. */
2853	uint32_t u1Accessed : 1;
2854	/** Reserved / Ignored (dirty bit). */
2855	uint32_t u1Reserved0 : 1;
2856	/** Size bit if PSE is enabled - in any event it's 0. */
2857	uint32_t u1Size : 1;
2858	/** Reserved / Ignored (global bit). / */
2859	uint32_t u1Reserved1 : 1;
2860	/** Available for use to system software. */
2861	uint32_t u3Available : 3;
2862	/** Physical Page number of the next level - Low Part. Don't use! */
2863	uint32_t u20PageNoLow : 20;
2864	/** Physical Page number of the next level - High Part. Don't use! */
2865	uint32_t u20PageNoHigh : 20;
2866	/** MBZ bits */
2867	uint32_t u11Reserved : 11;
2868	/** No Execute flag. */
2869	uint32_t u1NoExecute : 1;
2870	} X86PDEPAEBITS;
2871	# ifndef VBOX_FOR_DTRACE_LIB
2872	AssertCompileSize(X86PDEPAEBITS, 8);
2873	# endif
2874	/** Pointer to a page directory entry. */
2875	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2876	/** Pointer to a const page directory entry. */
2877	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2878
2879	#endif /* !__ASSEMBLER__ */
2880
2881	/** @} */
2882
2883
2884	/** @name 2/4MB Page Directory Entry
2885	* @{
2886	*/
2887	/** Bit 0 - P - Present bit. */
2888	#define X86_PDE4M_P RT_BIT_32(0)
2889	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2890	#define X86_PDE4M_RW RT_BIT_32(1)
2891	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2892	#define X86_PDE4M_US RT_BIT_32(2)
2893	/** Bit 3 - PWT - Page level write thru bit. */
2894	#define X86_PDE4M_PWT RT_BIT_32(3)
2895	/** Bit 4 - PCD - Page level cache disable bit. */
2896	#define X86_PDE4M_PCD RT_BIT_32(4)
2897	/** Bit 5 - A - Access bit. */
2898	#define X86_PDE4M_A RT_BIT_32(5)
2899	/** Bit 6 - D - Dirty bit. */
2900	#define X86_PDE4M_D RT_BIT_32(6)
2901	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2902	#define X86_PDE4M_PS RT_BIT_32(7)
2903	/** Bit 8 - G - Global flag. */
2904	#define X86_PDE4M_G RT_BIT_32(8)
2905	/** Bits 9-11 - AVL - Available for use to system software. */
2906	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2907	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2908	#define X86_PDE4M_PAT RT_BIT_32(12)
2909	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2910	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2911	/** Bits 22-31 - - Physical Page number. */
2912	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2913	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2914	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2915	/** The number of bits to the high part of the page number. */
2916	#define X86_PDE4M_PG_HIGH_SHIFT 19
2917	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2918	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2919
2920	/** Bits 21-51 - - PAE/LM - Physical Page number.
2921	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2922	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2923	/** Bits 63 - NX - PAE/LM - No execution flag. */
2924	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2925	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2926	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2927	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2928	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2929	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2930	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2931	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2932	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2933
2934	#ifndef __ASSEMBLER__
2935
2936	/**
2937	* 4MB page directory entry.
2938	*/
2939	typedef struct X86PDE4MBITS
2940	{
2941	/** Flags whether(=1) or not the page is present. */
2942	uint32_t u1Present : 1;
2943	/** Read(=0) / Write(=1) flag. */
2944	uint32_t u1Write : 1;
2945	/** User(=1) / Supervisor (=0) flag. */
2946	uint32_t u1User : 1;
2947	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2948	uint32_t u1WriteThru : 1;
2949	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2950	uint32_t u1CacheDisable : 1;
2951	/** Accessed flag.
2952	* Indicates that the page have been read or written to. */
2953	uint32_t u1Accessed : 1;
2954	/** Dirty flag.
2955	* Indicates that the page has been written to. */
2956	uint32_t u1Dirty : 1;
2957	/** Page size flag - always 1 for 4MB entries. */
2958	uint32_t u1Size : 1;
2959	/** Global flag. */
2960	uint32_t u1Global : 1;
2961	/** Available for use to system software. */
2962	uint32_t u3Available : 3;
2963	/** Reserved / If PAT enabled, bit 2 of the index. */
2964	uint32_t u1PAT : 1;
2965	/** Bits 32-39 of the page number on AMD64.
2966	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2967	uint32_t u8PageNoHigh : 8;
2968	/** Reserved. */
2969	uint32_t u1Reserved : 1;
2970	/** Physical Page number of the page. */
2971	uint32_t u10PageNo : 10;
2972	} X86PDE4MBITS;
2973	# ifndef VBOX_FOR_DTRACE_LIB
2974	AssertCompileSize(X86PDE4MBITS, 4);
2975	# endif
2976	/** Pointer to a page table entry. */
2977	typedef X86PDE4MBITS *PX86PDE4MBITS;
2978	/** Pointer to a const page table entry. */
2979	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2980
2981
2982	/**
2983	* 2MB PAE page directory entry.
2984	*/
2985	typedef struct X86PDE2MPAEBITS
2986	{
2987	/** Flags whether(=1) or not the page is present. */
2988	uint32_t u1Present : 1;
2989	/** Read(=0) / Write(=1) flag. */
2990	uint32_t u1Write : 1;
2991	/** User(=1) / Supervisor(=0) flag. */
2992	uint32_t u1User : 1;
2993	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2994	uint32_t u1WriteThru : 1;
2995	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2996	uint32_t u1CacheDisable : 1;
2997	/** Accessed flag.
2998	* Indicates that the page have been read or written to. */
2999	uint32_t u1Accessed : 1;
3000	/** Dirty flag.
3001	* Indicates that the page has been written to. */
3002	uint32_t u1Dirty : 1;
3003	/** Page size flag - always 1 for 2MB entries. */
3004	uint32_t u1Size : 1;
3005	/** Global flag. */
3006	uint32_t u1Global : 1;
3007	/** Available for use to system software. */
3008	uint32_t u3Available : 3;
3009	/** Reserved / If PAT enabled, bit 2 of the index. */
3010	uint32_t u1PAT : 1;
3011	/** Reserved. */
3012	uint32_t u9Reserved : 9;
3013	/** Physical Page number of the next level - Low part. Don't use! */
3014	uint32_t u10PageNoLow : 10;
3015	/** Physical Page number of the next level - High part. Don't use! */
3016	uint32_t u20PageNoHigh : 20;
3017	/** MBZ bits */
3018	uint32_t u11Reserved : 11;
3019	/** No Execute flag. */
3020	uint32_t u1NoExecute : 1;
3021	} X86PDE2MPAEBITS;
3022	# ifndef VBOX_FOR_DTRACE_LIB
3023	AssertCompileSize(X86PDE2MPAEBITS, 8);
3024	# endif
3025	/** Pointer to a 2MB PAE page table entry. */
3026	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
3027	/** Pointer to a 2MB PAE page table entry. */
3028	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
3029
3030	#endif /* !__ASSEMBLER__ */
3031
3032	/** @} */
3033
3034	#ifndef __ASSEMBLER__
3035
3036	/**
3037	* Page directory entry.
3038	*/
3039	typedef union X86PDE
3040	{
3041	/** Unsigned integer view. */
3042	X86PGUINT u;
3043	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3044	/** Normal view. */
3045	X86PDEBITS n;
3046	/** 4MB view (big). */
3047	X86PDE4MBITS b;
3048	# endif
3049	/** 8 bit unsigned integer view. */
3050	uint8_t au8[4];
3051	/** 16 bit unsigned integer view. */
3052	uint16_t au16[2];
3053	/** 32 bit unsigned integer view. */
3054	uint32_t au32[1];
3055	} X86PDE;
3056	# ifndef VBOX_FOR_DTRACE_LIB
3057	AssertCompileSize(X86PDE, 4);
3058	# endif
3059	/** Pointer to a page directory entry. */
3060	typedef X86PDE *PX86PDE;
3061	/** Pointer to a const page directory entry. */
3062	typedef const X86PDE *PCX86PDE;
3063
3064	/**
3065	* PAE page directory entry.
3066	*/
3067	typedef union X86PDEPAE
3068	{
3069	/** Unsigned integer view. */
3070	X86PGPAEUINT u;
3071	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3072	/** Normal view. */
3073	X86PDEPAEBITS n;
3074	/** 2MB page view (big). */
3075	X86PDE2MPAEBITS b;
3076	# endif
3077	/** 8 bit unsigned integer view. */
3078	uint8_t au8[8];
3079	/** 16 bit unsigned integer view. */
3080	uint16_t au16[4];
3081	/** 32 bit unsigned integer view. */
3082	uint32_t au32[2];
3083	} X86PDEPAE;
3084	# ifndef VBOX_FOR_DTRACE_LIB
3085	AssertCompileSize(X86PDEPAE, 8);
3086	# endif
3087	/** Pointer to a page directory entry. */
3088	typedef X86PDEPAE *PX86PDEPAE;
3089	/** Pointer to a const page directory entry. */
3090	typedef const X86PDEPAE *PCX86PDEPAE;
3091
3092	/**
3093	* Page directory.
3094	*/
3095	typedef struct X86PD
3096	{
3097	/** PDE Array. */
3098	X86PDE a[X86_PG_ENTRIES];
3099	} X86PD;
3100	# ifndef VBOX_FOR_DTRACE_LIB
3101	AssertCompileSize(X86PD, 4096);
3102	# endif
3103	/** Pointer to a page directory. */
3104	typedef X86PD *PX86PD;
3105	/** Pointer to a const page directory. */
3106	typedef const X86PD *PCX86PD;
3107
3108	#endif /* !__ASSEMBLER__ */
3109
3110	/** The page shift to get the PD index. */
3111	#define X86_PD_SHIFT 22
3112	/** The PD index mask (apply to a shifted page address). */
3113	#define X86_PD_MASK 0x3ff
3114
3115
3116	#ifndef __ASSEMBLER__
3117	/**
3118	* PAE page directory.
3119	*/
3120	typedef struct X86PDPAE
3121	{
3122	/** PDE Array. */
3123	X86PDEPAE a[X86_PG_PAE_ENTRIES];
3124	} X86PDPAE;
3125	# ifndef VBOX_FOR_DTRACE_LIB
3126	AssertCompileSize(X86PDPAE, 4096);
3127	# endif
3128	/** Pointer to a PAE page directory. */
3129	typedef X86PDPAE *PX86PDPAE;
3130	/** Pointer to a const PAE page directory. */
3131	typedef const X86PDPAE *PCX86PDPAE;
3132	#endif /* !__ASSEMBLER__ */
3133
3134	/** The page shift to get the PAE PD index. */
3135	#define X86_PD_PAE_SHIFT 21
3136	/** The PAE PD index mask (apply to a shifted page address). */
3137	#define X86_PD_PAE_MASK 0x1ff
3138
3139
3140	/** @name Page Directory Pointer Table Entry (PAE)
3141	* @{
3142	*/
3143	/** Bit 0 - P - Present bit. */
3144	#define X86_PDPE_P RT_BIT_32(0)
3145	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
3146	#define X86_PDPE_RW RT_BIT_32(1)
3147	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
3148	#define X86_PDPE_US RT_BIT_32(2)
3149	/** Bit 3 - PWT - Page level write thru bit. */
3150	#define X86_PDPE_PWT RT_BIT_32(3)
3151	/** Bit 4 - PCD - Page level cache disable bit. */
3152	#define X86_PDPE_PCD RT_BIT_32(4)
3153	/** Bit 5 - A - Access bit. Long Mode only. */
3154	#define X86_PDPE_A RT_BIT_32(5)
3155	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
3156	#define X86_PDPE_LM_PS RT_BIT_32(7)
3157	/** Bits 9-11 - - Available for use to system software. */
3158	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3159	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3160	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
3161	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
3162	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
3163	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
3164	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
3165	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
3166	#define X86_PDPE_LM_NX RT_BIT_64(63)
3167	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
3168	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
3169	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
3170	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
3171	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
3172	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
3173	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
3174	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
3175
3176	#ifndef __ASSEMBLER__
3177
3178	/**
3179	* Page directory pointer table entry.
3180	*/
3181	typedef struct X86PDPEBITS
3182	{
3183	/** Flags whether(=1) or not the page is present. */
3184	uint32_t u1Present : 1;
3185	/** Chunk of reserved bits. */
3186	uint32_t u2Reserved : 2;
3187	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3188	uint32_t u1WriteThru : 1;
3189	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3190	uint32_t u1CacheDisable : 1;
3191	/** Chunk of reserved bits. */
3192	uint32_t u4Reserved : 4;
3193	/** Available for use to system software. */
3194	uint32_t u3Available : 3;
3195	/** Physical Page number of the next level - Low Part. Don't use! */
3196	uint32_t u20PageNoLow : 20;
3197	/** Physical Page number of the next level - High Part. Don't use! */
3198	uint32_t u20PageNoHigh : 20;
3199	/** MBZ bits */
3200	uint32_t u12Reserved : 12;
3201	} X86PDPEBITS;
3202	# ifndef VBOX_FOR_DTRACE_LIB
3203	AssertCompileSize(X86PDPEBITS, 8);
3204	# endif
3205	/** Pointer to a page directory pointer table entry. */
3206	typedef X86PDPEBITS *PX86PTPEBITS;
3207	/** Pointer to a const page directory pointer table entry. */
3208	typedef const X86PDPEBITS *PCX86PTPEBITS;
3209
3210	/**
3211	* Page directory pointer table entry. AMD64 version
3212	*/
3213	typedef struct X86PDPEAMD64BITS
3214	{
3215	/** Flags whether(=1) or not the page is present. */
3216	uint32_t u1Present : 1;
3217	/** Read(=0) / Write(=1) flag. */
3218	uint32_t u1Write : 1;
3219	/** User(=1) / Supervisor (=0) flag. */
3220	uint32_t u1User : 1;
3221	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3222	uint32_t u1WriteThru : 1;
3223	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3224	uint32_t u1CacheDisable : 1;
3225	/** Accessed flag.
3226	* Indicates that the page have been read or written to. */
3227	uint32_t u1Accessed : 1;
3228	/** Chunk of reserved bits. */
3229	uint32_t u3Reserved : 3;
3230	/** Available for use to system software. */
3231	uint32_t u3Available : 3;
3232	/** Physical Page number of the next level - Low Part. Don't use! */
3233	uint32_t u20PageNoLow : 20;
3234	/** Physical Page number of the next level - High Part. Don't use! */
3235	uint32_t u20PageNoHigh : 20;
3236	/** MBZ bits */
3237	uint32_t u11Reserved : 11;
3238	/** No Execute flag. */
3239	uint32_t u1NoExecute : 1;
3240	} X86PDPEAMD64BITS;
3241	# ifndef VBOX_FOR_DTRACE_LIB
3242	AssertCompileSize(X86PDPEAMD64BITS, 8);
3243	# endif
3244	/** Pointer to a page directory pointer table entry. */
3245	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3246	/** Pointer to a const page directory pointer table entry. */
3247	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3248
3249	/**
3250	* Page directory pointer table entry for 1GB page. (AMD64 only)
3251	*/
3252	typedef struct X86PDPE1GB
3253	{
3254	/** 0: Flags whether(=1) or not the page is present. */
3255	uint32_t u1Present : 1;
3256	/** 1: Read(=0) / Write(=1) flag. */
3257	uint32_t u1Write : 1;
3258	/** 2: User(=1) / Supervisor (=0) flag. */
3259	uint32_t u1User : 1;
3260	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3261	uint32_t u1WriteThru : 1;
3262	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3263	uint32_t u1CacheDisable : 1;
3264	/** 5: Accessed flag.
3265	* Indicates that the page have been read or written to. */
3266	uint32_t u1Accessed : 1;
3267	/** 6: Dirty flag for 1GB pages. */
3268	uint32_t u1Dirty : 1;
3269	/** 7: Indicates 1GB page if set. */
3270	uint32_t u1Size : 1;
3271	/** 8: Global 1GB page. */
3272	uint32_t u1Global: 1;
3273	/** 9-11: Available for use to system software. */
3274	uint32_t u3Available : 3;
3275	/** 12: PAT bit for 1GB page. */
3276	uint32_t u1PAT : 1;
3277	/** 13-29: MBZ bits. */
3278	uint32_t u17Reserved : 17;
3279	/** 30-31: Physical page number - Low Part. Don't use! */
3280	uint32_t u2PageNoLow : 2;
3281	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3282	uint32_t u20PageNoHigh : 20;
3283	/** 52-62: MBZ bits */
3284	uint32_t u11Reserved : 11;
3285	/** 63: No Execute flag. */
3286	uint32_t u1NoExecute : 1;
3287	} X86PDPE1GB;
3288	# ifndef VBOX_FOR_DTRACE_LIB
3289	AssertCompileSize(X86PDPE1GB, 8);
3290	# endif
3291	/** Pointer to a page directory pointer table entry for a 1GB page. */
3292	typedef X86PDPE1GB *PX86PDPE1GB;
3293	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3294	typedef const X86PDPE1GB *PCX86PDPE1GB;
3295
3296	/**
3297	* Page directory pointer table entry.
3298	*/
3299	typedef union X86PDPE
3300	{
3301	/** Unsigned integer view. */
3302	X86PGPAEUINT u;
3303	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3304	/** Normal view. */
3305	X86PDPEBITS n;
3306	/** AMD64 view. */
3307	X86PDPEAMD64BITS lm;
3308	/** AMD64 big view. */
3309	X86PDPE1GB b;
3310	# endif
3311	/** 8 bit unsigned integer view. */
3312	uint8_t au8[8];
3313	/** 16 bit unsigned integer view. */
3314	uint16_t au16[4];
3315	/** 32 bit unsigned integer view. */
3316	uint32_t au32[2];
3317	} X86PDPE;
3318	# ifndef VBOX_FOR_DTRACE_LIB
3319	AssertCompileSize(X86PDPE, 8);
3320	# endif
3321	/** Pointer to a page directory pointer table entry. */
3322	typedef X86PDPE *PX86PDPE;
3323	/** Pointer to a const page directory pointer table entry. */
3324	typedef const X86PDPE *PCX86PDPE;
3325
3326
3327	/**
3328	* Page directory pointer table.
3329	*/
3330	typedef struct X86PDPT
3331	{
3332	/** PDE Array. */
3333	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3334	} X86PDPT;
3335	# ifndef VBOX_FOR_DTRACE_LIB
3336	AssertCompileSize(X86PDPT, 4096);
3337	# endif
3338	/** Pointer to a page directory pointer table. */
3339	typedef X86PDPT *PX86PDPT;
3340	/** Pointer to a const page directory pointer table. */
3341	typedef const X86PDPT *PCX86PDPT;
3342
3343	#endif /* !__ASSEMBLER__ */
3344
3345	/** The page shift to get the PDPT index. */
3346	#define X86_PDPT_SHIFT 30
3347	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3348	#define X86_PDPT_MASK_PAE 0x3
3349	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3350	#define X86_PDPT_MASK_AMD64 0x1ff
3351
3352	/** @} */
3353
3354
3355	/** @name Page Map Level-4 Entry (Long Mode PAE)
3356	* @{
3357	*/
3358	/** Bit 0 - P - Present bit. */
3359	#define X86_PML4E_P RT_BIT_32(0)
3360	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3361	#define X86_PML4E_RW RT_BIT_32(1)
3362	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3363	#define X86_PML4E_US RT_BIT_32(2)
3364	/** Bit 3 - PWT - Page level write thru bit. */
3365	#define X86_PML4E_PWT RT_BIT_32(3)
3366	/** Bit 4 - PCD - Page level cache disable bit. */
3367	#define X86_PML4E_PCD RT_BIT_32(4)
3368	/** Bit 5 - A - Access bit. */
3369	#define X86_PML4E_A RT_BIT_32(5)
3370	/** Bits 9-11 - - Available for use to system software. */
3371	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3372	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3373	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3374	/** Bits 8, 7 - - MBZ bits when NX is active. */
3375	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3376	/** Bits 63, 7 - - MBZ bits when no NX. */
3377	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3378	/** Bits 63 - NX - PAE - No execution flag. */
3379	#define X86_PML4E_NX RT_BIT_64(63)
3380
3381	#ifndef __ASSEMBLER__
3382
3383	/**
3384	* Page Map Level-4 Entry
3385	*/
3386	typedef struct X86PML4EBITS
3387	{
3388	/** Flags whether(=1) or not the page is present. */
3389	uint32_t u1Present : 1;
3390	/** Read(=0) / Write(=1) flag. */
3391	uint32_t u1Write : 1;
3392	/** User(=1) / Supervisor (=0) flag. */
3393	uint32_t u1User : 1;
3394	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3395	uint32_t u1WriteThru : 1;
3396	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3397	uint32_t u1CacheDisable : 1;
3398	/** Accessed flag.
3399	* Indicates that the page have been read or written to. */
3400	uint32_t u1Accessed : 1;
3401	/** Chunk of reserved bits. */
3402	uint32_t u3Reserved : 3;
3403	/** Available for use to system software. */
3404	uint32_t u3Available : 3;
3405	/** Physical Page number of the next level - Low Part. Don't use! */
3406	uint32_t u20PageNoLow : 20;
3407	/** Physical Page number of the next level - High Part. Don't use! */
3408	uint32_t u20PageNoHigh : 20;
3409	/** MBZ bits */
3410	uint32_t u11Reserved : 11;
3411	/** No Execute flag. */
3412	uint32_t u1NoExecute : 1;
3413	} X86PML4EBITS;
3414	# ifndef VBOX_FOR_DTRACE_LIB
3415	AssertCompileSize(X86PML4EBITS, 8);
3416	# endif
3417	/** Pointer to a page map level-4 entry. */
3418	typedef X86PML4EBITS *PX86PML4EBITS;
3419	/** Pointer to a const page map level-4 entry. */
3420	typedef const X86PML4EBITS *PCX86PML4EBITS;
3421
3422	/**
3423	* Page Map Level-4 Entry.
3424	*/
3425	typedef union X86PML4E
3426	{
3427	/** Unsigned integer view. */
3428	X86PGPAEUINT u;
3429	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3430	/** Normal view. */
3431	X86PML4EBITS n;
3432	# endif
3433	/** 8 bit unsigned integer view. */
3434	uint8_t au8[8];
3435	/** 16 bit unsigned integer view. */
3436	uint16_t au16[4];
3437	/** 32 bit unsigned integer view. */
3438	uint32_t au32[2];
3439	} X86PML4E;
3440	# ifndef VBOX_FOR_DTRACE_LIB
3441	AssertCompileSize(X86PML4E, 8);
3442	# endif
3443	/** Pointer to a page map level-4 entry. */
3444	typedef X86PML4E *PX86PML4E;
3445	/** Pointer to a const page map level-4 entry. */
3446	typedef const X86PML4E *PCX86PML4E;
3447
3448
3449	/**
3450	* Page Map Level-4.
3451	*/
3452	typedef struct X86PML4
3453	{
3454	/** PDE Array. */
3455	X86PML4E a[X86_PG_PAE_ENTRIES];
3456	} X86PML4;
3457	# ifndef VBOX_FOR_DTRACE_LIB
3458	AssertCompileSize(X86PML4, 4096);
3459	# endif
3460	/** Pointer to a page map level-4. */
3461	typedef X86PML4 *PX86PML4;
3462	/** Pointer to a const page map level-4. */
3463	typedef const X86PML4 *PCX86PML4;
3464
3465	#endif /* !__ASSEMBLER__ */
3466
3467	/** The page shift to get the PML4 index. */
3468	#define X86_PML4_SHIFT 39
3469	/** The PML4 index mask (apply to a shifted page address). */
3470	#define X86_PML4_MASK 0x1ff
3471
3472	/** @} */
3473
3474	/** @} */
3475
3476	/**
3477	* Intel PCID invalidation types.
3478	*/
3479	/** Individual address invalidation. */
3480	#define X86_INVPCID_TYPE_INDV_ADDR 0
3481	/** Single-context invalidation. */
3482	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3483	/** All-context including globals invalidation. */
3484	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3485	/** All-context excluding globals invalidation. */
3486	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3487	/** The maximum valid invalidation type value. */
3488	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3489
3490
3491	/** @name Special FPU integer values.
3492	* @{ */
3493	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3494	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3495	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3496	/** @} */
3497
3498	#ifndef __ASSEMBLER__
3499
3500	/**
3501	* 32-bit protected mode FSTENV image.
3502	*/
3503	typedef struct X86FSTENV32P
3504	{
3505	uint16_t FCW; /*< 0x00 /
3506	uint16_t padding1; /*< 0x02 /
3507	uint16_t FSW; /*< 0x04 /
3508	uint16_t padding2; /*< 0x06 /
3509	uint16_t FTW; /*< 0x08 /
3510	uint16_t padding3; /*< 0x0a /
3511	uint32_t FPUIP; /*< 0x0c /
3512	uint16_t FPUCS; /*< 0x10 /
3513	uint16_t FOP; /*< 0x12 /
3514	uint32_t FPUDP; /*< 0x14 /
3515	uint16_t FPUDS; /*< 0x18 /
3516	uint16_t padding4; /*< 0x1a /
3517	} X86FSTENV32P;
3518	# ifndef VBOX_FOR_DTRACE_LIB
3519	AssertCompileSize(X86FSTENV32P, 0x1c);
3520	# endif
3521	/** Pointer to a 32-bit protected mode FSTENV image. */
3522	typedef X86FSTENV32P *PX86FSTENV32P;
3523	/** Pointer to a const 32-bit protected mode FSTENV image. */
3524	typedef X86FSTENV32P const *PCX86FSTENV32P;
3525
3526
3527	/**
3528	* 80-bit MMX/FPU register type.
3529	*/
3530	typedef struct X86FPUMMX
3531	{
3532	uint8_t reg[10];
3533	} X86FPUMMX;
3534	# ifndef VBOX_FOR_DTRACE_LIB
3535	AssertCompileSize(X86FPUMMX, 10);
3536	# endif
3537	/** Pointer to a 80-bit MMX/FPU register type. */
3538	typedef X86FPUMMX *PX86FPUMMX;
3539	/** Pointer to a const 80-bit MMX/FPU register type. */
3540	typedef const X86FPUMMX *PCX86FPUMMX;
3541
3542	/** FPU (x87) register. */
3543	typedef union X86FPUREG
3544	{
3545	/** MMX view. */
3546	uint64_t mmx;
3547	/** FPU view - todo. */
3548	X86FPUMMX fpu;
3549	/** Extended precision floating point view. */
3550	RTFLOAT80U r80;
3551	/** Extended precision floating point view v2 */
3552	RTFLOAT80U2 r80Ex;
3553	/** 8-bit view. */
3554	uint8_t au8[16];
3555	/** 16-bit view. */
3556	uint16_t au16[8];
3557	/** 32-bit view. */
3558	uint32_t au32[4];
3559	/** 64-bit view. */
3560	uint64_t au64[2];
3561	/** 128-bit view. (yeah, very helpful) */
3562	uint128_t au128[1];
3563	} X86FPUREG;
3564	# ifndef VBOX_FOR_DTRACE_LIB
3565	AssertCompileSize(X86FPUREG, 16);
3566	# endif
3567	/** Pointer to a FPU register. */
3568	typedef X86FPUREG *PX86FPUREG;
3569	/** Pointer to a const FPU register. */
3570	typedef X86FPUREG const *PCX86FPUREG;
3571
3572	/** FPU (x87) register - v2 with correct size. */
3573	# pragma pack(1)
3574	typedef union X86FPUREG2
3575	{
3576	/** MMX view. */
3577	uint64_t mmx;
3578	/** FPU view - todo. */
3579	X86FPUMMX fpu;
3580	/** Extended precision floating point view. */
3581	RTFLOAT80U r80;
3582	/** 8-bit view. */
3583	uint8_t au8[10];
3584	/** 16-bit view. */
3585	uint16_t au16[5];
3586	/** 32-bit view. */
3587	uint32_t au32[2];
3588	/** 64-bit view. */
3589	uint64_t au64[1];
3590	} X86FPUREG2;
3591	# pragma pack()
3592	# ifndef VBOX_FOR_DTRACE_LIB
3593	AssertCompileSize(X86FPUREG2, 10);
3594	# endif
3595	/** Pointer to a FPU register - v2. */
3596	typedef X86FPUREG2 *PX86FPUREG2;
3597	/** Pointer to a const FPU register - v2. */
3598	typedef X86FPUREG2 const *PCX86FPUREG2;
3599
3600	/**
3601	* XMM register union.
3602	*/
3603	typedef union X86XMMREG
3604	{
3605	/** XMM Register view. */
3606	uint128_t xmm;
3607	/** 8-bit view. */
3608	uint8_t au8[16];
3609	/** 16-bit view. */
3610	uint16_t au16[8];
3611	/** 32-bit view. */
3612	uint32_t au32[4];
3613	/** 64-bit view. */
3614	uint64_t au64[2];
3615	/** Signed 8-bit view. */
3616	int8_t ai8[16];
3617	/** Signed 16-bit view. */
3618	int16_t ai16[8];
3619	/** Signed 32-bit view. */
3620	int32_t ai32[4];
3621	/** Signed 64-bit view. */
3622	int64_t ai64[2];
3623	/** 128-bit view. (yeah, very helpful) */
3624	uint128_t au128[1];
3625	/** Single precision floating point view. */
3626	RTFLOAT32U ar32[4];
3627	/** Double precision floating point view. */
3628	RTFLOAT64U ar64[2];
3629	# ifndef VBOX_FOR_DTRACE_LIB
3630	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3631	RTUINT128U uXmm;
3632	# endif
3633	} X86XMMREG;
3634	# ifndef VBOX_FOR_DTRACE_LIB
3635	AssertCompileSize(X86XMMREG, 16);
3636	# endif
3637	/** Pointer to an XMM register state. */
3638	typedef X86XMMREG *PX86XMMREG;
3639	/** Pointer to a const XMM register state. */
3640	typedef X86XMMREG const *PCX86XMMREG;
3641
3642	/**
3643	* YMM register union.
3644	*/
3645	typedef union X86YMMREG
3646	{
3647	/** YMM register view. */
3648	RTUINT256U ymm;
3649	/** 8-bit view. */
3650	uint8_t au8[32];
3651	/** 16-bit view. */
3652	uint16_t au16[16];
3653	/** 32-bit view. */
3654	uint32_t au32[8];
3655	/** 64-bit view. */
3656	uint64_t au64[4];
3657	/** Signed 8-bit view. */
3658	int8_t ai8[32];
3659	/** Signed 16-bit view. */
3660	int16_t ai16[16];
3661	/** Signed 32-bit view. */
3662	int32_t ai32[8];
3663	/** Signed 64-bit view. */
3664	int64_t ai64[4];
3665	/** 128-bit view. (yeah, very helpful) */
3666	uint128_t au128[2];
3667	/** Single precision floating point view. */
3668	RTFLOAT32U ar32[8];
3669	/** Double precision floating point view. */
3670	RTFLOAT64U ar64[4];
3671	/** XMM sub register view. */
3672	X86XMMREG aXmm[2];
3673	} X86YMMREG;
3674	# ifndef VBOX_FOR_DTRACE_LIB
3675	AssertCompileSize(X86YMMREG, 32);
3676	# endif
3677	/** Pointer to an YMM register state. */
3678	typedef X86YMMREG *PX86YMMREG;
3679	/** Pointer to a const YMM register state. */
3680	typedef X86YMMREG const *PCX86YMMREG;
3681
3682	/**
3683	* ZMM register union.
3684	*/
3685	typedef union X86ZMMREG
3686	{
3687	/** 8-bit view. */
3688	uint8_t au8[64];
3689	/** 16-bit view. */
3690	uint16_t au16[32];
3691	/** 32-bit view. */
3692	uint32_t au32[16];
3693	/** 64-bit view. */
3694	uint64_t au64[8];
3695	/** Signed 8-bit view. */
3696	int8_t ai8[64];
3697	/** Signed 16-bit view. */
3698	int16_t ai16[32];
3699	/** Signed 32-bit view. */
3700	int32_t ai32[16];
3701	/** Signed 64-bit view. */
3702	int64_t ai64[8];
3703	/** 128-bit view. (yeah, very helpful) */
3704	uint128_t au128[4];
3705	/** Single precision floating point view. */
3706	RTFLOAT32U ar32[16];
3707	/** Double precision floating point view. */
3708	RTFLOAT64U ar64[8];
3709	/** XMM sub register view. */
3710	X86XMMREG aXmm[4];
3711	/** YMM sub register view. */
3712	X86YMMREG aYmm[2];
3713	} X86ZMMREG;
3714	# ifndef VBOX_FOR_DTRACE_LIB
3715	AssertCompileSize(X86ZMMREG, 64);
3716	# endif
3717	/** Pointer to an ZMM register state. */
3718	typedef X86ZMMREG *PX86ZMMREG;
3719	/** Pointer to a const ZMM register state. */
3720	typedef X86ZMMREG const *PCX86ZMMREG;
3721
3722
3723	/**
3724	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3725	*/
3726	# pragma pack(1)
3727	typedef struct X86FPUSTATE
3728	{
3729	/** 0x00 - Control word. */
3730	uint16_t FCW;
3731	/** 0x02 - Alignment word */
3732	uint16_t Dummy1;
3733	/** 0x04 - Status word. */
3734	uint16_t FSW;
3735	/** 0x06 - Alignment word */
3736	uint16_t Dummy2;
3737	/** 0x08 - Tag word */
3738	uint16_t FTW;
3739	/** 0x0a - Alignment word */
3740	uint16_t Dummy3;
3741
3742	/** 0x0c - Instruction pointer. */
3743	uint32_t FPUIP;
3744	/** 0x10 - Code selector. */
3745	uint16_t CS;
3746	/** 0x12 - Opcode. */
3747	uint16_t FOP;
3748	/** 0x14 - Data pointer. */
3749	uint32_t FPUOO;
3750	/** 0x18 - FOS. */
3751	uint16_t FPUOS;
3752	/** 0x0a - Alignment word */
3753	uint16_t Dummy4;
3754	/** 0x1c - FPU register. */
3755	X86FPUREG2 regs[8];
3756	} X86FPUSTATE;
3757	# pragma pack()
3758	AssertCompileSize(X86FPUSTATE, 108);
3759	/** Pointer to a FPU state. */
3760	typedef X86FPUSTATE *PX86FPUSTATE;
3761	/** Pointer to a const FPU state. */
3762	typedef const X86FPUSTATE *PCX86FPUSTATE;
3763
3764	/**
3765	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3766	*/
3767	# pragma pack(1)
3768	typedef struct X86FXSTATE
3769	{
3770	/** 0x00 - Control word. */
3771	uint16_t FCW;
3772	/** 0x02 - Status word. */
3773	uint16_t FSW;
3774	/** 0x04 - Tag word. (The upper byte is always zero.) */
3775	uint16_t FTW;
3776	/** 0x06 - Opcode. */
3777	uint16_t FOP;
3778	/** 0x08 - Instruction pointer. */
3779	uint32_t FPUIP;
3780	/** 0x0c - Code selector. */
3781	uint16_t CS;
3782	uint16_t Rsrvd1;
3783	/** 0x10 - Data pointer. */
3784	uint32_t FPUDP;
3785	/** 0x14 - Data segment */
3786	uint16_t DS;
3787	/** 0x16 */
3788	uint16_t Rsrvd2;
3789	/** 0x18 */
3790	uint32_t MXCSR;
3791	/** 0x1c */
3792	uint32_t MXCSR_MASK;
3793	/** 0x20 - FPU registers. */
3794	X86FPUREG aRegs[8];
3795	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3796	X86XMMREG aXMM[16];
3797	/* - offset 416 - */
3798	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3799	/* - offset 464 - Software usable reserved bits. */
3800	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3801	} X86FXSTATE;
3802	# pragma pack()
3803	/** Pointer to a FPU Extended state. */
3804	typedef X86FXSTATE *PX86FXSTATE;
3805	/** Pointer to a const FPU Extended state. */
3806	typedef const X86FXSTATE *PCX86FXSTATE;
3807
3808	#endif /* !__ASSEMBLER__ */
3809
3810
3811	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3812	* magic. Don't forget to update x86.mac if you change this! */
3813	#define X86_OFF_FXSTATE_RSVD 0x1d0
3814	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3815	* forget to update x86.mac if you change this!
3816	* @todo r=bird: This has nothing what-so-ever to do here.... */
3817	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3818	#ifndef VBOX_FOR_DTRACE_LIB
3819	AssertCompileSize(X86FXSTATE, 512);
3820	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3821	#endif
3822
3823	/** @name FPU status word flags.
3824	* @{ */
3825	/** Exception Flag: Invalid operation. */
3826	#define X86_FSW_IE RT_BIT_32(0)
3827	#define X86_FSW_IE_BIT 0
3828	/** Exception Flag: Denormalized operand. */
3829	#define X86_FSW_DE RT_BIT_32(1)
3830	#define X86_FSW_DE_BIT 1
3831	/** Exception Flag: Zero divide. */
3832	#define X86_FSW_ZE RT_BIT_32(2)
3833	#define X86_FSW_ZE_BIT 2
3834	/** Exception Flag: Overflow. */
3835	#define X86_FSW_OE RT_BIT_32(3)
3836	#define X86_FSW_OE_BIT 3
3837	/** Exception Flag: Underflow. */
3838	#define X86_FSW_UE RT_BIT_32(4)
3839	#define X86_FSW_UE_BIT 4
3840	/** Exception Flag: Precision. */
3841	#define X86_FSW_PE RT_BIT_32(5)
3842	#define X86_FSW_PE_BIT 5
3843	/** Stack fault. */
3844	#define X86_FSW_SF RT_BIT_32(6)
3845	#define X86_FSW_SF_BIT 6
3846	/** Error summary status. */
3847	#define X86_FSW_ES RT_BIT_32(7)
3848	#define X86_FSW_ES_BIT 7
3849	/** Mask of exceptions flags, excluding the summary bit. */
3850	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3851	/** Mask of exceptions flags, including the summary bit. */
3852	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3853	/** Condition code 0. */
3854	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3855	#define X86_FSW_C0_BIT 8
3856	/** Condition code 1. */
3857	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3858	#define X86_FSW_C1_BIT 9
3859	/** Condition code 2. */
3860	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3861	#define X86_FSW_C2_BIT 10
3862	/** Top of the stack mask. */
3863	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3864	/** TOP shift value. */
3865	#define X86_FSW_TOP_SHIFT 11
3866	/** Mask for getting TOP value after shifting it right. */
3867	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3868	/** Get the TOP value. */
3869	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3870	/** Get the TOP value offsetted by a_iSt (0-7). */
3871	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3872	/** Condition code 3. */
3873	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3874	#define X86_FSW_C3_BIT 14
3875	/** Mask of exceptions flags, including the summary bit. */
3876	#define X86_FSW_C_MASK UINT16_C(0x4700)
3877	/** FPU busy. */
3878	#define X86_FSW_B RT_BIT_32(15)
3879	/** For use with FPREM and FPREM1. */
3880	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3881	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3882	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3883	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3884	/** For use with FPREM and FPREM1. */
3885	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3886	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3887	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3888	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3889	/** @} */
3890
3891
3892	/** @name FPU control word flags.
3893	* @{ */
3894	/** Exception Mask: Invalid operation. */
3895	#define X86_FCW_IM RT_BIT_32(0)
3896	#define X86_FCW_IM_BIT 0
3897	/** Exception Mask: Denormalized operand. */
3898	#define X86_FCW_DM RT_BIT_32(1)
3899	#define X86_FCW_DM_BIT 1
3900	/** Exception Mask: Zero divide. */
3901	#define X86_FCW_ZM RT_BIT_32(2)
3902	#define X86_FCW_ZM_BIT 2
3903	/** Exception Mask: Overflow. */
3904	#define X86_FCW_OM RT_BIT_32(3)
3905	#define X86_FCW_OM_BIT 3
3906	/** Exception Mask: Underflow. */
3907	#define X86_FCW_UM RT_BIT_32(4)
3908	#define X86_FCW_UM_BIT 4
3909	/** Exception Mask: Precision. */
3910	#define X86_FCW_PM RT_BIT_32(5)
3911	#define X86_FCW_PM_BIT 5
3912	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3913	* @remarks This includes reserved bit 6. */
3914	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3915	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3916	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3917	/** Precision control mask. */
3918	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3919	/** Precision control shift. */
3920	#define X86_FCW_PC_SHIFT 8
3921	/** Precision control: 24-bit. */
3922	#define X86_FCW_PC_24 UINT16_C(0x0000)
3923	/** Precision control: Reserved. */
3924	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3925	/** Precision control: 53-bit. */
3926	#define X86_FCW_PC_53 UINT16_C(0x0200)
3927	/** Precision control: 64-bit. */
3928	#define X86_FCW_PC_64 UINT16_C(0x0300)
3929	/** Rounding control mask. */
3930	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3931	/** Rounding control shift. */
3932	#define X86_FCW_RC_SHIFT 10
3933	/** Rounding control: To nearest. */
3934	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3935	/** Rounding control: Down. */
3936	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3937	/** Rounding control: Up. */
3938	#define X86_FCW_RC_UP UINT16_C(0x0800)
3939	/** Rounding control: Towards zero. */
3940	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3941	/** Infinity control mask - obsolete, 8087 & 287 only. */
3942	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3943	/** Infinity control: Affine - positive infinity is distictly different from
3944	* negative infinity.
3945	* @note 8087, 287 only */
3946	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3947	/** Infinity control: Projective - positive and negative infinity are the
3948	* same (sign ignored).
3949	* @note 8087, 287 only */
3950	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3951	/** Bits which should be zero, apparently. */
3952	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3953	/** @} */
3954
3955	/** @name SSE MXCSR
3956	* @{ */
3957	/** Exception Flag: Invalid operation. */
3958	#define X86_MXCSR_IE RT_BIT_32(0)
3959	#define X86_MXCSR_IE_BIT 0
3960	/** Exception Flag: Denormalized operand. */
3961	#define X86_MXCSR_DE RT_BIT_32(1)
3962	#define X86_MXCSR_DE_BIT 1
3963	/** Exception Flag: Zero divide. */
3964	#define X86_MXCSR_ZE RT_BIT_32(2)
3965	#define X86_MXCSR_ZE_BIT 2
3966	/** Exception Flag: Overflow. */
3967	#define X86_MXCSR_OE RT_BIT_32(3)
3968	#define X86_MXCSR_OE_BIT 3
3969	/** Exception Flag: Underflow. */
3970	#define X86_MXCSR_UE RT_BIT_32(4)
3971	#define X86_MXCSR_UE_BIT 4
3972	/** Exception Flag: Precision. */
3973	#define X86_MXCSR_PE RT_BIT_32(5)
3974	#define X86_MXCSR_PE_BIT 5
3975	/** Exception Flags: mask */
3976	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3977
3978	/** Denormals are zero. */
3979	#define X86_MXCSR_DAZ RT_BIT_32(6)
3980	#define X86_MXCSR_DAZ_BIT 6
3981
3982	/** Exception Mask: Invalid operation. */
3983	#define X86_MXCSR_IM RT_BIT_32(7)
3984	#define X86_MXCSR_IM_BIT 7
3985	/** Exception Mask: Denormalized operand. */
3986	#define X86_MXCSR_DM RT_BIT_32(8)
3987	#define X86_MXCSR_DM_BIT 8
3988	/** Exception Mask: Zero divide. */
3989	#define X86_MXCSR_ZM RT_BIT_32(9)
3990	#define X86_MXCSR_ZM_BIT 9
3991	/** Exception Mask: Overflow. */
3992	#define X86_MXCSR_OM RT_BIT_32(10)
3993	#define X86_MXCSR_OM_BIT 10
3994	/** Exception Mask: Underflow. */
3995	#define X86_MXCSR_UM RT_BIT_32(11)
3996	#define X86_MXCSR_UM_BIT 11
3997	/** Exception Mask: Precision. */
3998	#define X86_MXCSR_PM RT_BIT_32(12)
3999	#define X86_MXCSR_PM_BIT 12
4000	/** Exception Mask: mask. */
4001	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
4002	/** Exception Mask: shift. */
4003	#define X86_MXCSR_XCPT_MASK_SHIFT 7
4004
4005	/** Rounding control mask. */
4006	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
4007	/** Rounding control shift. */
4008	#define X86_MXCSR_RC_SHIFT 13
4009	/** Rounding control: To nearest. */
4010	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
4011	/** Rounding control: Down. */
4012	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
4013	/** Rounding control: Up. */
4014	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
4015	/** Rounding control: Towards zero. */
4016	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
4017
4018	/** Flush-to-zero for masked underflow. */
4019	#define X86_MXCSR_FZ RT_BIT_32(15)
4020	#define X86_MXCSR_FZ_BIT 15
4021
4022	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
4023	#define X86_MXCSR_MM RT_BIT_32(17)
4024	#define X86_MXCSR_MM_BIT 17
4025	/** Bits which should be zero, apparently. */
4026	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
4027	/** @} */
4028
4029	#ifndef __ASSEMBLER__
4030
4031	/**
4032	* XSAVE header.
4033	*/
4034	typedef struct X86XSAVEHDR
4035	{
4036	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
4037	uint64_t bmXState;
4038	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
4039	uint64_t bmXComp;
4040	/** Reserved for furture extensions, probably MBZ. */
4041	uint64_t au64Reserved[6];
4042	} X86XSAVEHDR;
4043	# ifndef VBOX_FOR_DTRACE_LIB
4044	AssertCompileSize(X86XSAVEHDR, 64);
4045	# endif
4046	/** Pointer to an XSAVE header. */
4047	typedef X86XSAVEHDR *PX86XSAVEHDR;
4048	/** Pointer to a const XSAVE header. */
4049	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
4050
4051
4052	/**
4053	* The high 128-bit YMM register state (XSAVE_C_YMM).
4054	* (The lower 128-bits being in X86FXSTATE.)
4055	*/
4056	typedef struct X86XSAVEYMMHI
4057	{
4058	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
4059	X86XMMREG aYmmHi[16];
4060	} X86XSAVEYMMHI;
4061	# ifndef VBOX_FOR_DTRACE_LIB
4062	AssertCompileSize(X86XSAVEYMMHI, 256);
4063	# endif
4064	/** Pointer to a high 128-bit YMM register state. */
4065	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
4066	/** Pointer to a const high 128-bit YMM register state. */
4067	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
4068
4069	/**
4070	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
4071	*/
4072	typedef struct X86XSAVEBNDREGS
4073	{
4074	/** Array of registers (BND0...BND3). */
4075	struct
4076	{
4077	/** Lower bound. */
4078	uint64_t uLowerBound;
4079	/** Upper bound. */
4080	uint64_t uUpperBound;
4081	} aRegs[4];
4082	} X86XSAVEBNDREGS;
4083	# ifndef VBOX_FOR_DTRACE_LIB
4084	AssertCompileSize(X86XSAVEBNDREGS, 64);
4085	# endif
4086	/** Pointer to a MPX bound register state. */
4087	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
4088	/** Pointer to a const MPX bound register state. */
4089	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
4090
4091	/**
4092	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
4093	*/
4094	typedef struct X86XSAVEBNDCFG
4095	{
4096	uint64_t fConfig;
4097	uint64_t fStatus;
4098	} X86XSAVEBNDCFG;
4099	# ifndef VBOX_FOR_DTRACE_LIB
4100	AssertCompileSize(X86XSAVEBNDCFG, 16);
4101	# endif
4102	/** Pointer to a MPX bound config and status register state. */
4103	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
4104	/** Pointer to a const MPX bound config and status register state. */
4105	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
4106
4107	/**
4108	* AVX-512 opmask state (XSAVE_C_OPMASK).
4109	*/
4110	typedef struct X86XSAVEOPMASK
4111	{
4112	/** The K0..K7 values. */
4113	uint64_t aKRegs[8];
4114	} X86XSAVEOPMASK;
4115	# ifndef VBOX_FOR_DTRACE_LIB
4116	AssertCompileSize(X86XSAVEOPMASK, 64);
4117	# endif
4118	/** Pointer to a AVX-512 opmask state. */
4119	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
4120	/** Pointer to a const AVX-512 opmask state. */
4121	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
4122
4123	/**
4124	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
4125	*/
4126	typedef struct X86XSAVEZMMHI256
4127	{
4128	/** Upper 256-bits of ZMM0-15. */
4129	X86YMMREG aHi256Regs[16];
4130	} X86XSAVEZMMHI256;
4131	# ifndef VBOX_FOR_DTRACE_LIB
4132	AssertCompileSize(X86XSAVEZMMHI256, 512);
4133	# endif
4134	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
4135	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
4136	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
4137	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
4138
4139	/**
4140	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
4141	*/
4142	typedef struct X86XSAVEZMM16HI
4143	{
4144	/** ZMM16 thru ZMM31. */
4145	X86ZMMREG aRegs[16];
4146	} X86XSAVEZMM16HI;
4147	# ifndef VBOX_FOR_DTRACE_LIB
4148	AssertCompileSize(X86XSAVEZMM16HI, 1024);
4149	# endif
4150	/** Pointer to a state comprising ZMM16-32. */
4151	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
4152	/** Pointer to a const state comprising ZMM16-32. */
4153	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
4154
4155	/**
4156	* AMD Light weight profiling state (XSAVE_C_LWP).
4157	*
4158	* We probably won't play with this as AMD seems to be dropping from their "zen"
4159	* processor micro architecture.
4160	*/
4161	typedef struct X86XSAVELWP
4162	{
4163	/** Details when needed. */
4164	uint64_t auLater[128/8];
4165	} X86XSAVELWP;
4166	# ifndef VBOX_FOR_DTRACE_LIB
4167	AssertCompileSize(X86XSAVELWP, 128);
4168	# endif
4169
4170
4171	/**
4172	* x86 FPU/SSE/AVX/XXXX state.
4173	*
4174	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
4175	* changes to this structure.
4176	*/
4177	typedef struct X86XSAVEAREA
4178	{
4179	/** The x87 and SSE region (or legacy region if you like). */
4180	X86FXSTATE x87;
4181	/** The XSAVE header. */
4182	X86XSAVEHDR Hdr;
4183	/** Beyond the header, there isn't really a fixed layout, but we can
4184	generally assume the YMM (AVX) register extensions are present and
4185	follows immediately. */
4186	union
4187	{
4188	/** The high 128-bit AVX registers for easy access by IEM.
4189	* @note This ASSUMES they will always be here... */
4190	X86XSAVEYMMHI YmmHi;
4191
4192	/** This is a typical layout on intel CPUs (good for debuggers). */
4193	struct
4194	{
4195	X86XSAVEYMMHI YmmHi;
4196	X86XSAVEBNDREGS BndRegs;
4197	X86XSAVEBNDCFG BndCfg;
4198	uint8_t abFudgeToMatchDocs[0xB0];
4199	X86XSAVEOPMASK Opmask;
4200	X86XSAVEZMMHI256 ZmmHi256;
4201	X86XSAVEZMM16HI Zmm16Hi;
4202	} Intel;
4203
4204	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
4205	struct
4206	{
4207	X86XSAVEYMMHI YmmHi;
4208	X86XSAVELWP Lwp;
4209	} AmdBd;
4210
4211	/** To enbling static deployments that have a reasonable chance of working for
4212	* the next 3-6 CPU generations without running short on space, we allocate a
4213	* lot of extra space here, making the structure a round 8KB in size. This
4214	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
4215	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
4216	uint8_t ab[8192 - 512 - 64];
4217	} u;
4218	} X86XSAVEAREA;
4219	# ifndef VBOX_FOR_DTRACE_LIB
4220	AssertCompileSize(X86XSAVEAREA, 8192);
4221	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
4222	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
4223	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
4224	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
4225	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
4226	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
4227	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
4228	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
4229	# endif
4230	/** Pointer to a XSAVE area. */
4231	typedef X86XSAVEAREA *PX86XSAVEAREA;
4232	/** Pointer to a const XSAVE area. */
4233	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
4234
4235	#endif /* __ASSEMBLER__ */
4236
4237
4238	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
4239	* @{ */
4240	/** Bit 0 - x87 - Legacy FPU state (bit number) */
4241	#define XSAVE_C_X87_BIT 0
4242	/** Bit 0 - x87 - Legacy FPU state. */
4243	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4244	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4245	#define XSAVE_C_SSE_BIT 1
4246	/** Bit 1 - SSE - 128-bit SSE state. */
4247	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4248	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4249	#define XSAVE_C_YMM_BIT 2
4250	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4251	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4252	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4253	#define XSAVE_C_BNDREGS_BIT 3
4254	/** Bit 3 - BNDREGS - MPX bound register state. */
4255	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4256	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4257	#define XSAVE_C_BNDCSR_BIT 4
4258	/** Bit 4 - BNDCSR - MPX bound config and status state. */
4259	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4260	/** Bit 5 - Opmask - opmask state (bit number). */
4261	#define XSAVE_C_OPMASK_BIT 5
4262	/** Bit 5 - Opmask - opmask state. */
4263	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4264	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4265	#define XSAVE_C_ZMM_HI256_BIT 6
4266	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4267	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4268	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4269	#define XSAVE_C_ZMM_16HI_BIT 7
4270	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4271	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4272	/** Bit 9 - PKRU - Protection-key state (bit number). */
4273	#define XSAVE_C_PKRU_BIT 9
4274	/** Bit 9 - PKRU - Protection-key state. */
4275	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4276	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4277	#define XSAVE_C_LWP_BIT 62
4278	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4279	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4280	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4281	#define XSAVE_C_X_BIT 63
4282	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4283	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4284	/** @} */
4285
4286
4287
4288	/** @name Selector Descriptor
4289	* @{
4290	*/
4291
4292	#ifndef __ASSEMBLER__
4293	# ifndef VBOX_FOR_DTRACE_LIB
4294	/**
4295	* Descriptor attributes (as seen by VT-x).
4296	*/
4297	typedef struct X86DESCATTRBITS
4298	{
4299	/** 00 - Segment Type. */
4300	unsigned u4Type : 4;
4301	/** 04 - Descriptor Type. System(=0) or code/data selector */
4302	unsigned u1DescType : 1;
4303	/** 05 - Descriptor Privilege level. */
4304	unsigned u2Dpl : 2;
4305	/** 07 - Flags selector present(=1) or not. */
4306	unsigned u1Present : 1;
4307	/** 08 - Segment limit 16-19. */
4308	unsigned u4LimitHigh : 4;
4309	/** 0c - Available for system software. */
4310	unsigned u1Available : 1;
4311	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4312	unsigned u1Long : 1;
4313	/** 0e - This flags meaning depends on the segment type. Try make sense out
4314	* of the intel manual yourself. */
4315	unsigned u1DefBig : 1;
4316	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
4317	* clear byte. */
4318	unsigned u1Granularity : 1;
4319	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4320	unsigned u1Unusable : 1;
4321	} X86DESCATTRBITS;
4322	# endif /* !VBOX_FOR_DTRACE_LIB */
4323	#endif /* !__ASSEMBLER__ */
4324
4325	/** @name X86DESCATTR masks
4326	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4327	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4328	* @{ */
4329	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4330	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4331	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4332	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4333	#define X86DESCATTR_P UINT32_C(0x00000080)
4334	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4335	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4336	#define X86DESCATTR_L UINT32_C(0x00002000)
4337	#define X86DESCATTR_D UINT32_C(0x00004000)
4338	#define X86DESCATTR_G UINT32_C(0x00008000)
4339	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4340	/** @} */
4341
4342
4343	#ifndef __ASSEMBLER__
4344	# pragma pack(1)
4345	typedef union X86DESCATTR
4346	{
4347	/** Unsigned integer view. */
4348	uint32_t u;
4349	# ifndef VBOX_FOR_DTRACE_LIB
4350	/** Normal view. */
4351	X86DESCATTRBITS n;
4352	# endif
4353	} X86DESCATTR;
4354	# pragma pack()
4355	/** Pointer to descriptor attributes. */
4356	typedef X86DESCATTR *PX86DESCATTR;
4357	/** Pointer to const descriptor attributes. */
4358	typedef const X86DESCATTR *PCX86DESCATTR;
4359	#endif /* !__ASSEMBLER__ */
4360
4361	#ifndef VBOX_FOR_DTRACE_LIB
4362
4363	#ifndef __ASSEMBLER__
4364	/**
4365	* Generic descriptor table entry
4366	*/
4367	# pragma pack(1)
4368	typedef struct X86DESCGENERIC
4369	{
4370	/** 00 - Limit - Low word. */
4371	unsigned u16LimitLow : 16;
4372	/** 10 - Base address - low word.
4373	* Don't try set this to 24 because MSC is doing stupid things then. */
4374	unsigned u16BaseLow : 16;
4375	/** 20 - Base address - first 8 bits of high word. */
4376	unsigned u8BaseHigh1 : 8;
4377	/** 28 - Segment Type. */
4378	unsigned u4Type : 4;
4379	/** 2c - Descriptor Type. System(=0) or code/data selector */
4380	unsigned u1DescType : 1;
4381	/** 2d - Descriptor Privilege level. */
4382	unsigned u2Dpl : 2;
4383	/** 2f - Flags selector present(=1) or not. */
4384	unsigned u1Present : 1;
4385	/** 30 - Segment limit 16-19. */
4386	unsigned u4LimitHigh : 4;
4387	/** 34 - Available for system software. */
4388	unsigned u1Available : 1;
4389	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4390	unsigned u1Long : 1;
4391	/** 36 - This flags meaning depends on the segment type. Try make sense out
4392	* of the intel manual yourself. */
4393	unsigned u1DefBig : 1;
4394	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4395	* clear byte. */
4396	unsigned u1Granularity : 1;
4397	/** 38 - Base address - highest 8 bits. */
4398	unsigned u8BaseHigh2 : 8;
4399	} X86DESCGENERIC;
4400	# pragma pack()
4401	/** Pointer to a generic descriptor entry. */
4402	typedef X86DESCGENERIC *PX86DESCGENERIC;
4403	/** Pointer to a const generic descriptor entry. */
4404	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4405	# endif /* !__ASSEMBLER__ */
4406
4407
4408	/** @name Bit offsets of X86DESCGENERIC members.
4409	* @{*/
4410	# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4411	# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4412	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4413	# define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4414	# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4415	# define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4416	# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4417	# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4418	# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4419	# define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4420	# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4421	# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4422	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4423	/** @} */
4424
4425
4426	/** @name LAR mask
4427	* @{ */
4428	# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4429	# define X86LAR_F_DT UINT16_C( 0x1000)
4430	# define X86LAR_F_DPL UINT16_C( 0x6000)
4431	# define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4432	# define X86LAR_F_P UINT16_C( 0x8000)
4433	# define X86LAR_F_AVL UINT32_C(0x00100000)
4434	# define X86LAR_F_L UINT32_C(0x00200000)
4435	# define X86LAR_F_D UINT32_C(0x00400000)
4436	# define X86LAR_F_G UINT32_C(0x00800000)
4437	/** @} */
4438
4439
4440	# ifndef __ASSEMBLER__
4441	/**
4442	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4443	*/
4444	typedef struct X86DESCGATE
4445	{
4446	/** 00 - Target code segment offset - Low word.
4447	* Ignored if task-gate. */
4448	unsigned u16OffsetLow : 16;
4449	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4450	* TSS selector if task-gate. */
4451	unsigned u16Sel : 16;
4452	/** 20 - Number of parameters for a call-gate.
4453	* Ignored if interrupt-, trap- or task-gate. */
4454	unsigned u5ParmCount : 5;
4455	/** 25 - Reserved / ignored. */
4456	unsigned u3Reserved : 3;
4457	/** 28 - Segment Type. */
4458	unsigned u4Type : 4;
4459	/** 2c - Descriptor Type (0 = system). */
4460	unsigned u1DescType : 1;
4461	/** 2d - Descriptor Privilege level. */
4462	unsigned u2Dpl : 2;
4463	/** 2f - Flags selector present(=1) or not. */
4464	unsigned u1Present : 1;
4465	/** 30 - Target code segment offset - High word.
4466	* Ignored if task-gate. */
4467	unsigned u16OffsetHigh : 16;
4468	} X86DESCGATE;
4469	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4470	typedef X86DESCGATE *PX86DESCGATE;
4471	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4472	typedef const X86DESCGATE *PCX86DESCGATE;
4473	# endif /* !__ASSEMBLER__ */
4474
4475	#endif /* VBOX_FOR_DTRACE_LIB */
4476
4477	#ifndef __ASSEMBLER__
4478	/**
4479	* Descriptor table entry.
4480	*/
4481	# pragma pack(1)
4482	typedef union X86DESC
4483	{
4484	# ifndef VBOX_FOR_DTRACE_LIB
4485	/** Generic descriptor view. */
4486	X86DESCGENERIC Gen;
4487	/** Gate descriptor view. */
4488	X86DESCGATE Gate;
4489	# endif
4490	/** 8 bit unsigned integer view. */
4491	uint8_t au8[8];
4492	/** 16 bit unsigned integer view. */
4493	uint16_t au16[4];
4494	/** 32 bit unsigned integer view. */
4495	uint32_t au32[2];
4496	/** 64 bit unsigned integer view. */
4497	uint64_t au64[1];
4498	/** Unsigned integer view. */
4499	uint64_t u;
4500	} X86DESC;
4501	# ifndef VBOX_FOR_DTRACE_LIB
4502	AssertCompileSize(X86DESC, 8);
4503	# endif
4504	# pragma pack()
4505	/** Pointer to descriptor table entry. */
4506	typedef X86DESC *PX86DESC;
4507	/** Pointer to const descriptor table entry. */
4508	typedef const X86DESC *PCX86DESC;
4509	#endif /* !__ASSEMBLER__ */
4510
4511	/** @def X86DESC_BASE
4512	* Return the base address of a descriptor.
4513	*/
4514	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4515	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4516	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4517	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4518
4519	/** @def X86DESC_LIMIT
4520	* Return the limit of a descriptor.
4521	*/
4522	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4523	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4524	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4525
4526	/** @def X86DESC_LIMIT_G
4527	* Return the limit of a descriptor with the granularity bit taken into account.
4528	* @returns Selector limit (uint32_t).
4529	* @param a_pDesc Pointer to the descriptor.
4530	*/
4531	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4532	( (a_pDesc)->Gen.u1Granularity \
4533	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4534	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4535	)
4536
4537	/** @def X86DESC_GET_HID_ATTR
4538	* Get the descriptor attributes for the hidden register.
4539	*/
4540	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4541	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4542
4543	#ifndef __ASSEMBLER__
4544	# ifndef VBOX_FOR_DTRACE_LIB
4545
4546	/**
4547	* 64 bits generic descriptor table entry
4548	* Note: most of these bits have no meaning in long mode.
4549	*/
4550	# pragma pack(1)
4551	typedef struct X86DESC64GENERIC
4552	{
4553	/** Limit - Low word - IGNORED. */
4554	uint32_t u16LimitLow : 16;
4555	/** Base address - low word. - IGNORED
4556	* Don't try set this to 24 because MSC is doing stupid things then. */
4557	uint32_t u16BaseLow : 16;
4558	/** Base address - first 8 bits of high word. - IGNORED */
4559	uint32_t u8BaseHigh1 : 8;
4560	/** Segment Type. */
4561	uint32_t u4Type : 4;
4562	/** Descriptor Type. System(=0) or code/data selector */
4563	uint32_t u1DescType : 1;
4564	/** Descriptor Privilege level. */
4565	uint32_t u2Dpl : 2;
4566	/** Flags selector present(=1) or not. */
4567	uint32_t u1Present : 1;
4568	/** Segment limit 16-19. - IGNORED */
4569	uint32_t u4LimitHigh : 4;
4570	/** Available for system software. - IGNORED */
4571	uint32_t u1Available : 1;
4572	/** Long mode flag. */
4573	uint32_t u1Long : 1;
4574	/** This flags meaning depends on the segment type. Try make sense out
4575	* of the intel manual yourself. */
4576	uint32_t u1DefBig : 1;
4577	/** Granularity of the limit. If set 4KB granularity is used, if
4578	* clear byte. - IGNORED */
4579	uint32_t u1Granularity : 1;
4580	/** Base address - highest 8 bits. - IGNORED */
4581	uint32_t u8BaseHigh2 : 8;
4582	/** Base address - bits 63-32. */
4583	uint32_t u32BaseHigh3 : 32;
4584	uint32_t u8Reserved : 8;
4585	uint32_t u5Zeros : 5;
4586	uint32_t u19Reserved : 19;
4587	} X86DESC64GENERIC;
4588	# pragma pack()
4589	/** Pointer to a generic descriptor entry. */
4590	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4591	/** Pointer to a const generic descriptor entry. */
4592	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4593
4594	/**
4595	* System descriptor table entry (64 bits)
4596	*
4597	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4598	*/
4599	# pragma pack(1)
4600	typedef struct X86DESC64SYSTEM
4601	{
4602	/** Limit - Low word. */
4603	uint32_t u16LimitLow : 16;
4604	/** Base address - low word.
4605	* Don't try set this to 24 because MSC is doing stupid things then. */
4606	uint32_t u16BaseLow : 16;
4607	/** Base address - first 8 bits of high word. */
4608	uint32_t u8BaseHigh1 : 8;
4609	/** Segment Type. */
4610	uint32_t u4Type : 4;
4611	/** Descriptor Type. System(=0) or code/data selector */
4612	uint32_t u1DescType : 1;
4613	/** Descriptor Privilege level. */
4614	uint32_t u2Dpl : 2;
4615	/** Flags selector present(=1) or not. */
4616	uint32_t u1Present : 1;
4617	/** Segment limit 16-19. */
4618	uint32_t u4LimitHigh : 4;
4619	/** Available for system software. */
4620	uint32_t u1Available : 1;
4621	/** Reserved - 0. */
4622	uint32_t u1Reserved : 1;
4623	/** This flags meaning depends on the segment type. Try make sense out
4624	* of the intel manual yourself. */
4625	uint32_t u1DefBig : 1;
4626	/** Granularity of the limit. If set 4KB granularity is used, if
4627	* clear byte. */
4628	uint32_t u1Granularity : 1;
4629	/** Base address - bits 31-24. */
4630	uint32_t u8BaseHigh2 : 8;
4631	/** Base address - bits 63-32. */
4632	uint32_t u32BaseHigh3 : 32;
4633	uint32_t u8Reserved : 8;
4634	uint32_t u5Zeros : 5;
4635	uint32_t u19Reserved : 19;
4636	} X86DESC64SYSTEM;
4637	# pragma pack()
4638	/** Pointer to a system descriptor entry. */
4639	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4640	/** Pointer to a const system descriptor entry. */
4641	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4642
4643	/**
4644	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4645	*/
4646	typedef struct X86DESC64GATE
4647	{
4648	/** Target code segment offset - Low word. */
4649	uint32_t u16OffsetLow : 16;
4650	/** Target code segment selector. */
4651	uint32_t u16Sel : 16;
4652	/** Interrupt stack table for interrupt- and trap-gates.
4653	* Ignored by call-gates. */
4654	uint32_t u3IST : 3;
4655	/** Reserved / ignored. */
4656	uint32_t u5Reserved : 5;
4657	/** Segment Type. */
4658	uint32_t u4Type : 4;
4659	/** Descriptor Type (0 = system). */
4660	uint32_t u1DescType : 1;
4661	/** Descriptor Privilege level. */
4662	uint32_t u2Dpl : 2;
4663	/** Flags selector present(=1) or not. */
4664	uint32_t u1Present : 1;
4665	/** Target code segment offset - High word.
4666	* Ignored if task-gate. */
4667	uint32_t u16OffsetHigh : 16;
4668	/** Target code segment offset - Top dword.
4669	* Ignored if task-gate. */
4670	uint32_t u32OffsetTop : 32;
4671	/** Reserved / ignored / must be zero.
4672	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4673	uint32_t u32Reserved : 32;
4674	} X86DESC64GATE;
4675	AssertCompileSize(X86DESC64GATE, 16);
4676	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4677	typedef X86DESC64GATE *PX86DESC64GATE;
4678	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4679	typedef const X86DESC64GATE *PCX86DESC64GATE;
4680
4681	# endif /* VBOX_FOR_DTRACE_LIB */
4682
4683	/**
4684	* Descriptor table entry.
4685	*/
4686	# pragma pack(1)
4687	typedef union X86DESC64
4688	{
4689	# ifndef VBOX_FOR_DTRACE_LIB
4690	/** Generic descriptor view. */
4691	X86DESC64GENERIC Gen;
4692	/** System descriptor view. */
4693	X86DESC64SYSTEM System;
4694	/** Gate descriptor view. */
4695	X86DESC64GATE Gate;
4696	# endif
4697
4698	/** 8 bit unsigned integer view. */
4699	uint8_t au8[16];
4700	/** 16 bit unsigned integer view. */
4701	uint16_t au16[8];
4702	/** 32 bit unsigned integer view. */
4703	uint32_t au32[4];
4704	/** 64 bit unsigned integer view. */
4705	uint64_t au64[2];
4706	} X86DESC64;
4707	# ifndef VBOX_FOR_DTRACE_LIB
4708	AssertCompileSize(X86DESC64, 16);
4709	# endif
4710	# pragma pack()
4711	/** Pointer to descriptor table entry. */
4712	typedef X86DESC64 *PX86DESC64;
4713	/** Pointer to const descriptor table entry. */
4714	typedef const X86DESC64 *PCX86DESC64;
4715
4716	/** @def X86DESC64_BASE
4717	* Return the base of a 64-bit descriptor.
4718	*/
4719	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4720	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4721	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4722	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4723	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4724
4725
4726
4727	/** @name Host system descriptor table entry - Use with care!
4728	* @{ */
4729	/** Host system descriptor table entry. */
4730	#if HC_ARCH_BITS == 64
4731	typedef X86DESC64 X86DESCHC;
4732	#else
4733	typedef X86DESC X86DESCHC;
4734	#endif
4735	/** Pointer to a host system descriptor table entry. */
4736	#if HC_ARCH_BITS == 64
4737	typedef PX86DESC64 PX86DESCHC;
4738	#else
4739	typedef PX86DESC PX86DESCHC;
4740	#endif
4741	/** Pointer to a const host system descriptor table entry. */
4742	#if HC_ARCH_BITS == 64
4743	typedef PCX86DESC64 PCX86DESCHC;
4744	#else
4745	typedef PCX86DESC PCX86DESCHC;
4746	#endif
4747	/** @} */
4748
4749	#endif /* !__ASSEMBLER__ */
4750
4751
4752	/** @name Selector Descriptor Types.
4753	* @{
4754	*/
4755
4756	/** @name Non-System Selector Types.
4757	* @{ */
4758	/** Code(=set)/Data(=clear) bit. */
4759	#define X86_SEL_TYPE_CODE 8
4760	/** Memory(=set)/System(=clear) bit. */
4761	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4762	/** Accessed bit. */
4763	#define X86_SEL_TYPE_ACCESSED 1
4764	/** Expand down bit (for data selectors only). */
4765	#define X86_SEL_TYPE_DOWN 4
4766	/** Conforming bit (for code selectors only). */
4767	#define X86_SEL_TYPE_CONF 4
4768	/** Write bit (for data selectors only). */
4769	#define X86_SEL_TYPE_WRITE 2
4770	/** Read bit (for code selectors only). */
4771	#define X86_SEL_TYPE_READ 2
4772	/** The bit number of the code segment read bit (relative to u4Type). */
4773	#define X86_SEL_TYPE_READ_BIT 1
4774
4775	/** Read only selector type. */
4776	#define X86_SEL_TYPE_RO 0
4777	/** Accessed read only selector type. */
4778	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4779	/** Read write selector type. */
4780	#define X86_SEL_TYPE_RW 2
4781	/** Accessed read write selector type. */
4782	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4783	/** Expand down read only selector type. */
4784	#define X86_SEL_TYPE_RO_DOWN 4
4785	/** Accessed expand down read only selector type. */
4786	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4787	/** Expand down read write selector type. */
4788	#define X86_SEL_TYPE_RW_DOWN 6
4789	/** Accessed expand down read write selector type. */
4790	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4791	/** Execute only selector type. */
4792	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4793	/** Accessed execute only selector type. */
4794	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4795	/** Execute and read selector type. */
4796	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4797	/** Accessed execute and read selector type. */
4798	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4799	/** Conforming execute only selector type. */
4800	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4801	/** Accessed Conforming execute only selector type. */
4802	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4803	/** Conforming execute and write selector type. */
4804	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4805	/** Accessed Conforming execute and write selector type. */
4806	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4807	/** @} */
4808
4809
4810	/** @name System Selector Types.
4811	* @{ */
4812	/** The TSS busy bit mask. */
4813	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4814
4815	/** Undefined system selector type. */
4816	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4817	/** 286 TSS selector. */
4818	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4819	/** LDT selector. */
4820	#define X86_SEL_TYPE_SYS_LDT 2
4821	/** 286 TSS selector - Busy. */
4822	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4823	/** 286 Callgate selector. */
4824	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4825	/** Taskgate selector. */
4826	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4827	/** 286 Interrupt gate selector. */
4828	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4829	/** 286 Trapgate selector. */
4830	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4831	/** Undefined system selector. */
4832	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4833	/** 386 TSS selector. */
4834	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4835	/** Undefined system selector. */
4836	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4837	/** 386 TSS selector - Busy. */
4838	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4839	/** 386 Callgate selector. */
4840	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4841	/** Undefined system selector. */
4842	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4843	/** 386 Interruptgate selector. */
4844	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4845	/** 386 Trapgate selector. */
4846	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4847	/** @} */
4848
4849	/** @name AMD64 System Selector Types.
4850	* @{ */
4851	/** LDT selector. */
4852	#define AMD64_SEL_TYPE_SYS_LDT 2
4853	/** TSS selector - Busy. */
4854	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4855	/** TSS selector - Busy. */
4856	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4857	/** Callgate selector. */
4858	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4859	/** Interruptgate selector. */
4860	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4861	/** Trapgate selector. */
4862	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4863	/** @} */
4864
4865	/** @} */
4866
4867
4868	/** @name Descriptor Table Entry Flag Masks.
4869	* These are for the 2nd 32-bit word of a descriptor.
4870	* @{ */
4871	/** Bits 8-11 - TYPE - Descriptor type mask. */
4872	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4873	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4874	#define X86_DESC_S RT_BIT_32(12)
4875	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4876	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4877	/** Bit 15 - P - Present. */
4878	#define X86_DESC_P RT_BIT_32(15)
4879	/** Bit 20 - AVL - Available for system software. */
4880	#define X86_DESC_AVL RT_BIT_32(20)
4881	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4882	#define X86_DESC_DB RT_BIT_32(22)
4883	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4884	* used, if clear byte. */
4885	#define X86_DESC_G RT_BIT_32(23)
4886	/** @} */
4887
4888	/** @} */
4889
4890
4891	/** @name Task Segments.
4892	* @{
4893	*/
4894
4895	/**
4896	* The minimum TSS descriptor limit for 286 tasks.
4897	*/
4898	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4899
4900	/**
4901	* The minimum TSS descriptor segment limit for 386 tasks.
4902	*/
4903	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4904
4905	#ifndef __ASSEMBLER__
4906
4907	/**
4908	* 16-bit Task Segment (TSS).
4909	*/
4910	# pragma pack(1)
4911	typedef struct X86TSS16
4912	{
4913	/** Back link to previous task. (static) */
4914	RTSEL selPrev;
4915	/** Ring-0 stack pointer. (static) */
4916	uint16_t sp0;
4917	/** Ring-0 stack segment. (static) */
4918	RTSEL ss0;
4919	/** Ring-1 stack pointer. (static) */
4920	uint16_t sp1;
4921	/** Ring-1 stack segment. (static) */
4922	RTSEL ss1;
4923	/** Ring-2 stack pointer. (static) */
4924	uint16_t sp2;
4925	/** Ring-2 stack segment. (static) */
4926	RTSEL ss2;
4927	/** IP before task switch. */
4928	uint16_t ip;
4929	/** FLAGS before task switch. */
4930	uint16_t flags;
4931	/** AX before task switch. */
4932	uint16_t ax;
4933	/** CX before task switch. */
4934	uint16_t cx;
4935	/** DX before task switch. */
4936	uint16_t dx;
4937	/** BX before task switch. */
4938	uint16_t bx;
4939	/** SP before task switch. */
4940	uint16_t sp;
4941	/** BP before task switch. */
4942	uint16_t bp;
4943	/** SI before task switch. */
4944	uint16_t si;
4945	/** DI before task switch. */
4946	uint16_t di;
4947	/** ES before task switch. */
4948	RTSEL es;
4949	/** CS before task switch. */
4950	RTSEL cs;
4951	/** SS before task switch. */
4952	RTSEL ss;
4953	/** DS before task switch. */
4954	RTSEL ds;
4955	/** LDTR before task switch. */
4956	RTSEL selLdt;
4957	} X86TSS16;
4958	# ifndef VBOX_FOR_DTRACE_LIB
4959	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4960	# endif
4961	# pragma pack()
4962	/** Pointer to a 16-bit task segment. */
4963	typedef X86TSS16 *PX86TSS16;
4964	/** Pointer to a const 16-bit task segment. */
4965	typedef const X86TSS16 *PCX86TSS16;
4966
4967
4968	/**
4969	* 32-bit Task Segment (TSS).
4970	*/
4971	# pragma pack(1)
4972	typedef struct X86TSS32
4973	{
4974	/** Back link to previous task. (static) */
4975	RTSEL selPrev;
4976	uint16_t padding1;
4977	/** Ring-0 stack pointer. (static) */
4978	uint32_t esp0;
4979	/** Ring-0 stack segment. (static) */
4980	RTSEL ss0;
4981	uint16_t padding_ss0;
4982	/** Ring-1 stack pointer. (static) */
4983	uint32_t esp1;
4984	/** Ring-1 stack segment. (static) */
4985	RTSEL ss1;
4986	uint16_t padding_ss1;
4987	/** Ring-2 stack pointer. (static) */
4988	uint32_t esp2;
4989	/** Ring-2 stack segment. (static) */
4990	RTSEL ss2;
4991	uint16_t padding_ss2;
4992	/** Page directory for the task. (static) */
4993	uint32_t cr3;
4994	/** EIP before task switch. */
4995	uint32_t eip;
4996	/** EFLAGS before task switch. */
4997	uint32_t eflags;
4998	/** EAX before task switch. */
4999	uint32_t eax;
5000	/** ECX before task switch. */
5001	uint32_t ecx;
5002	/** EDX before task switch. */
5003	uint32_t edx;
5004	/** EBX before task switch. */
5005	uint32_t ebx;
5006	/** ESP before task switch. */
5007	uint32_t esp;
5008	/** EBP before task switch. */
5009	uint32_t ebp;
5010	/** ESI before task switch. */
5011	uint32_t esi;
5012	/** EDI before task switch. */
5013	uint32_t edi;
5014	/** ES before task switch. */
5015	RTSEL es;
5016	uint16_t padding_es;
5017	/** CS before task switch. */
5018	RTSEL cs;
5019	uint16_t padding_cs;
5020	/** SS before task switch. */
5021	RTSEL ss;
5022	uint16_t padding_ss;
5023	/** DS before task switch. */
5024	RTSEL ds;
5025	uint16_t padding_ds;
5026	/** FS before task switch. */
5027	RTSEL fs;
5028	uint16_t padding_fs;
5029	/** GS before task switch. */
5030	RTSEL gs;
5031	uint16_t padding_gs;
5032	/** LDTR before task switch. */
5033	RTSEL selLdt;
5034	uint16_t padding_ldt;
5035	/** Debug trap flag */
5036	uint16_t fDebugTrap;
5037	/** Offset relative to the TSS of the start of the I/O Bitmap
5038	* and the end of the interrupt redirection bitmap. */
5039	uint16_t offIoBitmap;
5040	} X86TSS32;
5041	# pragma pack()
5042	/** Pointer to task segment. */
5043	typedef X86TSS32 *PX86TSS32;
5044	/** Pointer to const task segment. */
5045	typedef const X86TSS32 *PCX86TSS32;
5046	# ifndef VBOX_FOR_DTRACE_LIB
5047	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
5048	AssertCompileMemberOffset(X86TSS32, cr3, 28);
5049	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
5050	# endif
5051
5052	/**
5053	* 64-bit Task segment.
5054	*/
5055	# pragma pack(1)
5056	typedef struct X86TSS64
5057	{
5058	/** Reserved. */
5059	uint32_t u32Reserved;
5060	/** Ring-0 stack pointer. (static) */
5061	uint64_t rsp0;
5062	/** Ring-1 stack pointer. (static) */
5063	uint64_t rsp1;
5064	/** Ring-2 stack pointer. (static) */
5065	uint64_t rsp2;
5066	/** Reserved. */
5067	uint32_t u32Reserved2[2];
5068	/* IST */
5069	uint64_t ist1;
5070	uint64_t ist2;
5071	uint64_t ist3;
5072	uint64_t ist4;
5073	uint64_t ist5;
5074	uint64_t ist6;
5075	uint64_t ist7;
5076	/* Reserved. */
5077	uint16_t u16Reserved[5];
5078	/** Offset relative to the TSS of the start of the I/O Bitmap
5079	* and the end of the interrupt redirection bitmap. */
5080	uint16_t offIoBitmap;
5081	} X86TSS64;
5082	# pragma pack()
5083	/** Pointer to a 64-bit task segment. */
5084	typedef X86TSS64 *PX86TSS64;
5085	/** Pointer to a const 64-bit task segment. */
5086	typedef const X86TSS64 *PCX86TSS64;
5087	# ifndef VBOX_FOR_DTRACE_LIB
5088	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
5089	# endif
5090
5091	#endif /* !__ASSEMBLER__ */
5092
5093	/** @} */
5094
5095
5096	/** @name Selectors.
5097	* @{
5098	*/
5099
5100	/**
5101	* The shift used to convert a selector from and to index an index (C).
5102	*/
5103	#define X86_SEL_SHIFT 3
5104
5105	/**
5106	* The mask used to mask off the table indicator and RPL of an selector.
5107	*/
5108	#define X86_SEL_MASK 0xfff8U
5109
5110	/**
5111	* The mask used to mask off the RPL of an selector.
5112	* This is suitable for checking for NULL selectors.
5113	*/
5114	#define X86_SEL_MASK_OFF_RPL 0xfffcU
5115
5116	/**
5117	* The bit indicating that a selector is in the LDT and not in the GDT.
5118	*/
5119	#define X86_SEL_LDT 0x0004U
5120
5121	/**
5122	* The bit mask for getting the RPL of a selector.
5123	*/
5124	#define X86_SEL_RPL 0x0003U
5125
5126	/**
5127	* The mask covering both RPL and LDT.
5128	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
5129	* checks.
5130	*/
5131	#define X86_SEL_RPL_LDT 0x0007U
5132
5133	/** @} */
5134
5135
5136	#ifndef __ASSEMBLER__
5137	/**
5138	* x86 Exceptions/Faults/Traps.
5139	*/
5140	typedef enum X86XCPT
5141	{
5142	/** \#DE - Divide error. */
5143	X86_XCPT_DE = 0x00,
5144	/** \#DB - Debug event (single step, DRx, ..) */
5145	X86_XCPT_DB = 0x01,
5146	/** NMI - Non-Maskable Interrupt */
5147	X86_XCPT_NMI = 0x02,
5148	/** \#BP - Breakpoint (INT3). */
5149	X86_XCPT_BP = 0x03,
5150	/** \#OF - Overflow (INTO). */
5151	X86_XCPT_OF = 0x04,
5152	/** \#BR - Bound range exceeded (BOUND). */
5153	X86_XCPT_BR = 0x05,
5154	/** \#UD - Undefined opcode. */
5155	X86_XCPT_UD = 0x06,
5156	/** \#NM - Device not available (math coprocessor device). */
5157	X86_XCPT_NM = 0x07,
5158	/** \#DF - Double fault. */
5159	X86_XCPT_DF = 0x08,
5160	/** ??? - Coprocessor segment overrun (obsolete). */
5161	X86_XCPT_CO_SEG_OVERRUN = 0x09,
5162	/** \#TS - Taskswitch (TSS). */
5163	X86_XCPT_TS = 0x0a,
5164	/** \#NP - Segment no present. */
5165	X86_XCPT_NP = 0x0b,
5166	/** \#SS - Stack segment fault. */
5167	X86_XCPT_SS = 0x0c,
5168	/** \#GP - General protection fault. */
5169	X86_XCPT_GP = 0x0d,
5170	/** \#PF - Page fault. */
5171	X86_XCPT_PF = 0x0e,
5172	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
5173	/** \#MF - Math fault (FPU). */
5174	X86_XCPT_MF = 0x10,
5175	/** \#AC - Alignment check. */
5176	X86_XCPT_AC = 0x11,
5177	/** \#MC - Machine check. */
5178	X86_XCPT_MC = 0x12,
5179	/** \#XF - SIMD Floating-Point Exception. */
5180	X86_XCPT_XF = 0x13,
5181	/** \#VE - Virtualization Exception (Intel only). */
5182	X86_XCPT_VE = 0x14,
5183	/** \#CP - Control Protection Exception. */
5184	X86_XCPT_CP = 0x15,
5185	/** \#VC - VMM Communication Exception (AMD only). */
5186	X86_XCPT_VC = 0x1d,
5187	/** \#SX - Security Exception (AMD only). */
5188	X86_XCPT_SX = 0x1e
5189	} X86XCPT;
5190	/** Pointer to a x86 exception code. */
5191	typedef X86XCPT *PX86XCPT;
5192	/** Pointer to a const x86 exception code. */
5193	typedef const X86XCPT *PCX86XCPT;
5194	#endif /* !__ASSEMBLER__ */
5195	/** The last valid (currently reserved) exception value. */
5196	#define X86_XCPT_LAST 0x1f
5197
5198
5199	/** @name Trap Error Codes
5200	* @{
5201	*/
5202	/** External indicator. */
5203	#define X86_TRAP_ERR_EXTERNAL 1
5204	/** IDT indicator. */
5205	#define X86_TRAP_ERR_IDT 2
5206	/** Descriptor table indicator - If set LDT, if clear GDT. */
5207	#define X86_TRAP_ERR_TI 4
5208	/** Mask for getting the selector. */
5209	#define X86_TRAP_ERR_SEL_MASK 0xfff8
5210	/** Shift for getting the selector table index (C type index). */
5211	#define X86_TRAP_ERR_SEL_SHIFT 3
5212	/** @} */
5213
5214
5215	/** @name \#PF Trap Error Codes
5216	* @{
5217	*/
5218	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
5219	#define X86_TRAP_PF_P RT_BIT_32(0)
5220	/** Bit 1 - R/W - Read (clear) or write (set) access. */
5221	#define X86_TRAP_PF_RW RT_BIT_32(1)
5222	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
5223	#define X86_TRAP_PF_US RT_BIT_32(2)
5224	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
5225	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
5226	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
5227	#define X86_TRAP_PF_ID RT_BIT_32(4)
5228	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
5229	#define X86_TRAP_PF_PK RT_BIT_32(5)
5230	/** @} */
5231
5232	#ifndef __ASSEMBLER__
5233
5234	# pragma pack(1)
5235	/**
5236	* 16-bit IDTR.
5237	*/
5238	typedef struct X86IDTR16
5239	{
5240	/** Offset. */
5241	uint16_t offSel;
5242	/** Selector. */
5243	uint16_t uSel;
5244	} X86IDTR16, *PX86IDTR16;
5245	# pragma pack()
5246
5247	# pragma pack(1)
5248	/**
5249	* 32-bit IDTR/GDTR.
5250	*/
5251	typedef struct X86XDTR32
5252	{
5253	/** Size of the descriptor table. */
5254	uint16_t cb;
5255	/** Address of the descriptor table. */
5256	# ifndef VBOX_FOR_DTRACE_LIB
5257	uint32_t uAddr;
5258	# else
5259	uint16_t au16Addr[2];
5260	# endif
5261	} X86XDTR32, *PX86XDTR32;
5262	# pragma pack()
5263
5264	# pragma pack(1)
5265	/**
5266	* 64-bit IDTR/GDTR.
5267	*/
5268	typedef struct X86XDTR64
5269	{
5270	/** Size of the descriptor table. */
5271	uint16_t cb;
5272	/** Address of the descriptor table. */
5273	# ifndef VBOX_FOR_DTRACE_LIB
5274	uint64_t uAddr;
5275	# else
5276	uint16_t au16Addr[4];
5277	# endif
5278	} X86XDTR64, *PX86XDTR64;
5279	# pragma pack()
5280
5281	#endif /* !__ASSEMBLER__ */
5282
5283
5284	/** @name ModR/M
5285	* @{ */
5286	#define X86_MODRM_RM_MASK UINT8_C(0x07)
5287	#define X86_MODRM_REG_MASK UINT8_C(0x38)
5288	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5289	#define X86_MODRM_REG_SHIFT 3
5290	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5291	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5292	#define X86_MODRM_MOD_SHIFT 6
5293
5294	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
5295	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
5296	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
5297	#define X86_MOD_REG 3 /*< Registers. /
5298
5299	#ifndef VBOX_FOR_DTRACE_LIB
5300	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
5301	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5302	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5303	/** @def X86_MODRM_MAKE
5304	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5305	* @param a_Reg The register value (0..7).
5306	* @param a_RegMem The register or memory value (0..7). */
5307	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
5308	#endif
5309
5310	/** @} */
5311
5312	/** @name SIB
5313	* @{ */
5314	#define X86_SIB_BASE_MASK UINT8_C(0x07)
5315	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5316	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5317	#define X86_SIB_INDEX_SHIFT 3
5318	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5319	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5320	#define X86_SIB_SCALE_SHIFT 6
5321	#ifndef VBOX_FOR_DTRACE_LIB
5322	/** @def X86_SIB_MAKE
5323	* @param a_BaseReg The base register value (0..7).
5324	* @param a_IndexReg The index register value (0..7).
5325	* @param a_Scale The left shift (0..3) to be applied to the index
5326	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5327	* */
5328	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5329	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
5330
5331	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
5332	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5333	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5334	#endif
5335	/** @} */
5336
5337	/** @name General register indexes.
5338	* @{ */
5339	#define X86_GREG_xAX 0
5340	#define X86_GREG_xCX 1
5341	#define X86_GREG_xDX 2
5342	#define X86_GREG_xBX 3
5343	#define X86_GREG_xSP 4
5344	#define X86_GREG_xBP 5
5345	#define X86_GREG_xSI 6
5346	#define X86_GREG_xDI 7
5347	#define X86_GREG_x8 8
5348	#define X86_GREG_x9 9
5349	#define X86_GREG_x10 10
5350	#define X86_GREG_x11 11
5351	#define X86_GREG_x12 12
5352	#define X86_GREG_x13 13
5353	#define X86_GREG_x14 14
5354	#define X86_GREG_x15 15
5355	/** @} */
5356	/** General register count. */
5357	#define X86_GREG_COUNT 16
5358
5359	/** @name X86_SREG_XXX - Segment register indexes.
5360	* @{ */
5361	#define X86_SREG_ES 0
5362	#define X86_SREG_CS 1
5363	#define X86_SREG_SS 2
5364	#define X86_SREG_DS 3
5365	#define X86_SREG_FS 4
5366	#define X86_SREG_GS 5
5367	/** @} */
5368	/** Segment register count. */
5369	#define X86_SREG_COUNT 6
5370
5371
5372	/** @name X86_OP_XXX - Prefixes
5373	* @{ */
5374	#define X86_OP_PRF_CS UINT8_C(0x2e)
5375	#define X86_OP_PRF_SS UINT8_C(0x36)
5376	#define X86_OP_PRF_DS UINT8_C(0x3e)
5377	#define X86_OP_PRF_ES UINT8_C(0x26)
5378	#define X86_OP_PRF_FS UINT8_C(0x64)
5379	#define X86_OP_PRF_GS UINT8_C(0x65)
5380	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5381	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5382	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5383	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5384	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5385	#define X86_OP_REX UINT8_C(0x40)
5386	#define X86_OP_REX_B UINT8_C(0x41)
5387	#define X86_OP_REX_X UINT8_C(0x42)
5388	#define X86_OP_REX_R UINT8_C(0x44)
5389	#define X86_OP_REX_W UINT8_C(0x48)
5390	#define X86_OP_VEX3 UINT8_C(0xc4)
5391	#define X86_OP_VEX2 UINT8_C(0xc5)
5392	/** @} */
5393
5394	/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
5395	* @{ */
5396	#define X86_OP_VEX2_BYTE1_P_MASK 0x3
5397	# define X86_OP_VEX2_BYTE1_P_NO_PRF 0
5398	# define X86_OP_VEX2_BYTE1_P_066H 1
5399	# define X86_OP_VEX2_BYTE1_P_0F3H 2
5400	# define X86_OP_VEX2_BYTE1_P_0F2H 3
5401	#define X86_OP_VEX2_BYTE1_L RT_BIT(2)
5402	#define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
5403	#define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
5404	#define X86_OP_VEX2_BYTE1_VVVV_NONE 15
5405	#define X86_OP_VEX2_BYTE1_R RT_BIT(7)
5406
5407	#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5408	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5409	\| (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5410	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5411	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5412
5413	#define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
5414	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5415	\| (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5416	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5417	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5418	/** @} */
5419
5420	/** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
5421	* @{ */
5422	#define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
5423	#define X86_OP_VEX3_BYTE1_B RT_BIT(5)
5424	#define X86_OP_VEX3_BYTE1_X RT_BIT(6)
5425	#define X86_OP_VEX3_BYTE1_R RT_BIT(7)
5426	#define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
5427	( (uint8_t)(a_idxMap) \
5428	\| ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
5429	\| ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
5430	\| ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
5431
5432	#define X86_OP_VEX3_BYTE2_P_MASK 0x3
5433	# define X86_OP_VEX3_BYTE2_P_NO_PRF 0
5434	# define X86_OP_VEX3_BYTE2_P_066H 1
5435	# define X86_OP_VEX3_BYTE2_P_0F3H 2
5436	# define X86_OP_VEX3_BYTE2_P_0F2H 3
5437	#define X86_OP_VEX3_BYTE2_L RT_BIT(2)
5438	#define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
5439	#define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
5440	#define X86_OP_VEX3_BYTE2_VVVV_NONE 15
5441	#define X86_OP_VEX3_BYTE2_W RT_BIT(7)
5442
5443	/** @todo r=bird: Is the '& UINT8_C(0xf)' bit needed? You mask it again after
5444	* shifting. */
5445	#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5446	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5447	\| ((~((uint8_t)(a_iSrcReg) & UINT8_C(0xf)) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
5448	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5449	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5450
5451	#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
5452	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5453	\| (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
5454	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5455	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5456	/** @} */
5457
5458	/** @} */
5459
5460	#endif /* !IPRT_INCLUDED_x86_h */
5461

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source: vbox/trunk/include/iprt/x86.h

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