pgm.h@ 108326

最後變更在這個檔案從108326是 108132,由 vboxsync 提交於 7 週前
VMM/PGM: Merge and deduplicate code targeting x86 & amd64 in PGM.cpp. Don't bother compiling pool stuff on arm and darwin.amd64. jiraref:VBP-1531
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.alldomusa.eu.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_pgm_h
37	#define VBOX_INCLUDED_vmm_pgm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <VBox/sup.h>
44	#include <VBox/vmm/vmapi.h>
45	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
46	#include <VBox/vmm/hm_vmx.h>
47	#include <iprt/x86.h>
48	#include <VBox/param.h>
49
50	RT_C_DECLS_BEGIN
51
52	/** @defgroup grp_pgm The Page Monitor / Manager API
53	* @ingroup grp_vmm
54	* @{
55	*/
56
57	/**
58	* FNPGMRELOCATE callback mode.
59	*/
60	typedef enum PGMRELOCATECALL
61	{
62	/** The callback is for checking if the suggested address is suitable. */
63	PGMRELOCATECALL_SUGGEST = 1,
64	/** The callback is for executing the relocation. */
65	PGMRELOCATECALL_RELOCATE
66	} PGMRELOCATECALL;
67
68
69	/**
70	* Callback function which will be called when PGM is trying to find
71	* a new location for the mapping.
72	*
73	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
74	* In 1) the callback should say if it objects to a suggested new location. If it
75	* accepts the new location, it is called again for doing it's relocation.
76	*
77	*
78	* @returns true if the location is ok.
79	* @returns false if another location should be found.
80	* @param pVM The cross context VM structure.
81	* @param GCPtrOld The old virtual address.
82	* @param GCPtrNew The new virtual address.
83	* @param enmMode Used to indicate the callback mode.
84	* @param pvUser User argument.
85	* @remark The return value is no a failure indicator, it's an acceptance
86	* indicator. Relocation can not fail!
87	*/
88	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
89	/** Pointer to a relocation callback function. */
90	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
91
92
93	/**
94	* Memory access origin.
95	*/
96	typedef enum PGMACCESSORIGIN
97	{
98	/** Invalid zero value. */
99	PGMACCESSORIGIN_INVALID = 0,
100	/** IEM is access memory. */
101	PGMACCESSORIGIN_IEM,
102	/** HM is access memory. */
103	PGMACCESSORIGIN_HM,
104	/** Some device is access memory. */
105	PGMACCESSORIGIN_DEVICE,
106	/** Someone debugging is access memory. */
107	PGMACCESSORIGIN_DEBUGGER,
108	/** SELM is access memory. */
109	PGMACCESSORIGIN_SELM,
110	/** FTM is access memory. */
111	PGMACCESSORIGIN_FTM,
112	/** REM is access memory. */
113	PGMACCESSORIGIN_REM,
114	/** IOM is access memory. */
115	PGMACCESSORIGIN_IOM,
116	/** End of valid values. */
117	PGMACCESSORIGIN_END,
118	/** Type size hack. */
119	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
120	} PGMACCESSORIGIN;
121
122
123	/**
124	* Physical page access handler kind.
125	*/
126	typedef enum PGMPHYSHANDLERKIND
127	{
128	/** Invalid zero value. */
129	PGMPHYSHANDLERKIND_INVALID = 0,
130	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
131	PGMPHYSHANDLERKIND_MMIO,
132	/** Handler all write access to a physical page range. */
133	PGMPHYSHANDLERKIND_WRITE,
134	/** Handler all access to a physical page range. */
135	PGMPHYSHANDLERKIND_ALL,
136	/** End of the valid values. */
137	PGMPHYSHANDLERKIND_END,
138	/** Type size hack. */
139	PGMPHYSHANDLERKIND_32BIT_HACK = 0x7fffffff
140	} PGMPHYSHANDLERKIND;
141
142	/**
143	* Guest Access type
144	*/
145	typedef enum PGMACCESSTYPE
146	{
147	/** Read access. */
148	PGMACCESSTYPE_READ = 1,
149	/** Write access. */
150	PGMACCESSTYPE_WRITE
151	} PGMACCESSTYPE;
152
153
154	/** @def PGM_ALL_CB_DECL
155	* Macro for declaring a handler callback for all contexts. The handler
156	* callback is static in ring-3, and exported in RC and R0.
157	* @sa PGM_ALL_CB2_DECL.
158	*/
159	#if defined(IN_RC) \|\| defined(IN_RING0)
160	# ifdef __cplusplus
161	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
162	# else
163	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
164	# endif
165	#else
166	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
167	#endif
168
169	/** @def PGM_ALL_CB2_DECL
170	* Macro for declaring a handler callback for all contexts. The handler
171	* callback is hidden in ring-3, and exported in RC and R0.
172	* @sa PGM_ALL_CB2_DECL.
173	*/
174	#if defined(IN_RC) \|\| defined(IN_RING0)
175	# ifdef __cplusplus
176	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
177	# else
178	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
179	# endif
180	#else
181	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
182	#endif
183
184	/** @def PGM_ALL_CB2_PROTO
185	* Macro for declaring a handler callback for all contexts. The handler
186	* callback is hidden in ring-3, and exported in RC and R0.
187	* @param fnType The callback function type.
188	* @sa PGM_ALL_CB2_DECL.
189	*/
190	#if defined(IN_RC) \|\| defined(IN_RING0)
191	# ifdef __cplusplus
192	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
193	# else
194	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
195	# endif
196	#else
197	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
198	#endif
199
200
201	/**
202	* \#PF Handler callback for physical access handler ranges in RC and R0.
203	*
204	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
205	* @param pVM The cross context VM structure.
206	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
207	* @param uErrorCode CPU Error code.
208	* @param pCtx Pointer to the register context for the CPU.
209	* @param pvFault The fault address (cr2).
210	* @param GCPhysFault The GC physical address corresponding to pvFault.
211	* @param uUser User argument (not a pointer).
212	* @thread EMT(pVCpu)
213	*/
214	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
215	RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser));
216	/** Pointer to PGM access callback. */
217	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
218
219
220	/**
221	* Access handler callback for physical access handler ranges.
222	*
223	* The handler can not raise any faults, it's mainly for monitoring write access
224	* to certain pages (like MMIO).
225	*
226	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
227	* the only supported informational status code is
228	* VINF_PGM_HANDLER_DO_DEFAULT.
229	* @retval VINF_SUCCESS if the handler have carried out the operation.
230	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
231	* access operation.
232	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
233	*
234	* @param pVM The cross context VM structure.
235	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
236	* @param GCPhys The physical address the guest is writing to.
237	* @param pvPhys The HC mapping of that address.
238	* @param pvBuf What the guest is reading/writing.
239	* @param cbBuf How much it's reading/writing.
240	* @param enmAccessType The access type.
241	* @param enmOrigin The origin of this call.
242	* @param uUser User argument (not a pointer).
243	* @thread EMT(pVCpu)
244	*/
245	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
246	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
247	PGMACCESSORIGIN enmOrigin, uint64_t uUser));
248	/** Pointer to PGM access callback. */
249	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
250
251
252	/** @todo r=aeichner This doesn't seem to be used outside of the VMM module, so we might make
253	* all APIs (PGMGetGuestMode(), etc.) internal and split this up into an
254	* x86 and arm specific header. */
255	/**
256	* Paging mode.
257	*
258	* @note Part of saved state. Change with extreme care.
259	* @note Due to PGMGetShadowMode() and the possibility that we will be
260	* running ARMv8 VMs on a AMD64 hosts, it's safer to combine these
261	* modes. We could rethink this if we start using PGMMODE exclusively
262	* for the guest mode and come up with a different enum for the host.
263	*/
264	typedef enum PGMMODE
265	{
266	/** The usual invalid value. */
267	PGMMODE_INVALID = 0,
268
269	/** @name X86
270	* @{ */
271	/** Real mode. */
272	PGMMODE_REAL,
273	/** Protected mode, no paging. */
274	PGMMODE_PROTECTED,
275	/** 32-bit paging. */
276	PGMMODE_32_BIT,
277	/** PAE paging. */
278	PGMMODE_PAE,
279	/** PAE paging with NX enabled. */
280	PGMMODE_PAE_NX,
281	/** 64-bit AMD paging (long mode). */
282	PGMMODE_AMD64,
283	/** 64-bit AMD paging (long mode) with NX enabled. */
284	PGMMODE_AMD64_NX,
285	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
286	PGMMODE_NESTED_32BIT,
287	/** PAE nested paging mode (shadow only; guest physical to host physical). */
288	PGMMODE_NESTED_PAE,
289	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
290	PGMMODE_NESTED_AMD64,
291	/** Extended paging (Intel) mode. */
292	PGMMODE_EPT,
293	/** @} */
294
295	/** ARMv8: Paging is not enabled by the guest.
296	* AMD64 host: Special mode used by NEM to indicate no shadow paging
297	* necessary. Not used by X86 guests. */
298	PGMMODE_NONE = 32,
299
300	/** @name ARMv8
301	* @{ */
302	/** VMSAv8-32 Virtual Memory System Architecture v8 - 32-bit variant enabled. */
303	PGMMODE_VMSA_V8_32,
304	/** VMSAv8-64 Virtual Memory System Architecture v8 - 64-bit variant enabled. */
305	PGMMODE_VMSA_V8_64,
306	/** @} */
307
308	/** The max number of modes */
309	PGMMODE_MAX,
310	/** 32bit hackishness. */
311	PGMMODE_32BIT_HACK = 0x7fffffff
312	} PGMMODE;
313
314
315	/**
316	* Second level address translation (SLAT) mode.
317	*/
318	typedef enum PGMSLAT
319	{
320	/** The usual invalid value. */
321	PGMSLAT_INVALID = 0,
322	/** No second level translation. */
323	PGMSLAT_DIRECT,
324	/** Intel Extended Page Tables (EPT). */
325	PGMSLAT_EPT,
326	/** AMD-V Nested Paging 32-bit. */
327	PGMSLAT_32BIT,
328	/** AMD-V Nested Paging PAE. */
329	PGMSLAT_PAE,
330	/** AMD-V Nested Paging 64-bit. */
331	PGMSLAT_AMD64,
332	/** 32bit hackishness. */
333	PGMSLAT_32BIT_HACK = 0x7fffffff
334	} PGMSLAT;
335
336
337	/** @name PGMPTWALK::fFailed flags.
338	* These flags indicate the type of a page-walk failure.
339	* @{
340	*/
341	typedef uint32_t PGMWALKFAIL;
342	/** No fault. */
343	#define PGM_WALKFAIL_SUCCESS UINT32_C(0)
344
345	/** Not present (X86_TRAP_PF_P). */
346	#define PGM_WALKFAIL_NOT_PRESENT RT_BIT_32(0)
347	/** Reserved bit set in table entry (X86_TRAP_PF_RSVD). */
348	#define PGM_WALKFAIL_RESERVED_BITS RT_BIT_32(1)
349	/** Bad physical address (VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS). */
350	#define PGM_WALKFAIL_BAD_PHYSICAL_ADDRESS RT_BIT_32(2)
351
352	/** EPT violation - Intel. */
353	#define PGM_WALKFAIL_EPT_VIOLATION RT_BIT_32(3)
354	/** EPT violation, convertible to \#VE exception - Intel. */
355	#define PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE RT_BIT_32(4)
356	/** EPT misconfiguration - Intel. */
357	#define PGM_WALKFAIL_EPT_MISCONFIG RT_BIT_32(5)
358	/** Mask of all EPT induced page-walk failures - Intel. */
359	#define PGM_WALKFAIL_EPT ( PGM_WALKFAIL_EPT_VIOLATION \
360	\| PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE \
361	\| PGM_WALKFAIL_EPT_MISCONFIG)
362
363	/** Access denied: Not writable (VERR_ACCESS_DENIED). */
364	#define PGM_WALKFAIL_NOT_WRITABLE RT_BIT_32(6)
365	/** Access denied: Not executable (VERR_ACCESS_DENIED). */
366	#define PGM_WALKFAIL_NOT_EXECUTABLE RT_BIT_32(7)
367	/** Access denied: Not user/supervisor mode accessible (VERR_ACCESS_DENIED). */
368	#define PGM_WALKFAIL_NOT_ACCESSIBLE_BY_MODE RT_BIT_32(8)
369
370	/** The level the problem arrised at.
371	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
372	* level 8. This is 0 on success. */
373	#define PGM_WALKFAIL_LEVEL_MASK UINT32_C(0x0000f100)
374	/** Level shift (see PGM_WALKFAIL_LEVEL_MASK). */
375	#define PGM_WALKFAIL_LEVEL_SHIFT 11
376
377	/** @} */
378
379
380	/** @name PGM_PTATTRS_XXX - PGM page-table attributes.
381	*
382	* This is VirtualBox's combined page table attributes. It combines regular page
383	* table and Intel EPT attributes. It's 64-bit in size so there's ample room for
384	* bits added in the future to EPT or regular page tables (for e.g. Protection Key).
385	*
386	* The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
387	* attributes as these are unique to EPT and fit within 64-bits despite the shift:
388	* - EPT_R : Read access.
389	* - EPT_W : Write access.
390	* - EPT_X_SUPER : Execute or execute for supervisor-mode linear addr access.
391	* - EPT_MEMTYPE : EPT memory type.
392	* - EPT_IGNORE_PAT: Ignore PAT memory type.
393	* - EPT_X_USER : Execute access for user-mode linear addresses.
394	*
395	* For regular page tables, the R bit is always 1 (same as P bit).
396	* For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
397	*
398	* The following EPT attributes are mapped to the following positions because they
399	* exist in the regular page tables at these positions OR are exclusive to EPT and
400	* have been mapped to arbitrarily chosen positions:
401	* - EPT_A : Accessed (EPT bit 8 maps to bit 5).
402	* - EPT_D : Dirty (EPT bit 9 maps to bit 6).
403	* - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
404	* - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
405	*
406	* Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
407	* 11:9 in the regular page-table structures and to bit 11 in the EPT structures
408	* respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
409	* use by software and we may want to use/preserve them in the future.
410	*
411	* @{ */
412	typedef uint64_t PGMPTATTRS;
413	/** Pointer to a PGMPTATTRS type. */
414	typedef PGMPTATTRS *PPGMPTATTRS;
415
416	/** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
417	#define PGM_PTATTRS_R_SHIFT 0
418	#define PGM_PTATTRS_R_MASK RT_BIT_64(PGM_PTATTRS_R_SHIFT)
419	/** Write access bit (aka read/write bit for regular PT). */
420	#define PGM_PTATTRS_W_SHIFT 1
421	#define PGM_PTATTRS_W_MASK RT_BIT_64(PGM_PTATTRS_W_SHIFT)
422	/** User-mode access bit. */
423	#define PGM_PTATTRS_US_SHIFT 2
424	#define PGM_PTATTRS_US_MASK RT_BIT_64(PGM_PTATTRS_US_SHIFT)
425	/** Write through cache bit. */
426	#define PGM_PTATTRS_PWT_SHIFT 3
427	#define PGM_PTATTRS_PWT_MASK RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
428	/** Cache disabled bit. */
429	#define PGM_PTATTRS_PCD_SHIFT 4
430	#define PGM_PTATTRS_PCD_MASK RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
431	/** Accessed bit. */
432	#define PGM_PTATTRS_A_SHIFT 5
433	#define PGM_PTATTRS_A_MASK RT_BIT_64(PGM_PTATTRS_A_SHIFT)
434	/** Dirty bit. */
435	#define PGM_PTATTRS_D_SHIFT 6
436	#define PGM_PTATTRS_D_MASK RT_BIT_64(PGM_PTATTRS_D_SHIFT)
437	/** The PAT bit. */
438	#define PGM_PTATTRS_PAT_SHIFT 7
439	#define PGM_PTATTRS_PAT_MASK RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
440	/** The global bit. */
441	#define PGM_PTATTRS_G_SHIFT 8
442	#define PGM_PTATTRS_G_MASK RT_BIT_64(PGM_PTATTRS_G_SHIFT)
443	/** Reserved (bits 12:9) unused. */
444	#define PGM_PTATTRS_RSVD_12_9_SHIFT 9
445	#define PGM_PTATTRS_RSVD_12_9_MASK UINT64_C(0x0000000000001e00)
446	/** Read access bit - EPT only. */
447	#define PGM_PTATTRS_EPT_R_SHIFT 13
448	#define PGM_PTATTRS_EPT_R_MASK RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
449	/** Write access bit - EPT only. */
450	#define PGM_PTATTRS_EPT_W_SHIFT 14
451	#define PGM_PTATTRS_EPT_W_MASK RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
452	/** Execute or execute access for supervisor-mode linear addresses - EPT only. */
453	#define PGM_PTATTRS_EPT_X_SUPER_SHIFT 15
454	#define PGM_PTATTRS_EPT_X_SUPER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
455	/** EPT memory type - EPT only. */
456	#define PGM_PTATTRS_EPT_MEMTYPE_SHIFT 16
457	#define PGM_PTATTRS_EPT_MEMTYPE_MASK UINT64_C(0x0000000000070000)
458	/** Ignore PAT memory type - EPT only. */
459	#define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT 19
460	#define PGM_PTATTRS_EPT_IGNORE_PAT_MASK RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
461	/** Leaf paging entry (big or regular) - EPT only. */
462	#define PGM_PTATTRS_EPT_LEAF_SHIFT 20
463	#define PGM_PTATTRS_EPT_LEAF_MASK RT_BIT_64(PGM_PTATTRS_EPT_LEAF_SHIFT)
464	/** Accessed bit - EPT only. */
465	#define PGM_PTATTRS_EPT_A_SHIFT 21
466	#define PGM_PTATTRS_EPT_A_MASK RT_BIT_64(PGM_PTATTRS_EPT_A_SHIFT)
467	/** Dirty bit - EPT only. */
468	#define PGM_PTATTRS_EPT_D_SHIFT 22
469	#define PGM_PTATTRS_EPT_D_MASK RT_BIT_64(PGM_PTATTRS_EPT_D_SHIFT)
470	/** Execute access for user-mode linear addresses - EPT only. */
471	#define PGM_PTATTRS_EPT_X_USER_SHIFT 23
472	#define PGM_PTATTRS_EPT_X_USER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
473	/** Reserved (bits 29:24) - unused. */
474	#define PGM_PTATTRS_RSVD_29_24_SHIFT 24
475	#define PGM_PTATTRS_RSVD_29_24_MASK UINT64_C(0x000000003f000000)
476	/** Verify Guest Paging - EPT only. */
477	#define PGM_PTATTRS_EPT_VGP_SHIFT 30
478	#define PGM_PTATTRS_EPT_VGP_MASK RT_BIT_64(PGM_PTATTRS_EPT_VGP_SHIFT)
479	/** Paging-write - EPT only. */
480	#define PGM_PTATTRS_EPT_PW_SHIFT 31
481	#define PGM_PTATTRS_EPT_PW_MASK RT_BIT_64(PGM_PTATTRS_EPT_PW_SHIFT)
482	/** Reserved (bit 32) - unused. */
483	#define PGM_PTATTRS_RSVD_32_SHIFT 32
484	#define PGM_PTATTRS_RSVD_32_MASK UINT64_C(0x0000000100000000)
485	/** Supervisor shadow stack - EPT only. */
486	#define PGM_PTATTRS_EPT_SSS_SHIFT 33
487	#define PGM_PTATTRS_EPT_SSS_MASK RT_BIT_64(PGM_PTATTRS_EPT_SSS_SHIFT)
488	/** Sub-page write permission - EPT only. */
489	#define PGM_PTATTRS_EPT_SPP_SHIFT 34
490	#define PGM_PTATTRS_EPT_SPP_MASK RT_BIT_64(PGM_PTATTRS_EPT_SPP_SHIFT)
491	/** Reserved (bit 35) - unused. */
492	#define PGM_PTATTRS_RSVD_35_SHIFT 35
493	#define PGM_PTATTRS_RSVD_35_MASK UINT64_C(0x0000000800000000)
494	/** Suppress \#VE exception - EPT only. */
495	#define PGM_PTATTRS_EPT_SVE_SHIFT 36
496	#define PGM_PTATTRS_EPT_SVE_MASK RT_BIT_64(PGM_PTATTRS_EPT_SVE_SHIFT)
497	/** Reserved (bits 62:37) - unused. */
498	#define PGM_PTATTRS_RSVD_62_37_SHIFT 37
499	#define PGM_PTATTRS_RSVD_62_37_MASK UINT64_C(0x7fffffe000000000)
500	/** No-execute bit. */
501	#define PGM_PTATTRS_NX_SHIFT 63
502	#define PGM_PTATTRS_NX_MASK RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
503
504	RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
505	(R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
506	EPT_LEAF, EPT_A, EPT_D, EPT_X_USER, RSVD_29_24, EPT_VGP, EPT_PW, RSVD_32, EPT_SSS, EPT_SPP,
507	RSVD_35, EPT_SVE, RSVD_62_37, NX));
508
509	/** The bit position where the EPT specific attributes begin. */
510	#define PGM_PTATTRS_EPT_SHIFT PGM_PTATTRS_EPT_R_SHIFT
511	/** The mask of EPT bits (bits 36:ATTR_SHIFT). In the future we might choose to
512	* use higher unused bits for something else, in that case adjust this mask. */
513	#define PGM_PTATTRS_EPT_MASK UINT64_C(0x0000001fffffe000)
514
515	/** The mask of all PGM page attribute bits for regular page-tables. */
516	#define PGM_PTATTRS_PT_VALID_MASK ( PGM_PTATTRS_R_MASK \
517	\| PGM_PTATTRS_W_MASK \
518	\| PGM_PTATTRS_US_MASK \
519	\| PGM_PTATTRS_PWT_MASK \
520	\| PGM_PTATTRS_PCD_MASK \
521	\| PGM_PTATTRS_A_MASK \
522	\| PGM_PTATTRS_D_MASK \
523	\| PGM_PTATTRS_PAT_MASK \
524	\| PGM_PTATTRS_G_MASK \
525	\| PGM_PTATTRS_NX_MASK)
526
527	/** The mask of all PGM page attribute bits for EPT. */
528	#define PGM_PTATTRS_EPT_VALID_MASK ( PGM_PTATTRS_EPT_R_MASK \
529	\| PGM_PTATTRS_EPT_W_MASK \
530	\| PGM_PTATTRS_EPT_X_SUPER_MASK \
531	\| PGM_PTATTRS_EPT_MEMTYPE_MASK \
532	\| PGM_PTATTRS_EPT_IGNORE_PAT_MASK \
533	\| PGM_PTATTRS_EPT_LEAF_MASK \
534	\| PGM_PTATTRS_EPT_A_MASK \
535	\| PGM_PTATTRS_EPT_D_MASK \
536	\| PGM_PTATTRS_EPT_X_USER_MASK \
537	\| PGM_PTATTRS_EPT_VGP_MASK \
538	\| PGM_PTATTRS_EPT_PW_MASK \
539	\| PGM_PTATTRS_EPT_SSS_MASK \
540	\| PGM_PTATTRS_EPT_SPP_MASK \
541	\| PGM_PTATTRS_EPT_SVE_MASK)
542
543	/* The mask of all PGM page attribute bits (combined). */
544	#define PGM_PTATTRS_VALID_MASK (PGM_PTATTRS_PT_VALID_MASK \| PGM_PTATTRS_EPT_VALID_MASK)
545
546	/* Verify bits match the regular PT bits. */
547	AssertCompile(PGM_PTATTRS_W_SHIFT == X86_PTE_BIT_RW);
548	AssertCompile(PGM_PTATTRS_US_SHIFT == X86_PTE_BIT_US);
549	AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
550	AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
551	AssertCompile(PGM_PTATTRS_A_SHIFT == X86_PTE_BIT_A);
552	AssertCompile(PGM_PTATTRS_D_SHIFT == X86_PTE_BIT_D);
553	AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
554	AssertCompile(PGM_PTATTRS_G_SHIFT == X86_PTE_BIT_G);
555	AssertCompile(PGM_PTATTRS_W_MASK == X86_PTE_RW);
556	AssertCompile(PGM_PTATTRS_US_MASK == X86_PTE_US);
557	AssertCompile(PGM_PTATTRS_PWT_MASK == X86_PTE_PWT);
558	AssertCompile(PGM_PTATTRS_PCD_MASK == X86_PTE_PCD);
559	AssertCompile(PGM_PTATTRS_A_MASK == X86_PTE_A);
560	AssertCompile(PGM_PTATTRS_D_MASK == X86_PTE_D);
561	AssertCompile(PGM_PTATTRS_PAT_MASK == X86_PTE_PAT);
562	AssertCompile(PGM_PTATTRS_G_MASK == X86_PTE_G);
563	AssertCompile(PGM_PTATTRS_NX_MASK == X86_PTE_PAE_NX);
564
565	/* Verify those EPT bits that must map 1:1 (after shifting). */
566	AssertCompile(PGM_PTATTRS_EPT_R_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
567	AssertCompile(PGM_PTATTRS_EPT_W_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
568	AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
569	AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
570	AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
571	/** @} */
572
573
574	/**
575	* Page table walk information.
576	*
577	* This provides extensive information regarding page faults (or EPT
578	* violations/misconfigurations) while traversing page tables.
579	*/
580	typedef struct PGMPTWALK
581	{
582	/** The linear address that is being resolved (input). */
583	RTGCPTR GCPtr;
584
585	/** The second-level physical address (input/output).
586	* @remarks only valid if fIsSlat is set. */
587	RTGCPHYS GCPhysNested;
588
589	/** The physical address that is the result of the walk (output). */
590	RTGCPHYS GCPhys;
591
592	/** Set if the walk succeeded. */
593	bool fSucceeded;
594	/** Whether this is a second-level address translation. */
595	bool fIsSlat;
596	/** Whether the linear address (GCPtr) caused the second-level
597	* address translation. */
598	bool fIsLinearAddrValid;
599	/** The level problem arrised at.
600	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
601	* level 8. This is 0 on success. */
602	uint8_t uLevel;
603	/** Set if the page isn't present. */
604	bool fNotPresent;
605	/** Encountered a bad physical address. */
606	bool fBadPhysAddr;
607	/** Set if there was reserved bit violations. */
608	bool fRsvdError;
609	/** Set if it involves a big page (2/4 MB). */
610	bool fBigPage;
611	/** Set if it involves a gigantic page (1 GB). */
612	bool fGigantPage;
613	bool afPadding[3];
614	/** Page-walk failure type, PGM_WALKFAIL_XXX. */
615	PGMWALKFAIL fFailed;
616
617	/** The effective page-table attributes, PGM_PTATTRS_XXX. */
618	PGMPTATTRS fEffective;
619	} PGMPTWALK;
620	/** Pointer to page walk information. */
621	typedef PGMPTWALK *PPGMPTWALK;
622	/** Pointer to const page walk information. */
623	typedef PGMPTWALK const *PCPGMPTWALK;
624
625
626	/** @name PGM_WALKINFO_XXX - flag based PGM page table walk info.
627	* @{ */
628	/** Set if the walk succeeded. */
629	#define PGM_WALKINFO_SUCCEEDED RT_BIT_32(0)
630	/** Whether this is a second-level address translation. */
631	#define PGM_WALKINFO_IS_SLAT RT_BIT_32(1)
632
633	/** Set if it involves a big page (2/4 MB). */
634	#define PGM_WALKINFO_BIG_PAGE RT_BIT_32(7)
635	/** Set if it involves a gigantic page (1 GB). */
636	#define PGM_WALKINFO_GIGANTIC_PAGE RT_BIT_32(8)
637
638	/** Whether the linear address (GCPtr) caused the second-level
639	* address translation - read the code to figure this one.
640	* @todo for PGMPTWALKFAST::fFailed? */
641	#define PGM_WALKINFO_IS_LINEAR_ADDR_VALID RT_BIT_32(10)
642	/** @} */
643
644	/**
645	* Fast page table walk information.
646	*
647	* This is a slimmed down version of PGMPTWALK for use by IEM.
648	*/
649	typedef struct PGMPTWALKFAST
650	{
651	/** The linear address that is being resolved (input). */
652	RTGCPTR GCPtr;
653
654	/** The physical address that is the result of the walk (output).
655	* This includes the offset mask from the GCPtr input value. */
656	RTGCPHYS GCPhys;
657
658	/** The second-level physical address (input/output).
659	* @remarks only valid if fIsSlat is set. */
660	RTGCPHYS GCPhysNested;
661
662	/** Walk information PGM_WALKINFO_XXX (output). */
663	uint32_t fInfo;
664	/** Page-walk failure type, PGM_WALKFAIL_XXX (output). */
665	PGMWALKFAIL fFailed;
666
667	/** The effective page-table attributes, PGM_PTATTRS_XXX (output). */
668	PGMPTATTRS fEffective;
669	} PGMPTWALKFAST;
670	/** Pointer to fast page walk information. */
671	typedef PGMPTWALKFAST *PPGMPTWALKFAST;
672	/** Pointer to const fast page walk information. */
673	typedef PGMPTWALKFAST const *PCPGMPTWALKFAST;
674
675	#define PGMPTWALKFAST_ZERO(a_pWalkFast) do { \
676	(a_pWalkFast)->GCPtr = 0; \
677	(a_pWalkFast)->GCPhys = 0; \
678	(a_pWalkFast)->GCPhysNested = 0; \
679	(a_pWalkFast)->fInfo = 0; \
680	(a_pWalkFast)->fFailed = 0; \
681	(a_pWalkFast)->fEffective = 0; \
682	} while (0)
683
684
685	#ifndef VBOX_VMM_TARGET_ARMV8
686	/** Macro for checking if the guest is using paging.
687	* @param enmMode PGMMODE_*.
688	* @remark ASSUMES certain order of the PGMMODE_* values.
689	*/
690	# define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
691
692	/** Macro for checking if it's one of the long mode modes.
693	* @param enmMode PGMMODE_*.
694	*/
695	# define PGMMODE_IS_64BIT_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
696
697	/** Macro for checking if it's one of the AMD64 nested modes.
698	* @param enmMode PGMMODE_*.
699	*/
700	# define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
701	\|\| (enmMode) == PGMMODE_NESTED_PAE \
702	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
703
704	/** Macro for checking if it's one of the PAE modes.
705	* @param enmMode PGMMODE_*.
706	*/
707	# define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
708	\|\| (enmMode) == PGMMODE_PAE_NX)
709	#else
710	/** Macro for checking if the guest is using paging.
711	* @param enmMode PGMMODE_*.
712	* @remark ASSUMES certain order of the PGMMODE_* values.
713	*/
714	# define PGMMODE_WITH_PAGING(enmMode) ((enmMode) > PGMMODE_NONE)
715
716	/** Macro for checking if it's the 64-bit translation mode.
717	* @param enmMode PGMMODE_*.
718	*/
719	# define PGMMODE_IS_64BIT_MODE(enmMode) ((enmMode) == PGMMODE_VMSA_V8_64)
720	#endif
721
722
723	/**
724	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
725	*
726	* @returns boolean.
727	* @param enmProt The PGMROMPROT value, must be valid.
728	*/
729	#define PGMROMPROT_IS_ROM(enmProt) \
730	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
731	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
732
733
734	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
735
736	VMMDECL(int) PGMRegisterStringFormatTypes(void);
737	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
738	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
739	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault);
740	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
741	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault);
742	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
743	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
744	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
745	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
746	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
747	* PGMShwMakePageNotPresent
748	* @{ */
749	/** The call is from an access handler for dealing with the a faulting write
750	* operation. The virtual address is within the same page. */
751	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
752	/** The page is an MMIO2. */
753	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
754	/** @}*/
755	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
756	/** @name PGMQPAGE_F_XXX - Flags for PGMGstQueryPageFast
757	* @{ */
758	/** Querying for read access, set A bits accordingly. */
759	#define PGMQPAGE_F_READ RT_BIT_32(0)
760	/** Querying for write access, set A bits and D bit accordingly.
761	* Don't set leaf entry bits if is read-only. */
762	#define PGMQPAGE_F_WRITE RT_BIT_32(1)
763	/** Querying for execute access, set A bits accordingly. */
764	#define PGMQPAGE_F_EXECUTE RT_BIT_32(2)
765	/** The query is for a user mode access, so don't set leaf A or D bits
766	* unless the effective access allows usermode access.
767	* Assume supervisor access when not set. */
768	#define PGMQPAGE_F_USER_MODE RT_BIT_32(3)
769	/** Treat CR0.WP as zero when evalutating the access.
770	* @note Same value as X86_CR0_WP. */
771	#define PGMQPAGE_F_CR0_WP0 RT_BIT_32(16)
772	/** The valid flag mask. */
773	#define PGMQPAGE_F_VALID_MASK UINT32_C(0x0001000f)
774	/** @} */
775	VMM_INT_DECL(int) PGMGstQueryPageFast(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags, PPGMPTWALKFAST pWalkFast);
776	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
777	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
778	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
779	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
780
781	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
782	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
783	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
784	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
785	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce);
786	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode, bool fForce);
787	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
788	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
789	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
790	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
791	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
792	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
793	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode);
794	#endif
795	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
796	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
797	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr);
798
799	/** PGM physical access handler type registration handle (heap offset, valid
800	* cross contexts without needing fixing up). Callbacks and handler type is
801	* associated with this and it is shared by all handler registrations. */
802	typedef uint64_t PGMPHYSHANDLERTYPE;
803	/** Pointer to a PGM physical handler type registration handle. */
804	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
805	/** NIL value for PGM physical access handler type handle. */
806	#define NIL_PGMPHYSHANDLERTYPE UINT64_MAX
807	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
808	uint64_t uUser, R3PTRTYPE(const char *) pszDesc);
809	VMMDECL(int) PGMHandlerPhysicalRegisterVmxApicAccessPage(PVMCC pVM, RTGCPHYS GCPhys, PGMPHYSHANDLERTYPE hType);
810	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
811	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
812	VMMDECL(int) PGMHandlerPhysicalChangeUserArg(PVMCC pVM, RTGCPHYS GCPhys, uint64_t uUser);
813	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
814	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
815	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
816	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
817	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
818	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
819	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
820	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
821
822	/** @name PGMPHYSHANDLER_F_XXX - flags for PGMR3HandlerPhysicalTypeRegister and PGMR0HandlerPhysicalTypeRegister
823	* @{ */
824	/** Whether to hold the PGM lock while calling the handler or not.
825	* Mainly an optimization for PGM callers. */
826	#define PGMPHYSHANDLER_F_KEEP_PGM_LOCK RT_BIT_32(0)
827	/** The uUser value is a ring-0 device instance index that needs translating
828	* into a PDMDEVINS pointer before calling the handler. This is a hack to make
829	* it possible to use access handlers in devices. */
830	#define PGMPHYSHANDLER_F_R0_DEVINS_IDX RT_BIT_32(1)
831	/** Don't apply the access handler to VT-x and AMD-V. Only works with full pages.
832	* This is a trick for the VT-x APIC access page in nested VT-x setups. */
833	#define PGMPHYSHANDLER_F_NOT_IN_HM RT_BIT_32(2)
834	/** Mask of valid bits. */
835	#define PGMPHYSHANDLER_F_VALID_MASK UINT32_C(7)
836	/** @} */
837
838
839	/**
840	* Page type.
841	*
842	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
843	* @remarks This is used in the saved state, so changes to it requires bumping
844	* the saved state version.
845	* @todo So, convert to \#defines!
846	*/
847	typedef enum PGMPAGETYPE
848	{
849	/** The usual invalid zero entry. */
850	PGMPAGETYPE_INVALID = 0,
851	/** RAM page. (RWX) */
852	PGMPAGETYPE_RAM,
853	/** MMIO2 page. (RWX) */
854	PGMPAGETYPE_MMIO2,
855	/** MMIO2 page aliased over an MMIO page. (RWX)
856	* See PGMHandlerPhysicalPageAlias(). */
857	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
858	/** Special page aliased over an MMIO page. (RWX)
859	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
860	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
861	* the shadow paging code. */
862	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
863	/** Shadowed ROM. (RWX) */
864	PGMPAGETYPE_ROM_SHADOW,
865	/** ROM page. (R-X) */
866	PGMPAGETYPE_ROM,
867	/** MMIO page. (---) */
868	PGMPAGETYPE_MMIO,
869	/** End of valid entries. */
870	PGMPAGETYPE_END
871	} PGMPAGETYPE;
872	AssertCompile(PGMPAGETYPE_END == 8);
873
874	/** @name PGM page type predicates.
875	* @{ */
876	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
877	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
878	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
879	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
880	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
881	/** @} */
882
883	/**
884	* A physical memory range.
885	*
886	* @note This layout adheres to to GIM Hyper-V specs (asserted while compiling
887	* GIM Hyper-V that uses the PGM API).
888	*/
889	typedef struct PGMPHYSRANGE
890	{
891	/** The first address in the range. */
892	RTGCPHYS GCPhysStart;
893	/** The number of pages in the range. */
894	uint64_t cPages;
895	} PGMPHYSRANGE;
896	AssertCompileSize(PGMPHYSRANGE, 16);
897
898	/**
899	* A list of physical memory ranges.
900	*
901	* @note This layout adheres to to GIM Hyper-V specs (asserted while compiling
902	* GIM Hyper-V that uses the PGM API).
903	*/
904	typedef struct PGMPHYSRANGES
905	{
906	/** The number of ranges in the list. */
907	uint64_t cRanges;
908	/** Array of physical memory ranges. */
909	RT_FLEXIBLE_ARRAY_EXTENSION
910	PGMPHYSRANGE aRanges[RT_FLEXIBLE_ARRAY];
911	} PGMPHYSRANGES;
912	/** Pointer to a list of physical memory ranges. */
913	typedef PGMPHYSRANGES *PPGMPHYSRANGES;
914	/** Pointer to a const list of physical memory ranges. */
915	typedef PGMPHYSRANGES const *PCPGMPHYSRANGES;
916
917
918	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
919
920	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
921	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
922	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
923	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
924	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
925	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
926
927	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
928	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
929	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
930	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
931	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
932	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
933
934	/** @def PGM_PHYS_RW_IS_SUCCESS
935	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
936	* PGMPhysWriteGCPtr call completed the given task.
937	*
938	* @returns true if completed, false if not.
939	* @param a_rcStrict The status code.
940	* @sa IOM_SUCCESS
941	*/
942	#ifdef IN_RING3
943	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
944	( (a_rcStrict) == VINF_SUCCESS \
945	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
946	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
947	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
948	)
949	#elif defined(IN_RING0)
950	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
951	( (a_rcStrict) == VINF_SUCCESS \
952	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
953	\|\| (a_rcStrict) == VINF_EM_OFF \
954	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
955	\|\| (a_rcStrict) == VINF_EM_RESET \
956	\|\| (a_rcStrict) == VINF_EM_HALT \
957	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
958	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
959	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
960	)
961	#elif defined(IN_RC)
962	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
963	( (a_rcStrict) == VINF_SUCCESS \
964	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
965	\|\| (a_rcStrict) == VINF_EM_OFF \
966	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
967	\|\| (a_rcStrict) == VINF_EM_RESET \
968	\|\| (a_rcStrict) == VINF_EM_HALT \
969	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
970	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
971	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
972	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
973	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
974	)
975	#endif
976	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
977	* Updates the return code with a new result.
978	*
979	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
980	*
981	* @param a_rcStrict The current return code, to be updated.
982	* @param a_rcStrict2 The new return code to merge in.
983	*/
984	#ifdef IN_RING3
985	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
986	do { \
987	Assert(rcStrict == VINF_SUCCESS); \
988	Assert(rcStrict2 == VINF_SUCCESS); \
989	} while (0)
990	#elif defined(IN_RING0)
991	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
992	do { \
993	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
994	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
995	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
996	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
997	{ /* likely */ } \
998	else if ( (a_rcStrict) == VINF_SUCCESS \
999	\|\| (a_rcStrict) > (a_rcStrict2)) \
1000	(a_rcStrict) = (a_rcStrict2); \
1001	} while (0)
1002	#elif defined(IN_RC)
1003	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
1004	do { \
1005	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
1006	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
1007	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
1008	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
1009	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
1010	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
1011	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
1012	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
1013	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
1014	{ /* likely */ } \
1015	else if ((a_rcStrict) == VINF_SUCCESS) \
1016	(a_rcStrict) = (a_rcStrict2); \
1017	else if ( ( (a_rcStrict) > (a_rcStrict2) \
1018	&& ( (a_rcStrict2) <= VINF_EM_RESET \
1019	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
1020	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
1021	&& (a_rcStrict) > VINF_EM_RESET) ) \
1022	(a_rcStrict) = (a_rcStrict2); \
1023	} while (0)
1024	#endif
1025
1026	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1027	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1028	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
1029	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
1030
1031	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
1032	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
1033	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
1034	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
1035	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
1036
1037	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
1038	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
1039	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
1040	R3R0PTRTYPE(uint8_t ) ppb, uint64_t *pfTlb);
1041	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
1042	* @{ */
1043	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
1044	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
1045	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(8) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
1046	#define PGMIEMGCPHYS2PTR_F_UNASSIGNED RT_BIT_32(9) /*< Unassgined memory (IEMTLBE_F_PG_UNASSIGNED). /
1047	#define PGMIEMGCPHYS2PTR_F_CODE_PAGE RT_BIT_32(10) /*< Write monitored IEM code page (IEMTLBE_F_PG_CODE_PAGE). /
1048	/** @} */
1049
1050	/** Information returned by PGMPhysNemQueryPageInfo. */
1051	typedef struct PGMPHYSNEMPAGEINFO
1052	{
1053	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
1054	RTHCPHYS HCPhys;
1055	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
1056	uint32_t fNemProt : 8;
1057	/** The NEM state associated with the PAGE. */
1058	uint32_t u2NemState : 2;
1059	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
1060	uint32_t u2OldNemState : 2;
1061	/** Set if the page has handler. */
1062	uint32_t fHasHandlers : 1;
1063	/** Set if is the zero page backing it. */
1064	uint32_t fZeroPage : 1;
1065	/** Set if the page has handler. */
1066	PGMPAGETYPE enmType;
1067	} PGMPHYSNEMPAGEINFO;
1068	/** Pointer to page information for NEM. */
1069	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
1070	/**
1071	* Callback for checking that the page is in sync while under the PGM lock.
1072	*
1073	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
1074	* in-sync between PGM and the native hypervisor API in an atomic fashion.
1075	*
1076	* @returns VBox status code.
1077	* @param pVM The cross context VM structure.
1078	* @param pVCpu The cross context per virtual CPU structure. Optional,
1079	* see PGMPhysNemQueryPageInfo.
1080	* @param GCPhys The guest physical address (not A20 masked).
1081	* @param pInfo The page info structure. This function updates the
1082	* u2NemState memory and the caller will update the PGMPAGE
1083	* copy accordingly.
1084	* @param pvUser Callback user argument.
1085	*/
1086	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
1087	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
1088	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
1089
1090	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
1091	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
1092
1093	/**
1094	* Callback for use with PGMPhysNemEnumPagesByState.
1095	* @returns VBox status code.
1096	* Failure status will stop enumeration immediately and return.
1097	* @param pVM The cross context VM structure.
1098	* @param pVCpu The cross context per virtual CPU structure. Optional,
1099	* see PGMPhysNemEnumPagesByState.
1100	* @param GCPhys The guest physical address (not A20 masked).
1101	* @param pu2NemState Pointer to variable with the NEM state. This can be
1102	* update.
1103	* @param pvUser The user argument.
1104	*/
1105	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
1106	uint8_t pu2NemState, void pvUser));
1107	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
1108	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
1109	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
1110	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
1111
1112
1113	#ifdef VBOX_STRICT
1114	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
1115	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
1116	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
1117	#endif /* VBOX_STRICT */
1118
1119	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
1120
1121	/**
1122	* Query large page usage state
1123	*
1124	* @returns 0 - disabled, 1 - enabled
1125	* @param pVM The cross context VM structure.
1126	*/
1127	#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
1128
1129
1130	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
1131	* @{
1132	*/
1133	#ifdef IN_RING0
1134	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM, RTR0MEMOBJ hMemObj);
1135	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
1136	VMMR0_INT_DECL(void) PGMR0DoneInitVM(PGVM pGVM);
1137	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
1138	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
1139	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
1140	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
1141	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1142	size_t offSub, size_t cbSub, void **ppvMapping);
1143	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
1144	VMMR0_INT_DECL(int) PGMR0PhysHandlerInitReqHandler(PGVM pGVM, uint32_t cEntries);
1145
1146	VMMR0_INT_DECL(int) PGMR0HandlerPhysicalTypeSetUpContext(PGVM pGVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1147	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
1148	const char *pszDesc, PGMPHYSHANDLERTYPE hType);
1149
1150	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
1151	PCRTGCPTR64 paRegionsGCPtrs);
1152	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
1153	PCPUMCTX pCtx, RTGCPHYS pvFault);
1154	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
1155	PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr);
1156	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
1157
1158	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1159	VMMR0DECL(VBOXSTRICTRC) PGMR0NestedTrap0eHandlerNestedPaging(PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
1160	PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
1161	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk);
1162	# endif
1163	#endif /* IN_RING0 */
1164
1165	/**
1166	* Request buffer for PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_ALLOCATE_RAM_RANGE
1167	*/
1168	typedef struct PGMPHYSALLOCATERAMRANGEREQ
1169	{
1170	/** The header. */
1171	SUPVMMR0REQHDR Hdr;
1172	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1173	uint32_t cbGuestPage;
1174	/** Input: Number of guest pages in the range. */
1175	uint32_t cGuestPages;
1176	/** Input: The RAM range flags (PGM_RAM_RANGE_FLAGS_XXX). */
1177	uint32_t fFlags;
1178	/** Output: The range identifier. */
1179	uint32_t idNewRange;
1180	} PGMPHYSALLOCATERAMRANGEREQ;
1181	/** Pointer to a PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_ALLOCATE_RAM_RANGE request buffer. */
1182	typedef PGMPHYSALLOCATERAMRANGEREQ *PPGMPHYSALLOCATERAMRANGEREQ;
1183
1184	VMMR0_INT_DECL(int) PGMR0PhysAllocateRamRangeReq(PGVM pGVM, PPGMPHYSALLOCATERAMRANGEREQ pReq);
1185
1186
1187	/**
1188	* Request buffer for PGMR0PhysMmio2RegisterReq / VMMR0_DO_PGM_PHYS_MMIO2_REGISTER
1189	*/
1190	typedef struct PGMPHYSMMIO2REGISTERREQ
1191	{
1192	/** The header. */
1193	SUPVMMR0REQHDR Hdr;
1194	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1195	uint32_t cbGuestPage;
1196	/** Input: Number of guest pages in the MMIO2 range. */
1197	uint32_t cGuestPages;
1198	/** Input: The MMIO2 ID of the first chunk. */
1199	uint8_t idMmio2;
1200	/** Input: The number of MMIO2 chunks needed. */
1201	uint8_t cChunks;
1202	/** Input: The sub-device number. */
1203	uint8_t iSubDev;
1204	/** Input: The device region number. */
1205	uint8_t iRegion;
1206	/** Input: Flags (PGMPHYS_MMIO2_FLAGS_XXX). */
1207	uint32_t fFlags;
1208	/** Input: The owner device key. */
1209	PPDMDEVINSR3 pDevIns;
1210	} PGMPHYSMMIO2REGISTERREQ;
1211	/** Pointer to a PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_MMIO2_REGISTER request buffer. */
1212	typedef PGMPHYSMMIO2REGISTERREQ *PPGMPHYSMMIO2REGISTERREQ;
1213
1214	VMMR0_INT_DECL(int) PGMR0PhysMmio2RegisterReq(PGVM pGVM, PPGMPHYSMMIO2REGISTERREQ pReq);
1215
1216
1217	/*
1218	* Request buffer for PGMR0PhysMmio2DeregisterReq / VMMR0_DO_PGM_PHYS_MMIO2_DEREGISTER
1219	*/
1220	typedef struct PGMPHYSMMIO2DEREGISTERREQ
1221	{
1222	/** The header. */
1223	SUPVMMR0REQHDR Hdr;
1224	/** Input: The MMIO2 ID of the first chunk. */
1225	uint8_t idMmio2;
1226	/** Input: The number of MMIO2 chunks to free. */
1227	uint8_t cChunks;
1228	/** Input: Reserved and must be zero. */
1229	uint8_t abReserved[6];
1230	/** Input: The owner device key. */
1231	PPDMDEVINSR3 pDevIns;
1232	} PGMPHYSMMIO2DEREGISTERREQ;
1233	/** Pointer to a PGMR0PhysMmio2DeregisterReq / VMMR0_DO_PGM_PHYS_MMIO2_DEREGISTER request buffer. */
1234	typedef PGMPHYSMMIO2DEREGISTERREQ *PPGMPHYSMMIO2DEREGISTERREQ;
1235
1236	VMMR0_INT_DECL(int) PGMR0PhysMmio2DeregisterReq(PGVM pGVM, PPGMPHYSMMIO2DEREGISTERREQ pReq);
1237
1238	/*
1239	* Request buffer for PGMR0PhysRomAllocateRangeReq / VMMR0_DO_PGM_PHYS_ROM_ALLOCATE_RANGE
1240	*/
1241	typedef struct PGMPHYSROMALLOCATERANGEREQ
1242	{
1243	/** The header. */
1244	SUPVMMR0REQHDR Hdr;
1245	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1246	uint32_t cbGuestPage;
1247	/** Input: Number of guest pages in the range. */
1248	uint32_t cGuestPages;
1249	/** Input: The ROM range ID (index) to be allocated. */
1250	uint32_t idRomRange;
1251	/** Input: The ROM range flags (PGMPHYS_ROM_FLAGS_XXX). */
1252	uint32_t fFlags;
1253	} PGMPHYSROMALLOCATERANGEREQ;
1254	/* Pointer to a PGMR0PhysRomAllocateRangeReq / VMMR0_DO_PGM_PHYS_ROM_ALLOCATE_RANGE request buffer. */
1255	typedef PGMPHYSROMALLOCATERANGEREQ *PPGMPHYSROMALLOCATERANGEREQ;
1256
1257	VMMR0_INT_DECL(int) PGMR0PhysRomAllocateRangeReq(PGVM pGVM, PPGMPHYSROMALLOCATERANGEREQ pReq);
1258
1259
1260	/** @} */
1261
1262
1263
1264	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
1265	* @{
1266	*/
1267	#ifdef IN_RING3
1268	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
1269	VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM);
1270	VMMR3DECL(int) PGMR3Init(PVM pVM);
1271	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
1272	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1273	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
1274	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1275	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
1276	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
1277	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
1278	VMMR3DECL(int) PGMR3Term(PVM pVM);
1279
1280	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
1281	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
1282	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
1283	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
1284	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1285	const char *ppszDesc, bool pfIsMmio);
1286	VMMR3_INT_DECL(int) PGMR3PhysGetRamBootZeroedRanges(PVM pVM, PPGMPHYSRANGES pRanges, uint32_t cMaxRanges);
1287	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
1288	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
1289
1290	VMMR3_INT_DECL(int) PGMR3PhysMmioRegister(PVM pVM, PVMCPU pVCpu, RTGCPHYS cb, const char pszDesc, uint16_t pidRamRange);
1291	VMMR3_INT_DECL(int) PGMR3PhysMmioMap(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, uint16_t idRamRange,
1292	PGMPHYSHANDLERTYPE hType, uint64_t uUser);
1293	VMMR3_INT_DECL(int) PGMR3PhysMmioUnmap(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, uint16_t idRamRange);
1294	#endif /* IN_RING3 */
1295
1296	/** @name PGMPHYS_MMIO2_FLAGS_XXX - MMIO2 registration flags.
1297	* @see PGMR3PhysMmio2Register, PDMDevHlpMmio2Create
1298	* @{ */
1299	/** Track dirty pages.
1300	* @see PGMR3PhysMmio2QueryAndResetDirtyBitmap(), PGMR3PhysMmio2ControlDirtyPageTracking(). */
1301	#define PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES RT_BIT_32(0)
1302	/** Valid flags. */
1303	#define PGMPHYS_MMIO2_FLAGS_VALID_MASK UINT32_C(0x00000001)
1304	/** @} */
1305
1306	#ifdef IN_RING3
1307	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
1308	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
1309	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1310	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1311	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1312	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
1313	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1314	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1315	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
1316	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1317	void *pvBitmap, size_t cbBitmap);
1318	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled);
1319	#endif /* IN_RING3 */
1320
1321	/** @name PGMPHYS_ROM_FLAGS_XXX - ROM registration flags.
1322	* @see PGMR3PhysRegisterRom, PDMDevHlpROMRegister
1323	* @{ */
1324	/** Inidicates that ROM shadowing should be enabled. */
1325	#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
1326	/** Indicates that what pvBinary points to won't go away
1327	* and can be used for strictness checks. */
1328	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
1329	/** Indicates that the ROM is allowed to be missing from saved state.
1330	* @note This is a hack for EFI, see @bugref{6940} */
1331	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
1332	/** Valid flags. */
1333	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
1334	/** @} */
1335
1336	#ifdef IN_RING3
1337	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1338	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc);
1339	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
1340	# if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
1341	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
1342	# endif
1343
1344	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1345	PFNPGMPHYSHANDLER pfnHandlerR3, const char *pszDesc,
1346	PPGMPHYSHANDLERTYPE phType);
1347
1348	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
1349
1350	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
1351	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1352	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1353	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1354	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1355	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
1356	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
1357	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
1358	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
1359	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1360	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1361	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
1362	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
1363	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1364	void **papvPages, PPGMPAGEMAPLOCK paLocks);
1365	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1366	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
1367	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
1368
1369	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
1370
1371	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
1372	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
1373	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
1374	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1375	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1376	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1377	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1378	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
1379	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
1380	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1381	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1382	#endif /* IN_RING3 */
1383
1384	/** @name Page sharing
1385	* @{ */
1386	#ifdef IN_RING3
1387	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
1388	RTGCPTR GCBaseAddr, uint32_t cbModule,
1389	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
1390	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
1391	RTGCPTR GCBaseAddr, uint32_t cbModule);
1392	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
1393	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
1394	#endif /* IN_RING3 */
1395	/** @} */
1396
1397	/** @} */
1398
1399	RT_C_DECLS_END
1400
1401	/** @} */
1402	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
1403

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 108326

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