pgm.h@ 105177

最後變更在這個檔案從105177是 105177,由 vboxsync 提交於 8 月前
VMM/IEM: Increase TLB size to 8192 on arm; quick fix for 2M/4M page problem with invlpg. On AMD64 we stick to 256 TLB entries for VM struct size reasons. bugref:10687
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.alldomusa.eu.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_pgm_h
37	#define VBOX_INCLUDED_vmm_pgm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <VBox/sup.h>
44	#include <VBox/vmm/vmapi.h>
45	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
46	#include <VBox/vmm/hm_vmx.h>
47	#include <iprt/x86.h>
48	#include <VBox/param.h>
49
50	RT_C_DECLS_BEGIN
51
52	/** @defgroup grp_pgm The Page Monitor / Manager API
53	* @ingroup grp_vmm
54	* @{
55	*/
56
57	/**
58	* FNPGMRELOCATE callback mode.
59	*/
60	typedef enum PGMRELOCATECALL
61	{
62	/** The callback is for checking if the suggested address is suitable. */
63	PGMRELOCATECALL_SUGGEST = 1,
64	/** The callback is for executing the relocation. */
65	PGMRELOCATECALL_RELOCATE
66	} PGMRELOCATECALL;
67
68
69	/**
70	* Callback function which will be called when PGM is trying to find
71	* a new location for the mapping.
72	*
73	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
74	* In 1) the callback should say if it objects to a suggested new location. If it
75	* accepts the new location, it is called again for doing it's relocation.
76	*
77	*
78	* @returns true if the location is ok.
79	* @returns false if another location should be found.
80	* @param pVM The cross context VM structure.
81	* @param GCPtrOld The old virtual address.
82	* @param GCPtrNew The new virtual address.
83	* @param enmMode Used to indicate the callback mode.
84	* @param pvUser User argument.
85	* @remark The return value is no a failure indicator, it's an acceptance
86	* indicator. Relocation can not fail!
87	*/
88	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
89	/** Pointer to a relocation callback function. */
90	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
91
92
93	/**
94	* Memory access origin.
95	*/
96	typedef enum PGMACCESSORIGIN
97	{
98	/** Invalid zero value. */
99	PGMACCESSORIGIN_INVALID = 0,
100	/** IEM is access memory. */
101	PGMACCESSORIGIN_IEM,
102	/** HM is access memory. */
103	PGMACCESSORIGIN_HM,
104	/** Some device is access memory. */
105	PGMACCESSORIGIN_DEVICE,
106	/** Someone debugging is access memory. */
107	PGMACCESSORIGIN_DEBUGGER,
108	/** SELM is access memory. */
109	PGMACCESSORIGIN_SELM,
110	/** FTM is access memory. */
111	PGMACCESSORIGIN_FTM,
112	/** REM is access memory. */
113	PGMACCESSORIGIN_REM,
114	/** IOM is access memory. */
115	PGMACCESSORIGIN_IOM,
116	/** End of valid values. */
117	PGMACCESSORIGIN_END,
118	/** Type size hack. */
119	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
120	} PGMACCESSORIGIN;
121
122
123	/**
124	* Physical page access handler kind.
125	*/
126	typedef enum PGMPHYSHANDLERKIND
127	{
128	/** Invalid zero value. */
129	PGMPHYSHANDLERKIND_INVALID = 0,
130	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
131	PGMPHYSHANDLERKIND_MMIO,
132	/** Handler all write access to a physical page range. */
133	PGMPHYSHANDLERKIND_WRITE,
134	/** Handler all access to a physical page range. */
135	PGMPHYSHANDLERKIND_ALL,
136	/** End of the valid values. */
137	PGMPHYSHANDLERKIND_END,
138	/** Type size hack. */
139	PGMPHYSHANDLERKIND_32BIT_HACK = 0x7fffffff
140	} PGMPHYSHANDLERKIND;
141
142	/**
143	* Guest Access type
144	*/
145	typedef enum PGMACCESSTYPE
146	{
147	/** Read access. */
148	PGMACCESSTYPE_READ = 1,
149	/** Write access. */
150	PGMACCESSTYPE_WRITE
151	} PGMACCESSTYPE;
152
153
154	/** @def PGM_ALL_CB_DECL
155	* Macro for declaring a handler callback for all contexts. The handler
156	* callback is static in ring-3, and exported in RC and R0.
157	* @sa PGM_ALL_CB2_DECL.
158	*/
159	#if defined(IN_RC) \|\| defined(IN_RING0)
160	# ifdef __cplusplus
161	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
162	# else
163	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
164	# endif
165	#else
166	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
167	#endif
168
169	/** @def PGM_ALL_CB2_DECL
170	* Macro for declaring a handler callback for all contexts. The handler
171	* callback is hidden in ring-3, and exported in RC and R0.
172	* @sa PGM_ALL_CB2_DECL.
173	*/
174	#if defined(IN_RC) \|\| defined(IN_RING0)
175	# ifdef __cplusplus
176	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
177	# else
178	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
179	# endif
180	#else
181	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
182	#endif
183
184	/** @def PGM_ALL_CB2_PROTO
185	* Macro for declaring a handler callback for all contexts. The handler
186	* callback is hidden in ring-3, and exported in RC and R0.
187	* @param fnType The callback function type.
188	* @sa PGM_ALL_CB2_DECL.
189	*/
190	#if defined(IN_RC) \|\| defined(IN_RING0)
191	# ifdef __cplusplus
192	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
193	# else
194	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
195	# endif
196	#else
197	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
198	#endif
199
200
201	/**
202	* \#PF Handler callback for physical access handler ranges in RC and R0.
203	*
204	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
205	* @param pVM The cross context VM structure.
206	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
207	* @param uErrorCode CPU Error code.
208	* @param pCtx Pointer to the register context for the CPU.
209	* @param pvFault The fault address (cr2).
210	* @param GCPhysFault The GC physical address corresponding to pvFault.
211	* @param uUser User argument (not a pointer).
212	* @thread EMT(pVCpu)
213	*/
214	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
215	RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser));
216	/** Pointer to PGM access callback. */
217	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
218
219
220	/**
221	* Access handler callback for physical access handler ranges.
222	*
223	* The handler can not raise any faults, it's mainly for monitoring write access
224	* to certain pages (like MMIO).
225	*
226	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
227	* the only supported informational status code is
228	* VINF_PGM_HANDLER_DO_DEFAULT.
229	* @retval VINF_SUCCESS if the handler have carried out the operation.
230	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
231	* access operation.
232	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
233	*
234	* @param pVM The cross context VM structure.
235	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
236	* @param GCPhys The physical address the guest is writing to.
237	* @param pvPhys The HC mapping of that address.
238	* @param pvBuf What the guest is reading/writing.
239	* @param cbBuf How much it's reading/writing.
240	* @param enmAccessType The access type.
241	* @param enmOrigin The origin of this call.
242	* @param uUser User argument (not a pointer).
243	* @thread EMT(pVCpu)
244	*/
245	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
246	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
247	PGMACCESSORIGIN enmOrigin, uint64_t uUser));
248	/** Pointer to PGM access callback. */
249	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
250
251
252	/**
253	* Paging mode.
254	*
255	* @note Part of saved state. Change with extreme care.
256	*/
257	typedef enum PGMMODE
258	{
259	/** The usual invalid value. */
260	PGMMODE_INVALID = 0,
261	/** Real mode. */
262	PGMMODE_REAL,
263	/** Protected mode, no paging. */
264	PGMMODE_PROTECTED,
265	/** 32-bit paging. */
266	PGMMODE_32_BIT,
267	/** PAE paging. */
268	PGMMODE_PAE,
269	/** PAE paging with NX enabled. */
270	PGMMODE_PAE_NX,
271	/** 64-bit AMD paging (long mode). */
272	PGMMODE_AMD64,
273	/** 64-bit AMD paging (long mode) with NX enabled. */
274	PGMMODE_AMD64_NX,
275	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
276	PGMMODE_NESTED_32BIT,
277	/** PAE nested paging mode (shadow only; guest physical to host physical). */
278	PGMMODE_NESTED_PAE,
279	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
280	PGMMODE_NESTED_AMD64,
281	/** Extended paging (Intel) mode. */
282	PGMMODE_EPT,
283	/** Special mode used by NEM to indicate no shadow paging necessary. */
284	PGMMODE_NONE,
285	/** The max number of modes */
286	PGMMODE_MAX,
287	/** 32bit hackishness. */
288	PGMMODE_32BIT_HACK = 0x7fffffff
289	} PGMMODE;
290
291	/**
292	* Second level address translation (SLAT) mode.
293	*/
294	typedef enum PGMSLAT
295	{
296	/** The usual invalid value. */
297	PGMSLAT_INVALID = 0,
298	/** No second level translation. */
299	PGMSLAT_DIRECT,
300	/** Intel Extended Page Tables (EPT). */
301	PGMSLAT_EPT,
302	/** AMD-V Nested Paging 32-bit. */
303	PGMSLAT_32BIT,
304	/** AMD-V Nested Paging PAE. */
305	PGMSLAT_PAE,
306	/** AMD-V Nested Paging 64-bit. */
307	PGMSLAT_AMD64,
308	/** 32bit hackishness. */
309	PGMSLAT_32BIT_HACK = 0x7fffffff
310	} PGMSLAT;
311
312
313	/** @name PGMPTWALK::fFailed flags.
314	* These flags indicate the type of a page-walk failure.
315	* @{
316	*/
317	typedef uint32_t PGMWALKFAIL;
318	/** No fault. */
319	#define PGM_WALKFAIL_SUCCESS UINT32_C(0)
320
321	/** Not present (X86_TRAP_PF_P). */
322	#define PGM_WALKFAIL_NOT_PRESENT RT_BIT_32(0)
323	/** Reserved bit set in table entry (X86_TRAP_PF_RSVD). */
324	#define PGM_WALKFAIL_RESERVED_BITS RT_BIT_32(1)
325	/** Bad physical address (VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS). */
326	#define PGM_WALKFAIL_BAD_PHYSICAL_ADDRESS RT_BIT_32(2)
327
328	/** EPT violation - Intel. */
329	#define PGM_WALKFAIL_EPT_VIOLATION RT_BIT_32(3)
330	/** EPT violation, convertible to \#VE exception - Intel. */
331	#define PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE RT_BIT_32(4)
332	/** EPT misconfiguration - Intel. */
333	#define PGM_WALKFAIL_EPT_MISCONFIG RT_BIT_32(5)
334	/** Mask of all EPT induced page-walk failures - Intel. */
335	#define PGM_WALKFAIL_EPT ( PGM_WALKFAIL_EPT_VIOLATION \
336	\| PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE \
337	\| PGM_WALKFAIL_EPT_MISCONFIG)
338
339	/** Access denied: Not writable (VERR_ACCESS_DENIED). */
340	#define PGM_WALKFAIL_NOT_WRITABLE RT_BIT_32(6)
341	/** Access denied: Not executable (VERR_ACCESS_DENIED). */
342	#define PGM_WALKFAIL_NOT_EXECUTABLE RT_BIT_32(7)
343	/** Access denied: Not user/supervisor mode accessible (VERR_ACCESS_DENIED). */
344	#define PGM_WALKFAIL_NOT_ACCESSIBLE_BY_MODE RT_BIT_32(8)
345
346	/** The level the problem arrised at.
347	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
348	* level 8. This is 0 on success. */
349	#define PGM_WALKFAIL_LEVEL_MASK UINT32_C(0x0000f100)
350	/** Level shift (see PGM_WALKFAIL_LEVEL_MASK). */
351	#define PGM_WALKFAIL_LEVEL_SHIFT 11
352
353	/** @} */
354
355
356	/** @name PGM_PTATTRS_XXX - PGM page-table attributes.
357	*
358	* This is VirtualBox's combined page table attributes. It combines regular page
359	* table and Intel EPT attributes. It's 64-bit in size so there's ample room for
360	* bits added in the future to EPT or regular page tables (for e.g. Protection Key).
361	*
362	* The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
363	* attributes as these are unique to EPT and fit within 64-bits despite the shift:
364	* - EPT_R : Read access.
365	* - EPT_W : Write access.
366	* - EPT_X_SUPER : Execute or execute for supervisor-mode linear addr access.
367	* - EPT_MEMTYPE : EPT memory type.
368	* - EPT_IGNORE_PAT: Ignore PAT memory type.
369	* - EPT_X_USER : Execute access for user-mode linear addresses.
370	*
371	* For regular page tables, the R bit is always 1 (same as P bit).
372	* For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
373	*
374	* The following EPT attributes are mapped to the following positions because they
375	* exist in the regular page tables at these positions OR are exclusive to EPT and
376	* have been mapped to arbitrarily chosen positions:
377	* - EPT_A : Accessed (EPT bit 8 maps to bit 5).
378	* - EPT_D : Dirty (EPT bit 9 maps to bit 6).
379	* - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
380	* - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
381	*
382	* Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
383	* 11:9 in the regular page-table structures and to bit 11 in the EPT structures
384	* respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
385	* use by software and we may want to use/preserve them in the future.
386	*
387	* @{ */
388	typedef uint64_t PGMPTATTRS;
389	/** Pointer to a PGMPTATTRS type. */
390	typedef PGMPTATTRS *PPGMPTATTRS;
391
392	/** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
393	#define PGM_PTATTRS_R_SHIFT 0
394	#define PGM_PTATTRS_R_MASK RT_BIT_64(PGM_PTATTRS_R_SHIFT)
395	/** Write access bit (aka read/write bit for regular PT). */
396	#define PGM_PTATTRS_W_SHIFT 1
397	#define PGM_PTATTRS_W_MASK RT_BIT_64(PGM_PTATTRS_W_SHIFT)
398	/** User-mode access bit. */
399	#define PGM_PTATTRS_US_SHIFT 2
400	#define PGM_PTATTRS_US_MASK RT_BIT_64(PGM_PTATTRS_US_SHIFT)
401	/** Write through cache bit. */
402	#define PGM_PTATTRS_PWT_SHIFT 3
403	#define PGM_PTATTRS_PWT_MASK RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
404	/** Cache disabled bit. */
405	#define PGM_PTATTRS_PCD_SHIFT 4
406	#define PGM_PTATTRS_PCD_MASK RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
407	/** Accessed bit. */
408	#define PGM_PTATTRS_A_SHIFT 5
409	#define PGM_PTATTRS_A_MASK RT_BIT_64(PGM_PTATTRS_A_SHIFT)
410	/** Dirty bit. */
411	#define PGM_PTATTRS_D_SHIFT 6
412	#define PGM_PTATTRS_D_MASK RT_BIT_64(PGM_PTATTRS_D_SHIFT)
413	/** The PAT bit. */
414	#define PGM_PTATTRS_PAT_SHIFT 7
415	#define PGM_PTATTRS_PAT_MASK RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
416	/** The global bit. */
417	#define PGM_PTATTRS_G_SHIFT 8
418	#define PGM_PTATTRS_G_MASK RT_BIT_64(PGM_PTATTRS_G_SHIFT)
419	/** Reserved (bits 12:9) unused. */
420	#define PGM_PTATTRS_RSVD_12_9_SHIFT 9
421	#define PGM_PTATTRS_RSVD_12_9_MASK UINT64_C(0x0000000000001e00)
422	/** Read access bit - EPT only. */
423	#define PGM_PTATTRS_EPT_R_SHIFT 13
424	#define PGM_PTATTRS_EPT_R_MASK RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
425	/** Write access bit - EPT only. */
426	#define PGM_PTATTRS_EPT_W_SHIFT 14
427	#define PGM_PTATTRS_EPT_W_MASK RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
428	/** Execute or execute access for supervisor-mode linear addresses - EPT only. */
429	#define PGM_PTATTRS_EPT_X_SUPER_SHIFT 15
430	#define PGM_PTATTRS_EPT_X_SUPER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
431	/** EPT memory type - EPT only. */
432	#define PGM_PTATTRS_EPT_MEMTYPE_SHIFT 16
433	#define PGM_PTATTRS_EPT_MEMTYPE_MASK UINT64_C(0x0000000000070000)
434	/** Ignore PAT memory type - EPT only. */
435	#define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT 19
436	#define PGM_PTATTRS_EPT_IGNORE_PAT_MASK RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
437	/** Leaf paging entry (big or regular) - EPT only. */
438	#define PGM_PTATTRS_EPT_LEAF_SHIFT 20
439	#define PGM_PTATTRS_EPT_LEAF_MASK RT_BIT_64(PGM_PTATTRS_EPT_LEAF_SHIFT)
440	/** Accessed bit - EPT only. */
441	#define PGM_PTATTRS_EPT_A_SHIFT 21
442	#define PGM_PTATTRS_EPT_A_MASK RT_BIT_64(PGM_PTATTRS_EPT_A_SHIFT)
443	/** Dirty bit - EPT only. */
444	#define PGM_PTATTRS_EPT_D_SHIFT 22
445	#define PGM_PTATTRS_EPT_D_MASK RT_BIT_64(PGM_PTATTRS_EPT_D_SHIFT)
446	/** Execute access for user-mode linear addresses - EPT only. */
447	#define PGM_PTATTRS_EPT_X_USER_SHIFT 23
448	#define PGM_PTATTRS_EPT_X_USER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
449	/** Reserved (bits 29:24) - unused. */
450	#define PGM_PTATTRS_RSVD_29_24_SHIFT 24
451	#define PGM_PTATTRS_RSVD_29_24_MASK UINT64_C(0x000000003f000000)
452	/** Verify Guest Paging - EPT only. */
453	#define PGM_PTATTRS_EPT_VGP_SHIFT 30
454	#define PGM_PTATTRS_EPT_VGP_MASK RT_BIT_64(PGM_PTATTRS_EPT_VGP_SHIFT)
455	/** Paging-write - EPT only. */
456	#define PGM_PTATTRS_EPT_PW_SHIFT 31
457	#define PGM_PTATTRS_EPT_PW_MASK RT_BIT_64(PGM_PTATTRS_EPT_PW_SHIFT)
458	/** Reserved (bit 32) - unused. */
459	#define PGM_PTATTRS_RSVD_32_SHIFT 32
460	#define PGM_PTATTRS_RSVD_32_MASK UINT64_C(0x0000000100000000)
461	/** Supervisor shadow stack - EPT only. */
462	#define PGM_PTATTRS_EPT_SSS_SHIFT 33
463	#define PGM_PTATTRS_EPT_SSS_MASK RT_BIT_64(PGM_PTATTRS_EPT_SSS_SHIFT)
464	/** Sub-page write permission - EPT only. */
465	#define PGM_PTATTRS_EPT_SPP_SHIFT 34
466	#define PGM_PTATTRS_EPT_SPP_MASK RT_BIT_64(PGM_PTATTRS_EPT_SPP_SHIFT)
467	/** Reserved (bit 35) - unused. */
468	#define PGM_PTATTRS_RSVD_35_SHIFT 35
469	#define PGM_PTATTRS_RSVD_35_MASK UINT64_C(0x0000000800000000)
470	/** Suppress \#VE exception - EPT only. */
471	#define PGM_PTATTRS_EPT_SVE_SHIFT 36
472	#define PGM_PTATTRS_EPT_SVE_MASK RT_BIT_64(PGM_PTATTRS_EPT_SVE_SHIFT)
473	/** Reserved (bits 62:37) - unused. */
474	#define PGM_PTATTRS_RSVD_62_37_SHIFT 37
475	#define PGM_PTATTRS_RSVD_62_37_MASK UINT64_C(0x7fffffe000000000)
476	/** No-execute bit. */
477	#define PGM_PTATTRS_NX_SHIFT 63
478	#define PGM_PTATTRS_NX_MASK RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
479
480	RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
481	(R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
482	EPT_LEAF, EPT_A, EPT_D, EPT_X_USER, RSVD_29_24, EPT_VGP, EPT_PW, RSVD_32, EPT_SSS, EPT_SPP,
483	RSVD_35, EPT_SVE, RSVD_62_37, NX));
484
485	/** The bit position where the EPT specific attributes begin. */
486	#define PGM_PTATTRS_EPT_SHIFT PGM_PTATTRS_EPT_R_SHIFT
487	/** The mask of EPT bits (bits 36:ATTR_SHIFT). In the future we might choose to
488	* use higher unused bits for something else, in that case adjust this mask. */
489	#define PGM_PTATTRS_EPT_MASK UINT64_C(0x0000001fffffe000)
490
491	/** The mask of all PGM page attribute bits for regular page-tables. */
492	#define PGM_PTATTRS_PT_VALID_MASK ( PGM_PTATTRS_R_MASK \
493	\| PGM_PTATTRS_W_MASK \
494	\| PGM_PTATTRS_US_MASK \
495	\| PGM_PTATTRS_PWT_MASK \
496	\| PGM_PTATTRS_PCD_MASK \
497	\| PGM_PTATTRS_A_MASK \
498	\| PGM_PTATTRS_D_MASK \
499	\| PGM_PTATTRS_PAT_MASK \
500	\| PGM_PTATTRS_G_MASK \
501	\| PGM_PTATTRS_NX_MASK)
502
503	/** The mask of all PGM page attribute bits for EPT. */
504	#define PGM_PTATTRS_EPT_VALID_MASK ( PGM_PTATTRS_EPT_R_MASK \
505	\| PGM_PTATTRS_EPT_W_MASK \
506	\| PGM_PTATTRS_EPT_X_SUPER_MASK \
507	\| PGM_PTATTRS_EPT_MEMTYPE_MASK \
508	\| PGM_PTATTRS_EPT_IGNORE_PAT_MASK \
509	\| PGM_PTATTRS_EPT_LEAF_MASK \
510	\| PGM_PTATTRS_EPT_A_MASK \
511	\| PGM_PTATTRS_EPT_D_MASK \
512	\| PGM_PTATTRS_EPT_X_USER_MASK \
513	\| PGM_PTATTRS_EPT_VGP_MASK \
514	\| PGM_PTATTRS_EPT_PW_MASK \
515	\| PGM_PTATTRS_EPT_SSS_MASK \
516	\| PGM_PTATTRS_EPT_SPP_MASK \
517	\| PGM_PTATTRS_EPT_SVE_MASK)
518
519	/* The mask of all PGM page attribute bits (combined). */
520	#define PGM_PTATTRS_VALID_MASK (PGM_PTATTRS_PT_VALID_MASK \| PGM_PTATTRS_EPT_VALID_MASK)
521
522	/* Verify bits match the regular PT bits. */
523	AssertCompile(PGM_PTATTRS_W_SHIFT == X86_PTE_BIT_RW);
524	AssertCompile(PGM_PTATTRS_US_SHIFT == X86_PTE_BIT_US);
525	AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
526	AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
527	AssertCompile(PGM_PTATTRS_A_SHIFT == X86_PTE_BIT_A);
528	AssertCompile(PGM_PTATTRS_D_SHIFT == X86_PTE_BIT_D);
529	AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
530	AssertCompile(PGM_PTATTRS_G_SHIFT == X86_PTE_BIT_G);
531	AssertCompile(PGM_PTATTRS_W_MASK == X86_PTE_RW);
532	AssertCompile(PGM_PTATTRS_US_MASK == X86_PTE_US);
533	AssertCompile(PGM_PTATTRS_PWT_MASK == X86_PTE_PWT);
534	AssertCompile(PGM_PTATTRS_PCD_MASK == X86_PTE_PCD);
535	AssertCompile(PGM_PTATTRS_A_MASK == X86_PTE_A);
536	AssertCompile(PGM_PTATTRS_D_MASK == X86_PTE_D);
537	AssertCompile(PGM_PTATTRS_PAT_MASK == X86_PTE_PAT);
538	AssertCompile(PGM_PTATTRS_G_MASK == X86_PTE_G);
539	AssertCompile(PGM_PTATTRS_NX_MASK == X86_PTE_PAE_NX);
540
541	/* Verify those EPT bits that must map 1:1 (after shifting). */
542	AssertCompile(PGM_PTATTRS_EPT_R_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
543	AssertCompile(PGM_PTATTRS_EPT_W_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
544	AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
545	AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
546	AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
547	/** @} */
548
549
550	/**
551	* Page table walk information.
552	*
553	* This provides extensive information regarding page faults (or EPT
554	* violations/misconfigurations) while traversing page tables.
555	*/
556	typedef struct PGMPTWALK
557	{
558	/** The linear address that is being resolved (input). */
559	RTGCPTR GCPtr;
560
561	/** The second-level physical address (input/output).
562	* @remarks only valid if fIsSlat is set. */
563	RTGCPHYS GCPhysNested;
564
565	/** The physical address that is the result of the walk (output). */
566	RTGCPHYS GCPhys;
567
568	/** Set if the walk succeeded. */
569	bool fSucceeded;
570	/** Whether this is a second-level address translation. */
571	bool fIsSlat;
572	/** Whether the linear address (GCPtr) caused the second-level
573	* address translation. */
574	bool fIsLinearAddrValid;
575	/** The level problem arrised at.
576	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
577	* level 8. This is 0 on success. */
578	uint8_t uLevel;
579	/** Set if the page isn't present. */
580	bool fNotPresent;
581	/** Encountered a bad physical address. */
582	bool fBadPhysAddr;
583	/** Set if there was reserved bit violations. */
584	bool fRsvdError;
585	/** Set if it involves a big page (2/4 MB). */
586	bool fBigPage;
587	/** Set if it involves a gigantic page (1 GB). */
588	bool fGigantPage;
589	bool afPadding[3];
590	/** Page-walk failure type, PGM_WALKFAIL_XXX. */
591	PGMWALKFAIL fFailed;
592
593	/** The effective page-table attributes, PGM_PTATTRS_XXX. */
594	PGMPTATTRS fEffective;
595	} PGMPTWALK;
596	/** Pointer to page walk information. */
597	typedef PGMPTWALK *PPGMPTWALK;
598	/** Pointer to const page walk information. */
599	typedef PGMPTWALK const *PCPGMPTWALK;
600
601
602	/** @name PGM_WALKINFO_XXX - flag based PGM page table walk info.
603	* @{ */
604	/** Set if the walk succeeded. */
605	#define PGM_WALKINFO_SUCCEEDED RT_BIT_32(0)
606	/** Whether this is a second-level address translation. */
607	#define PGM_WALKINFO_IS_SLAT RT_BIT_32(1)
608
609	/** Set if it involves a big page (2/4 MB). */
610	#define PGM_WALKINFO_BIG_PAGE RT_BIT_32(7)
611	/** Set if it involves a gigantic page (1 GB). */
612	#define PGM_WALKINFO_GIGANTIC_PAGE RT_BIT_32(8)
613
614	/** Whether the linear address (GCPtr) caused the second-level
615	* address translation - read the code to figure this one.
616	* @todo for PGMPTWALKFAST::fFailed? */
617	#define PGM_WALKINFO_IS_LINEAR_ADDR_VALID RT_BIT_32(10)
618	/** @} */
619
620	/**
621	* Fast page table walk information.
622	*
623	* This is a slimmed down version of PGMPTWALK for use by IEM.
624	*/
625	typedef struct PGMPTWALKFAST
626	{
627	/** The linear address that is being resolved (input). */
628	RTGCPTR GCPtr;
629
630	/** The physical address that is the result of the walk (output).
631	* This includes the offset mask from the GCPtr input value. */
632	RTGCPHYS GCPhys;
633
634	/** The second-level physical address (input/output).
635	* @remarks only valid if fIsSlat is set. */
636	RTGCPHYS GCPhysNested;
637
638	/** Walk information PGM_WALKINFO_XXX (output). */
639	uint32_t fInfo;
640	/** Page-walk failure type, PGM_WALKFAIL_XXX (output). */
641	PGMWALKFAIL fFailed;
642
643	/** The effective page-table attributes, PGM_PTATTRS_XXX (output). */
644	PGMPTATTRS fEffective;
645	} PGMPTWALKFAST;
646	/** Pointer to fast page walk information. */
647	typedef PGMPTWALKFAST *PPGMPTWALKFAST;
648	/** Pointer to const fast page walk information. */
649	typedef PGMPTWALKFAST const *PCPGMPTWALKFAST;
650
651	#define PGMPTWALKFAST_ZERO(a_pWalkFast) do { \
652	(a_pWalkFast)->GCPtr = 0; \
653	(a_pWalkFast)->GCPhys = 0; \
654	(a_pWalkFast)->GCPhysNested = 0; \
655	(a_pWalkFast)->fInfo = 0; \
656	(a_pWalkFast)->fFailed = 0; \
657	(a_pWalkFast)->fEffective = 0; \
658	} while (0)
659
660
661	/** Macro for checking if the guest is using paging.
662	* @param enmMode PGMMODE_*.
663	* @remark ASSUMES certain order of the PGMMODE_* values.
664	*/
665	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
666
667	/** Macro for checking if it's one of the long mode modes.
668	* @param enmMode PGMMODE_*.
669	*/
670	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
671
672	/** Macro for checking if it's one of the AMD64 nested modes.
673	* @param enmMode PGMMODE_*.
674	*/
675	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
676	\|\| (enmMode) == PGMMODE_NESTED_PAE \
677	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
678
679	/** Macro for checking if it's one of the PAE modes.
680	* @param enmMode PGMMODE_*.
681	*/
682	#define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
683	\|\| (enmMode) == PGMMODE_PAE_NX)
684
685	/**
686	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
687	*
688	* @returns boolean.
689	* @param enmProt The PGMROMPROT value, must be valid.
690	*/
691	#define PGMROMPROT_IS_ROM(enmProt) \
692	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
693	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
694
695
696	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
697
698	VMMDECL(int) PGMRegisterStringFormatTypes(void);
699	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
700	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
701	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault);
702	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
703	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault);
704	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
705	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
706	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
707	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
708	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
709	* PGMShwMakePageNotPresent
710	* @{ */
711	/** The call is from an access handler for dealing with the a faulting write
712	* operation. The virtual address is within the same page. */
713	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
714	/** The page is an MMIO2. */
715	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
716	/** @}*/
717	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
718	/** @name PGMQPAGE_F_XXX - Flags for PGMGstQueryPageFast
719	* @{ */
720	/** Querying for read access, set A bits accordingly. */
721	#define PGMQPAGE_F_READ RT_BIT_32(0)
722	/** Querying for write access, set A bits and D bit accordingly.
723	* Don't set leaf entry bits if is read-only. */
724	#define PGMQPAGE_F_WRITE RT_BIT_32(1)
725	/** Querying for execute access, set A bits accordingly. */
726	#define PGMQPAGE_F_EXECUTE RT_BIT_32(2)
727	/** The query is for a user mode access, so don't set leaf A or D bits
728	* unless the effective access allows usermode access.
729	* Assume supervisor access when not set. */
730	#define PGMQPAGE_F_USER_MODE RT_BIT_32(3)
731	/** Treat CR0.WP as zero when evalutating the access.
732	* @note Same value as X86_CR0_WP. */
733	#define PGMQPAGE_F_CR0_WP0 RT_BIT_32(16)
734	/** The valid flag mask. */
735	#define PGMQPAGE_F_VALID_MASK UINT32_C(0x0001000f)
736	/** @} */
737	VMM_INT_DECL(int) PGMGstQueryPageFast(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags, PPGMPTWALKFAST pWalkFast);
738	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
739	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
740	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
741	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
742
743	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
744	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
745	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
746	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
747	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce);
748	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode, bool fForce);
749	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
750	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
751	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
752	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
753	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
754	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
755	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode);
756	#endif
757	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
758	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
759	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
760	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr);
761
762	/** PGM physical access handler type registration handle (heap offset, valid
763	* cross contexts without needing fixing up). Callbacks and handler type is
764	* associated with this and it is shared by all handler registrations. */
765	typedef uint64_t PGMPHYSHANDLERTYPE;
766	/** Pointer to a PGM physical handler type registration handle. */
767	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
768	/** NIL value for PGM physical access handler type handle. */
769	#define NIL_PGMPHYSHANDLERTYPE UINT64_MAX
770	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
771	uint64_t uUser, R3PTRTYPE(const char *) pszDesc);
772	VMMDECL(int) PGMHandlerPhysicalRegisterVmxApicAccessPage(PVMCC pVM, RTGCPHYS GCPhys, PGMPHYSHANDLERTYPE hType);
773	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
774	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
775	VMMDECL(int) PGMHandlerPhysicalChangeUserArg(PVMCC pVM, RTGCPHYS GCPhys, uint64_t uUser);
776	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
777	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
778	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
779	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
780	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
781	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
782	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
783	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
784
785	/** @name PGMPHYSHANDLER_F_XXX - flags for PGMR3HandlerPhysicalTypeRegister and PGMR0HandlerPhysicalTypeRegister
786	* @{ */
787	/** Whether to hold the PGM lock while calling the handler or not.
788	* Mainly an optimization for PGM callers. */
789	#define PGMPHYSHANDLER_F_KEEP_PGM_LOCK RT_BIT_32(0)
790	/** The uUser value is a ring-0 device instance index that needs translating
791	* into a PDMDEVINS pointer before calling the handler. This is a hack to make
792	* it possible to use access handlers in devices. */
793	#define PGMPHYSHANDLER_F_R0_DEVINS_IDX RT_BIT_32(1)
794	/** Don't apply the access handler to VT-x and AMD-V. Only works with full pages.
795	* This is a trick for the VT-x APIC access page in nested VT-x setups. */
796	#define PGMPHYSHANDLER_F_NOT_IN_HM RT_BIT_32(2)
797	/** Mask of valid bits. */
798	#define PGMPHYSHANDLER_F_VALID_MASK UINT32_C(7)
799	/** @} */
800
801
802	/**
803	* Page type.
804	*
805	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
806	* @remarks This is used in the saved state, so changes to it requires bumping
807	* the saved state version.
808	* @todo So, convert to \#defines!
809	*/
810	typedef enum PGMPAGETYPE
811	{
812	/** The usual invalid zero entry. */
813	PGMPAGETYPE_INVALID = 0,
814	/** RAM page. (RWX) */
815	PGMPAGETYPE_RAM,
816	/** MMIO2 page. (RWX) */
817	PGMPAGETYPE_MMIO2,
818	/** MMIO2 page aliased over an MMIO page. (RWX)
819	* See PGMHandlerPhysicalPageAlias(). */
820	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
821	/** Special page aliased over an MMIO page. (RWX)
822	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
823	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
824	* the shadow paging code. */
825	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
826	/** Shadowed ROM. (RWX) */
827	PGMPAGETYPE_ROM_SHADOW,
828	/** ROM page. (R-X) */
829	PGMPAGETYPE_ROM,
830	/** MMIO page. (---) */
831	PGMPAGETYPE_MMIO,
832	/** End of valid entries. */
833	PGMPAGETYPE_END
834	} PGMPAGETYPE;
835	AssertCompile(PGMPAGETYPE_END == 8);
836
837	/** @name PGM page type predicates.
838	* @{ */
839	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
840	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
841	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
842	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
843	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
844	/** @} */
845
846	/**
847	* A physical memory range.
848	*
849	* @note This layout adheres to to GIM Hyper-V specs (asserted while compiling
850	* GIM Hyper-V that uses the PGM API).
851	*/
852	typedef struct PGMPHYSRANGE
853	{
854	/** The first address in the range. */
855	RTGCPHYS GCPhysStart;
856	/** The number of pages in the range. */
857	uint64_t cPages;
858	} PGMPHYSRANGE;
859	AssertCompileSize(PGMPHYSRANGE, 16);
860
861	/**
862	* A list of physical memory ranges.
863	*
864	* @note This layout adheres to to GIM Hyper-V specs (asserted while compiling
865	* GIM Hyper-V that uses the PGM API).
866	*/
867	typedef struct PGMPHYSRANGES
868	{
869	/** The number of ranges in the list. */
870	uint64_t cRanges;
871	/** Array of physical memory ranges. */
872	RT_FLEXIBLE_ARRAY_EXTENSION
873	PGMPHYSRANGE aRanges[RT_FLEXIBLE_ARRAY];
874	} PGMPHYSRANGES;
875	/** Pointer to a list of physical memory ranges. */
876	typedef PGMPHYSRANGES *PPGMPHYSRANGES;
877	/** Pointer to a const list of physical memory ranges. */
878	typedef PGMPHYSRANGES const *PCPGMPHYSRANGES;
879
880
881	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
882
883	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
884	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
885	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
886	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
887	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
888	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
889
890	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
891	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
892	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
893	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
894	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
895	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
896
897	/** @def PGM_PHYS_RW_IS_SUCCESS
898	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
899	* PGMPhysWriteGCPtr call completed the given task.
900	*
901	* @returns true if completed, false if not.
902	* @param a_rcStrict The status code.
903	* @sa IOM_SUCCESS
904	*/
905	#ifdef IN_RING3
906	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
907	( (a_rcStrict) == VINF_SUCCESS \
908	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
909	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
910	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
911	)
912	#elif defined(IN_RING0)
913	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
914	( (a_rcStrict) == VINF_SUCCESS \
915	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
916	\|\| (a_rcStrict) == VINF_EM_OFF \
917	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
918	\|\| (a_rcStrict) == VINF_EM_RESET \
919	\|\| (a_rcStrict) == VINF_EM_HALT \
920	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
921	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
922	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
923	)
924	#elif defined(IN_RC)
925	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
926	( (a_rcStrict) == VINF_SUCCESS \
927	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
928	\|\| (a_rcStrict) == VINF_EM_OFF \
929	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
930	\|\| (a_rcStrict) == VINF_EM_RESET \
931	\|\| (a_rcStrict) == VINF_EM_HALT \
932	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
933	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
934	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
935	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
936	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
937	)
938	#endif
939	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
940	* Updates the return code with a new result.
941	*
942	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
943	*
944	* @param a_rcStrict The current return code, to be updated.
945	* @param a_rcStrict2 The new return code to merge in.
946	*/
947	#ifdef IN_RING3
948	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
949	do { \
950	Assert(rcStrict == VINF_SUCCESS); \
951	Assert(rcStrict2 == VINF_SUCCESS); \
952	} while (0)
953	#elif defined(IN_RING0)
954	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
955	do { \
956	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
957	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
958	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
959	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
960	{ /* likely */ } \
961	else if ( (a_rcStrict) == VINF_SUCCESS \
962	\|\| (a_rcStrict) > (a_rcStrict2)) \
963	(a_rcStrict) = (a_rcStrict2); \
964	} while (0)
965	#elif defined(IN_RC)
966	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
967	do { \
968	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
969	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
970	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
971	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
972	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
973	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
974	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
975	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
976	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
977	{ /* likely */ } \
978	else if ((a_rcStrict) == VINF_SUCCESS) \
979	(a_rcStrict) = (a_rcStrict2); \
980	else if ( ( (a_rcStrict) > (a_rcStrict2) \
981	&& ( (a_rcStrict2) <= VINF_EM_RESET \
982	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
983	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
984	&& (a_rcStrict) > VINF_EM_RESET) ) \
985	(a_rcStrict) = (a_rcStrict2); \
986	} while (0)
987	#endif
988
989	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
990	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
991	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
992	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
993
994	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
995	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
996	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
997	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
998	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
999
1000	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
1001	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
1002	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
1003	R3R0PTRTYPE(uint8_t ) ppb, uint64_t *pfTlb);
1004	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
1005	* @{ */
1006	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
1007	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
1008	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(8) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
1009	#define PGMIEMGCPHYS2PTR_F_UNASSIGNED RT_BIT_32(9) /*< Unassgined memory (IEMTLBE_F_PG_UNASSIGNED). /
1010	#define PGMIEMGCPHYS2PTR_F_CODE_PAGE RT_BIT_32(10) /*< Write monitored IEM code page (IEMTLBE_F_PG_CODE_PAGE). /
1011	/** @} */
1012
1013	/** Information returned by PGMPhysNemQueryPageInfo. */
1014	typedef struct PGMPHYSNEMPAGEINFO
1015	{
1016	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
1017	RTHCPHYS HCPhys;
1018	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
1019	uint32_t fNemProt : 8;
1020	/** The NEM state associated with the PAGE. */
1021	uint32_t u2NemState : 2;
1022	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
1023	uint32_t u2OldNemState : 2;
1024	/** Set if the page has handler. */
1025	uint32_t fHasHandlers : 1;
1026	/** Set if is the zero page backing it. */
1027	uint32_t fZeroPage : 1;
1028	/** Set if the page has handler. */
1029	PGMPAGETYPE enmType;
1030	} PGMPHYSNEMPAGEINFO;
1031	/** Pointer to page information for NEM. */
1032	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
1033	/**
1034	* Callback for checking that the page is in sync while under the PGM lock.
1035	*
1036	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
1037	* in-sync between PGM and the native hypervisor API in an atomic fashion.
1038	*
1039	* @returns VBox status code.
1040	* @param pVM The cross context VM structure.
1041	* @param pVCpu The cross context per virtual CPU structure. Optional,
1042	* see PGMPhysNemQueryPageInfo.
1043	* @param GCPhys The guest physical address (not A20 masked).
1044	* @param pInfo The page info structure. This function updates the
1045	* u2NemState memory and the caller will update the PGMPAGE
1046	* copy accordingly.
1047	* @param pvUser Callback user argument.
1048	*/
1049	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
1050	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
1051	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
1052
1053	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
1054	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
1055
1056	/**
1057	* Callback for use with PGMPhysNemEnumPagesByState.
1058	* @returns VBox status code.
1059	* Failure status will stop enumeration immediately and return.
1060	* @param pVM The cross context VM structure.
1061	* @param pVCpu The cross context per virtual CPU structure. Optional,
1062	* see PGMPhysNemEnumPagesByState.
1063	* @param GCPhys The guest physical address (not A20 masked).
1064	* @param pu2NemState Pointer to variable with the NEM state. This can be
1065	* update.
1066	* @param pvUser The user argument.
1067	*/
1068	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
1069	uint8_t pu2NemState, void pvUser));
1070	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
1071	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
1072	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
1073	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
1074
1075
1076	#ifdef VBOX_STRICT
1077	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
1078	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
1079	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
1080	#endif /* VBOX_STRICT */
1081
1082	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
1083
1084	/**
1085	* Query large page usage state
1086	*
1087	* @returns 0 - disabled, 1 - enabled
1088	* @param pVM The cross context VM structure.
1089	*/
1090	#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
1091
1092
1093	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
1094	* @{
1095	*/
1096	#ifdef IN_RING0
1097	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM, RTR0MEMOBJ hMemObj);
1098	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
1099	VMMR0_INT_DECL(void) PGMR0DoneInitVM(PGVM pGVM);
1100	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
1101	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
1102	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
1103	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
1104	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1105	size_t offSub, size_t cbSub, void **ppvMapping);
1106	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
1107	VMMR0_INT_DECL(int) PGMR0PhysHandlerInitReqHandler(PGVM pGVM, uint32_t cEntries);
1108
1109	VMMR0_INT_DECL(int) PGMR0HandlerPhysicalTypeSetUpContext(PGVM pGVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1110	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
1111	const char *pszDesc, PGMPHYSHANDLERTYPE hType);
1112
1113	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
1114	PCRTGCPTR64 paRegionsGCPtrs);
1115	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
1116	PCPUMCTX pCtx, RTGCPHYS pvFault);
1117	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
1118	PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr);
1119	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
1120
1121	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1122	VMMR0DECL(VBOXSTRICTRC) PGMR0NestedTrap0eHandlerNestedPaging(PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
1123	PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
1124	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk);
1125	# endif
1126	#endif /* IN_RING0 */
1127
1128	/**
1129	* Request buffer for PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_ALLOCATE_RAM_RANGE
1130	*/
1131	typedef struct PGMPHYSALLOCATERAMRANGEREQ
1132	{
1133	/** The header. */
1134	SUPVMMR0REQHDR Hdr;
1135	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1136	uint32_t cbGuestPage;
1137	/** Input: Number of guest pages in the range. */
1138	uint32_t cGuestPages;
1139	/** Input: The RAM range flags (PGM_RAM_RANGE_FLAGS_XXX). */
1140	uint32_t fFlags;
1141	/** Output: The range identifier. */
1142	uint32_t idNewRange;
1143	} PGMPHYSALLOCATERAMRANGEREQ;
1144	/** Pointer to a PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_ALLOCATE_RAM_RANGE request buffer. */
1145	typedef PGMPHYSALLOCATERAMRANGEREQ *PPGMPHYSALLOCATERAMRANGEREQ;
1146
1147	VMMR0_INT_DECL(int) PGMR0PhysAllocateRamRangeReq(PGVM pGVM, PPGMPHYSALLOCATERAMRANGEREQ pReq);
1148
1149
1150	/**
1151	* Request buffer for PGMR0PhysMmio2RegisterReq / VMMR0_DO_PGM_PHYS_MMIO2_REGISTER
1152	*/
1153	typedef struct PGMPHYSMMIO2REGISTERREQ
1154	{
1155	/** The header. */
1156	SUPVMMR0REQHDR Hdr;
1157	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1158	uint32_t cbGuestPage;
1159	/** Input: Number of guest pages in the MMIO2 range. */
1160	uint32_t cGuestPages;
1161	/** Input: The MMIO2 ID of the first chunk. */
1162	uint8_t idMmio2;
1163	/** Input: The number of MMIO2 chunks needed. */
1164	uint8_t cChunks;
1165	/** Input: The sub-device number. */
1166	uint8_t iSubDev;
1167	/** Input: The device region number. */
1168	uint8_t iRegion;
1169	/** Input: Flags (PGMPHYS_MMIO2_FLAGS_XXX). */
1170	uint32_t fFlags;
1171	/** Input: The owner device key. */
1172	PPDMDEVINSR3 pDevIns;
1173	} PGMPHYSMMIO2REGISTERREQ;
1174	/** Pointer to a PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_MMIO2_REGISTER request buffer. */
1175	typedef PGMPHYSMMIO2REGISTERREQ *PPGMPHYSMMIO2REGISTERREQ;
1176
1177	VMMR0_INT_DECL(int) PGMR0PhysMmio2RegisterReq(PGVM pGVM, PPGMPHYSMMIO2REGISTERREQ pReq);
1178
1179
1180	/*
1181	* Request buffer for PGMR0PhysMmio2DeregisterReq / VMMR0_DO_PGM_PHYS_MMIO2_DEREGISTER
1182	*/
1183	typedef struct PGMPHYSMMIO2DEREGISTERREQ
1184	{
1185	/** The header. */
1186	SUPVMMR0REQHDR Hdr;
1187	/** Input: The MMIO2 ID of the first chunk. */
1188	uint8_t idMmio2;
1189	/** Input: The number of MMIO2 chunks to free. */
1190	uint8_t cChunks;
1191	/** Input: Reserved and must be zero. */
1192	uint8_t abReserved[6];
1193	/** Input: The owner device key. */
1194	PPDMDEVINSR3 pDevIns;
1195	} PGMPHYSMMIO2DEREGISTERREQ;
1196	/** Pointer to a PGMR0PhysMmio2DeregisterReq / VMMR0_DO_PGM_PHYS_MMIO2_DEREGISTER request buffer. */
1197	typedef PGMPHYSMMIO2DEREGISTERREQ *PPGMPHYSMMIO2DEREGISTERREQ;
1198
1199	VMMR0_INT_DECL(int) PGMR0PhysMmio2DeregisterReq(PGVM pGVM, PPGMPHYSMMIO2DEREGISTERREQ pReq);
1200
1201	/*
1202	* Request buffer for PGMR0PhysRomAllocateRangeReq / VMMR0_DO_PGM_PHYS_ROM_ALLOCATE_RANGE
1203	*/
1204	typedef struct PGMPHYSROMALLOCATERANGEREQ
1205	{
1206	/** The header. */
1207	SUPVMMR0REQHDR Hdr;
1208	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1209	uint32_t cbGuestPage;
1210	/** Input: Number of guest pages in the range. */
1211	uint32_t cGuestPages;
1212	/** Input: The ROM range ID (index) to be allocated. */
1213	uint32_t idRomRange;
1214	/** Input: The ROM range flags (PGMPHYS_ROM_FLAGS_XXX). */
1215	uint32_t fFlags;
1216	} PGMPHYSROMALLOCATERANGEREQ;
1217	/* Pointer to a PGMR0PhysRomAllocateRangeReq / VMMR0_DO_PGM_PHYS_ROM_ALLOCATE_RANGE request buffer. */
1218	typedef PGMPHYSROMALLOCATERANGEREQ *PPGMPHYSROMALLOCATERANGEREQ;
1219
1220	VMMR0_INT_DECL(int) PGMR0PhysRomAllocateRangeReq(PGVM pGVM, PPGMPHYSROMALLOCATERANGEREQ pReq);
1221
1222
1223	/** @} */
1224
1225
1226
1227	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
1228	* @{
1229	*/
1230	#ifdef IN_RING3
1231	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
1232	VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM);
1233	VMMR3DECL(int) PGMR3Init(PVM pVM);
1234	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
1235	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1236	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
1237	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1238	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
1239	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
1240	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
1241	VMMR3DECL(int) PGMR3Term(PVM pVM);
1242
1243	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
1244	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
1245	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
1246	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
1247	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1248	const char *ppszDesc, bool pfIsMmio);
1249	VMMR3_INT_DECL(int) PGMR3PhysGetRamBootZeroedRanges(PVM pVM, PPGMPHYSRANGES pRanges, uint32_t cMaxRanges);
1250	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
1251	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
1252
1253	VMMR3_INT_DECL(int) PGMR3PhysMmioRegister(PVM pVM, PVMCPU pVCpu, RTGCPHYS cb, const char pszDesc, uint16_t pidRamRange);
1254	VMMR3_INT_DECL(int) PGMR3PhysMmioMap(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, uint16_t idRamRange,
1255	PGMPHYSHANDLERTYPE hType, uint64_t uUser);
1256	VMMR3_INT_DECL(int) PGMR3PhysMmioUnmap(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, uint16_t idRamRange);
1257	#endif /* IN_RING3 */
1258
1259	/** @name PGMPHYS_MMIO2_FLAGS_XXX - MMIO2 registration flags.
1260	* @see PGMR3PhysMmio2Register, PDMDevHlpMmio2Create
1261	* @{ */
1262	/** Track dirty pages.
1263	* @see PGMR3PhysMmio2QueryAndResetDirtyBitmap(), PGMR3PhysMmio2ControlDirtyPageTracking(). */
1264	#define PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES RT_BIT_32(0)
1265	/** Valid flags. */
1266	#define PGMPHYS_MMIO2_FLAGS_VALID_MASK UINT32_C(0x00000001)
1267	/** @} */
1268
1269	#ifdef IN_RING3
1270	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
1271	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
1272	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1273	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1274	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1275	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
1276	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1277	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1278	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
1279	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1280	void *pvBitmap, size_t cbBitmap);
1281	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled);
1282	#endif /* IN_RING3 */
1283
1284	/** @name PGMPHYS_ROM_FLAGS_XXX - ROM registration flags.
1285	* @see PGMR3PhysRegisterRom, PDMDevHlpROMRegister
1286	* @{ */
1287	/** Inidicates that ROM shadowing should be enabled. */
1288	#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
1289	/** Indicates that what pvBinary points to won't go away
1290	* and can be used for strictness checks. */
1291	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
1292	/** Indicates that the ROM is allowed to be missing from saved state.
1293	* @note This is a hack for EFI, see @bugref{6940} */
1294	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
1295	/** Valid flags. */
1296	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
1297	/** @} */
1298
1299	#ifdef IN_RING3
1300	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1301	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc);
1302	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
1303	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
1304
1305	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1306	PFNPGMPHYSHANDLER pfnHandlerR3, const char *pszDesc,
1307	PPGMPHYSHANDLERTYPE phType);
1308
1309	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
1310
1311	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
1312	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1313	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1314	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1315	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1316	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
1317	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
1318	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
1319	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
1320	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1321	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1322	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
1323	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
1324	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1325	void **papvPages, PPGMPAGEMAPLOCK paLocks);
1326	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1327	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
1328	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
1329
1330	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
1331
1332	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
1333	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
1334	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
1335	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1336	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1337	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1338	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1339	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
1340	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
1341	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1342	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1343	#endif /* IN_RING3 */
1344
1345	/** @name Page sharing
1346	* @{ */
1347	#ifdef IN_RING3
1348	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
1349	RTGCPTR GCBaseAddr, uint32_t cbModule,
1350	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
1351	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
1352	RTGCPTR GCBaseAddr, uint32_t cbModule);
1353	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
1354	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
1355	#endif /* IN_RING3 */
1356	/** @} */
1357
1358	/** @} */
1359
1360	RT_C_DECLS_END
1361
1362	/** @} */
1363	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
1364

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 105177

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