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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 91980

最後變更 在這個檔案從91980是 91980,由 vboxsync 提交於 3 年 前

VMM,GIMDev: Missing PDMDevHlpGIMGetMmio2Regions for ring-0 variant, bugref:10074

  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
檔案大小: 399.7 KB
 
1/** @file
2 * PDM - Pluggable Device Manager, Devices.
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.alldomusa.eu.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27#define VBOX_INCLUDED_vmm_pdmdev_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmcritsectrw.h>
34#include <VBox/vmm/pdmqueue.h>
35#include <VBox/vmm/pdmtask.h>
36#ifdef IN_RING3
37# include <VBox/vmm/pdmthread.h>
38#endif
39#include <VBox/vmm/pdmifs.h>
40#include <VBox/vmm/pdmins.h>
41#include <VBox/vmm/pdmcommon.h>
42#include <VBox/vmm/pdmpcidev.h>
43#include <VBox/vmm/iom.h>
44#include <VBox/vmm/mm.h>
45#include <VBox/vmm/tm.h>
46#include <VBox/vmm/ssm.h>
47#include <VBox/vmm/cfgm.h>
48#include <VBox/vmm/cpum.h>
49#include <VBox/vmm/dbgf.h>
50#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
51#include <VBox/vmm/gim.h>
52#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
53#include <VBox/msi.h>
54#include <iprt/stdarg.h>
55#include <iprt/list.h>
56
57
58RT_C_DECLS_BEGIN
59
60/** @defgroup grp_pdm_device The PDM Devices API
61 * @ingroup grp_pdm
62 * @{
63 */
64
65/**
66 * Construct a device instance for a VM.
67 *
68 * @returns VBox status.
69 * @param pDevIns The device instance data. If the registration structure
70 * is needed, it can be accessed thru pDevIns->pReg.
71 * @param iInstance Instance number. Use this to figure out which registers
72 * and such to use. The instance number is also found in
73 * pDevIns->iInstance, but since it's likely to be
74 * frequently used PDM passes it as parameter.
75 * @param pCfg Configuration node handle for the driver. This is
76 * expected to be in high demand in the constructor and is
77 * therefore passed as an argument. When using it at other
78 * times, it can be found in pDevIns->pCfg.
79 */
80typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
81/** Pointer to a FNPDMDEVCONSTRUCT() function. */
82typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
83
84/**
85 * Destruct a device instance.
86 *
87 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
88 * resources can be freed correctly.
89 *
90 * @returns VBox status.
91 * @param pDevIns The device instance data.
92 *
93 * @remarks The device critical section is not entered. The routine may delete
94 * the critical section, so the caller cannot exit it.
95 */
96typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
97/** Pointer to a FNPDMDEVDESTRUCT() function. */
98typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
99
100/**
101 * Device relocation callback.
102 *
103 * This is called when the instance data has been relocated in raw-mode context
104 * (RC). It is also called when the RC hypervisor selects changes. The device
105 * must fixup all necessary pointers and re-query all interfaces to other RC
106 * devices and drivers.
107 *
108 * Before the RC code is executed the first time, this function will be called
109 * with a 0 delta so RC pointer calculations can be one in one place.
110 *
111 * @param pDevIns Pointer to the device instance.
112 * @param offDelta The relocation delta relative to the old location.
113 *
114 * @remarks A relocation CANNOT fail.
115 *
116 * @remarks The device critical section is not entered. The relocations should
117 * not normally require any locking.
118 */
119typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
120/** Pointer to a FNPDMDEVRELOCATE() function. */
121typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
122
123/**
124 * Power On notification.
125 *
126 * @returns VBox status.
127 * @param pDevIns The device instance data.
128 *
129 * @remarks Caller enters the device critical section.
130 */
131typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
132/** Pointer to a FNPDMDEVPOWERON() function. */
133typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
134
135/**
136 * Reset notification.
137 *
138 * @returns VBox status.
139 * @param pDevIns The device instance data.
140 *
141 * @remarks Caller enters the device critical section.
142 */
143typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
144/** Pointer to a FNPDMDEVRESET() function. */
145typedef FNPDMDEVRESET *PFNPDMDEVRESET;
146
147/**
148 * Soft reset notification.
149 *
150 * This is mainly for emulating the 286 style protected mode exits, in which
151 * most devices should remain in their current state.
152 *
153 * @returns VBox status.
154 * @param pDevIns The device instance data.
155 * @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
156 *
157 * @remarks Caller enters the device critical section.
158 */
159typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
160/** Pointer to a FNPDMDEVSOFTRESET() function. */
161typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
162
163/** @name PDMVMRESET_F_XXX - VM reset flags.
164 * These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
165 * reset via PDMDevHlpVMReset.
166 * @{ */
167/** Unknown reason. */
168#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
169/** GIM triggered reset. */
170#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
171/** The last source always causing hard resets. */
172#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
173/** ACPI triggered reset. */
174#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
175/** PS/2 system port A (92h) reset. */
176#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
177/** Keyboard reset. */
178#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
179/** Tripple fault. */
180#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
181/** Reset source mask. */
182#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
183/** @} */
184
185/**
186 * Suspend notification.
187 *
188 * @returns VBox status.
189 * @param pDevIns The device instance data.
190 * @thread EMT(0)
191 *
192 * @remarks Caller enters the device critical section.
193 */
194typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
195/** Pointer to a FNPDMDEVSUSPEND() function. */
196typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
197
198/**
199 * Resume notification.
200 *
201 * @returns VBox status.
202 * @param pDevIns The device instance data.
203 *
204 * @remarks Caller enters the device critical section.
205 */
206typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
207/** Pointer to a FNPDMDEVRESUME() function. */
208typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
209
210/**
211 * Power Off notification.
212 *
213 * This is always called when VMR3PowerOff is called.
214 * There will be no callback when hot plugging devices.
215 *
216 * @param pDevIns The device instance data.
217 * @thread EMT(0)
218 *
219 * @remarks Caller enters the device critical section.
220 */
221typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
222/** Pointer to a FNPDMDEVPOWEROFF() function. */
223typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
224
225/**
226 * Attach command.
227 *
228 * This is called to let the device attach to a driver for a specified LUN
229 * at runtime. This is not called during VM construction, the device
230 * constructor has to attach to all the available drivers.
231 *
232 * This is like plugging in the keyboard or mouse after turning on the PC.
233 *
234 * @returns VBox status code.
235 * @param pDevIns The device instance.
236 * @param iLUN The logical unit which is being attached.
237 * @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
238 *
239 * @remarks Caller enters the device critical section.
240 */
241typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
242/** Pointer to a FNPDMDEVATTACH() function. */
243typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
244
245/**
246 * Detach notification.
247 *
248 * This is called when a driver is detaching itself from a LUN of the device.
249 * The device should adjust its state to reflect this.
250 *
251 * This is like unplugging the network cable to use it for the laptop or
252 * something while the PC is still running.
253 *
254 * @param pDevIns The device instance.
255 * @param iLUN The logical unit which is being detached.
256 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
257 *
258 * @remarks Caller enters the device critical section.
259 */
260typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
261/** Pointer to a FNPDMDEVDETACH() function. */
262typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
263
264/**
265 * Query the base interface of a logical unit.
266 *
267 * @returns VBOX status code.
268 * @param pDevIns The device instance.
269 * @param iLUN The logicial unit to query.
270 * @param ppBase Where to store the pointer to the base interface of the LUN.
271 *
272 * @remarks The device critical section is not entered.
273 */
274typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
275/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
276typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
277
278/**
279 * Init complete notification (after ring-0 & RC init since 5.1).
280 *
281 * This can be done to do communication with other devices and other
282 * initialization which requires everything to be in place.
283 *
284 * @returns VBOX status code.
285 * @param pDevIns The device instance.
286 *
287 * @remarks Caller enters the device critical section.
288 */
289typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
290/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
291typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
292
293
294/**
295 * The context of a pfnMemSetup call.
296 */
297typedef enum PDMDEVMEMSETUPCTX
298{
299 /** Invalid zero value. */
300 PDMDEVMEMSETUPCTX_INVALID = 0,
301 /** After construction. */
302 PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
303 /** After reset. */
304 PDMDEVMEMSETUPCTX_AFTER_RESET,
305 /** Type size hack. */
306 PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
307} PDMDEVMEMSETUPCTX;
308
309
310/**
311 * PDM Device Registration Structure.
312 *
313 * This structure is used when registering a device from VBoxInitDevices() in HC
314 * Ring-3. PDM will continue use till the VM is terminated.
315 *
316 * @note The first part is the same in every context.
317 */
318typedef struct PDMDEVREGR3
319{
320 /** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
321 uint32_t u32Version;
322 /** Reserved, must be zero. */
323 uint32_t uReserved0;
324 /** Device name, must match the ring-3 one. */
325 char szName[32];
326 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
327 uint32_t fFlags;
328 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
329 uint32_t fClass;
330 /** Maximum number of instances (per VM). */
331 uint32_t cMaxInstances;
332 /** The shared data structure version number. */
333 uint32_t uSharedVersion;
334 /** Size of the instance data. */
335 uint32_t cbInstanceShared;
336 /** Size of the ring-0 instance data. */
337 uint32_t cbInstanceCC;
338 /** Size of the raw-mode instance data. */
339 uint32_t cbInstanceRC;
340 /** Max number of PCI devices. */
341 uint16_t cMaxPciDevices;
342 /** Max number of MSI-X vectors in any of the PCI devices. */
343 uint16_t cMaxMsixVectors;
344 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
345 * remain unchanged from registration till VM destruction. */
346 const char *pszDescription;
347
348 /** Name of the raw-mode context module (no path).
349 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
350 const char *pszRCMod;
351 /** Name of the ring-0 module (no path).
352 * Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
353 const char *pszR0Mod;
354
355 /** Construct instance - required. */
356 PFNPDMDEVCONSTRUCT pfnConstruct;
357 /** Destruct instance - optional.
358 * Critical section NOT entered (will be destroyed). */
359 PFNPDMDEVDESTRUCT pfnDestruct;
360 /** Relocation command - optional.
361 * Critical section NOT entered. */
362 PFNPDMDEVRELOCATE pfnRelocate;
363 /**
364 * Memory setup callback.
365 *
366 * @param pDevIns The device instance data.
367 * @param enmCtx Indicates the context of the call.
368 * @remarks The critical section is entered prior to calling this method.
369 */
370 DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
371 /** Power on notification - optional.
372 * Critical section is entered. */
373 PFNPDMDEVPOWERON pfnPowerOn;
374 /** Reset notification - optional.
375 * Critical section is entered. */
376 PFNPDMDEVRESET pfnReset;
377 /** Suspend notification - optional.
378 * Critical section is entered. */
379 PFNPDMDEVSUSPEND pfnSuspend;
380 /** Resume notification - optional.
381 * Critical section is entered. */
382 PFNPDMDEVRESUME pfnResume;
383 /** Attach command - optional.
384 * Critical section is entered. */
385 PFNPDMDEVATTACH pfnAttach;
386 /** Detach notification - optional.
387 * Critical section is entered. */
388 PFNPDMDEVDETACH pfnDetach;
389 /** Query a LUN base interface - optional.
390 * Critical section is NOT entered. */
391 PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
392 /** Init complete notification - optional.
393 * Critical section is entered. */
394 PFNPDMDEVINITCOMPLETE pfnInitComplete;
395 /** Power off notification - optional.
396 * Critical section is entered. */
397 PFNPDMDEVPOWEROFF pfnPowerOff;
398 /** Software system reset notification - optional.
399 * Critical section is entered. */
400 PFNPDMDEVSOFTRESET pfnSoftReset;
401
402 /** @name Reserved for future extensions, must be zero.
403 * @{ */
404 DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
405 DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
406 DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
407 DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
408 DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
409 DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
410 DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
411 DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
412 /** @} */
413
414 /** Initialization safty marker. */
415 uint32_t u32VersionEnd;
416} PDMDEVREGR3;
417/** Pointer to a PDM Device Structure. */
418typedef PDMDEVREGR3 *PPDMDEVREGR3;
419/** Const pointer to a PDM Device Structure. */
420typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
421/** Current DEVREGR3 version number. */
422#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
423
424
425/** PDM Device Flags.
426 * @{ */
427/** This flag is used to indicate that the device has a R0 component. */
428#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
429/** Requires the ring-0 component, ignore configuration values. */
430#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
431/** Requires the ring-0 component, ignore configuration values. */
432#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
433
434/** This flag is used to indicate that the device has a RC component. */
435#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
436/** Requires the raw-mode component, ignore configuration values. */
437#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
438/** Requires the raw-mode component, ignore configuration values. */
439#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
440
441/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
442#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_RC)
443
444/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
445 * The bit count for the current host.
446 * @note Superfluous, but still around for hysterical raisins. */
447#if HC_ARCH_BITS == 32
448# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
449#elif HC_ARCH_BITS == 64
450# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
451#else
452# error Unsupported HC_ARCH_BITS value.
453#endif
454/** The host bit count mask. */
455#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
456
457/** The device support only 32-bit guests. */
458#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
459/** The device support only 64-bit guests. */
460#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
461/** The device support both 32-bit & 64-bit guests. */
462#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
463/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
464 * The guest bit count for the current compilation. */
465#if GC_ARCH_BITS == 32
466# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
467#elif GC_ARCH_BITS == 64
468# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
469#else
470# error Unsupported GC_ARCH_BITS value.
471#endif
472/** The guest bit count mask. */
473#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
474
475/** A convenience. */
476#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
477
478/** Indicates that the device needs to be notified before the drivers when suspending. */
479#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
480/** Indicates that the device needs to be notified before the drivers when powering off. */
481#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
482/** Indicates that the device needs to be notified before the drivers when resetting. */
483#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
484
485/** This flag is used to indicate that the device has been converted to the
486 * new device style. */
487#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
488
489/** @} */
490
491
492/** PDM Device Classes.
493 * The order is important, lower bit earlier instantiation.
494 * @{ */
495/** Architecture device. */
496#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
497/** Architecture BIOS device. */
498#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
499/** PCI bus brigde. */
500#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
501/** PCI built-in device (e.g. PCI root complex devices). */
502#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
503/** Input device (mouse, keyboard, joystick, HID, ...). */
504#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
505/** Interrupt controller (PIC). */
506#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
507/** Interval controoler (PIT). */
508#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
509/** RTC/CMOS. */
510#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
511/** DMA controller. */
512#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
513/** VMM Device. */
514#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
515/** Graphics device, like VGA. */
516#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
517/** Storage controller device. */
518#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
519/** Network interface controller. */
520#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
521/** Audio. */
522#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
523/** USB HIC. */
524#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
525/** ACPI. */
526#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
527/** Serial controller device. */
528#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
529/** Parallel controller device */
530#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
531/** Host PCI pass-through device */
532#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
533/** Misc devices (always last). */
534#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
535/** @} */
536
537
538/**
539 * PDM Device Registration Structure, ring-0.
540 *
541 * This structure is used when registering a device from VBoxInitDevices() in HC
542 * Ring-0. PDM will continue use till the VM is terminated.
543 */
544typedef struct PDMDEVREGR0
545{
546 /** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
547 uint32_t u32Version;
548 /** Reserved, must be zero. */
549 uint32_t uReserved0;
550 /** Device name, must match the ring-3 one. */
551 char szName[32];
552 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
553 uint32_t fFlags;
554 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
555 uint32_t fClass;
556 /** Maximum number of instances (per VM). */
557 uint32_t cMaxInstances;
558 /** The shared data structure version number. */
559 uint32_t uSharedVersion;
560 /** Size of the instance data. */
561 uint32_t cbInstanceShared;
562 /** Size of the ring-0 instance data. */
563 uint32_t cbInstanceCC;
564 /** Size of the raw-mode instance data. */
565 uint32_t cbInstanceRC;
566 /** Max number of PCI devices. */
567 uint16_t cMaxPciDevices;
568 /** Max number of MSI-X vectors in any of the PCI devices. */
569 uint16_t cMaxMsixVectors;
570 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
571 * remain unchanged from registration till VM destruction. */
572 const char *pszDescription;
573
574 /**
575 * Early construction callback (optional).
576 *
577 * This is called right after the device instance structure has been allocated
578 * and before the ring-3 constructor gets called.
579 *
580 * @returns VBox status code.
581 * @param pDevIns The device instance data.
582 * @note The destructure is always called, regardless of the return status.
583 */
584 DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
585
586 /**
587 * Regular construction callback (optional).
588 *
589 * This is called after (or during) the ring-3 constructor.
590 *
591 * @returns VBox status code.
592 * @param pDevIns The device instance data.
593 * @note The destructure is always called, regardless of the return status.
594 */
595 DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
596
597 /**
598 * Destructor (optional).
599 *
600 * This is called after the ring-3 destruction. This is not called if ring-3
601 * fails to trigger it (e.g. process is killed or crashes).
602 *
603 * @param pDevIns The device instance data.
604 */
605 DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
606
607 /**
608 * Final destructor (optional).
609 *
610 * This is called right before the memory is freed, which happens when the
611 * VM/GVM object is destroyed. This is always called.
612 *
613 * @param pDevIns The device instance data.
614 */
615 DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
616
617 /**
618 * Generic request handler (optional).
619 *
620 * @param pDevIns The device instance data.
621 * @param uReq Device specific request.
622 * @param uArg Request argument.
623 */
624 DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
625
626 /** @name Reserved for future extensions, must be zero.
627 * @{ */
628 DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
629 DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
630 DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
631 DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
632 DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
633 DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
634 DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
635 DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
636 /** @} */
637
638 /** Initialization safty marker. */
639 uint32_t u32VersionEnd;
640} PDMDEVREGR0;
641/** Pointer to a ring-0 PDM device registration structure. */
642typedef PDMDEVREGR0 *PPDMDEVREGR0;
643/** Pointer to a const ring-0 PDM device registration structure. */
644typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
645/** Current DEVREGR0 version number. */
646#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
647
648
649/**
650 * PDM Device Registration Structure, raw-mode
651 *
652 * At the moment, this structure is mostly here to match the other two contexts.
653 */
654typedef struct PDMDEVREGRC
655{
656 /** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
657 uint32_t u32Version;
658 /** Reserved, must be zero. */
659 uint32_t uReserved0;
660 /** Device name, must match the ring-3 one. */
661 char szName[32];
662 /** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
663 uint32_t fFlags;
664 /** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
665 uint32_t fClass;
666 /** Maximum number of instances (per VM). */
667 uint32_t cMaxInstances;
668 /** The shared data structure version number. */
669 uint32_t uSharedVersion;
670 /** Size of the instance data. */
671 uint32_t cbInstanceShared;
672 /** Size of the ring-0 instance data. */
673 uint32_t cbInstanceCC;
674 /** Size of the raw-mode instance data. */
675 uint32_t cbInstanceRC;
676 /** Max number of PCI devices. */
677 uint16_t cMaxPciDevices;
678 /** Max number of MSI-X vectors in any of the PCI devices. */
679 uint16_t cMaxMsixVectors;
680 /** The description of the device. The UTF-8 string pointed to shall, like this structure,
681 * remain unchanged from registration till VM destruction. */
682 const char *pszDescription;
683
684 /**
685 * Constructor callback.
686 *
687 * This is called much later than both the ring-0 and ring-3 constructors, since
688 * raw-mode v2 require a working VMM to run actual code.
689 *
690 * @returns VBox status code.
691 * @param pDevIns The device instance data.
692 * @note The destructure is always called, regardless of the return status.
693 */
694 DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
695
696 /** @name Reserved for future extensions, must be zero.
697 * @{ */
698 DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
699 DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
700 DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
701 DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
702 DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
703 DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
704 DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
705 DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
706 /** @} */
707
708 /** Initialization safty marker. */
709 uint32_t u32VersionEnd;
710} PDMDEVREGRC;
711/** Pointer to a raw-mode PDM device registration structure. */
712typedef PDMDEVREGRC *PPDMDEVREGRC;
713/** Pointer to a const raw-mode PDM device registration structure. */
714typedef PDMDEVREGRC const *PCPDMDEVREGRC;
715/** Current DEVREGRC version number. */
716#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
717
718
719
720/** @def PDM_DEVREG_VERSION
721 * Current DEVREG version number. */
722/** @typedef PDMDEVREGR3
723 * A current context PDM device registration structure. */
724/** @typedef PPDMDEVREGR3
725 * Pointer to a current context PDM device registration structure. */
726/** @typedef PCPDMDEVREGR3
727 * Pointer to a const current context PDM device registration structure. */
728#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
729# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
730typedef PDMDEVREGR3 PDMDEVREG;
731typedef PPDMDEVREGR3 PPDMDEVREG;
732typedef PCPDMDEVREGR3 PCPDMDEVREG;
733#elif defined(IN_RING0)
734# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
735typedef PDMDEVREGR0 PDMDEVREG;
736typedef PPDMDEVREGR0 PPDMDEVREG;
737typedef PCPDMDEVREGR0 PCPDMDEVREG;
738#elif defined(IN_RC)
739# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
740typedef PDMDEVREGRC PDMDEVREG;
741typedef PPDMDEVREGRC PPDMDEVREG;
742typedef PCPDMDEVREGRC PCPDMDEVREG;
743#else
744# error "Not IN_RING3, IN_RING0 or IN_RC"
745#endif
746
747
748/**
749 * Device registrations for ring-0 modules.
750 *
751 * This structure is used directly and must therefore reside in persistent
752 * memory (i.e. the data section).
753 */
754typedef struct PDMDEVMODREGR0
755{
756 /** The structure version (PDM_DEVMODREGR0_VERSION). */
757 uint32_t u32Version;
758 /** Number of devices in the array papDevRegs points to. */
759 uint32_t cDevRegs;
760 /** Pointer to device registration structures. */
761 PCPDMDEVREGR0 *papDevRegs;
762 /** The ring-0 module handle - PDM internal, fingers off. */
763 void *hMod;
764 /** List entry - PDM internal, fingers off. */
765 RTLISTNODE ListEntry;
766} PDMDEVMODREGR0;
767/** Pointer to device registriations for a ring-0 module. */
768typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
769/** Current PDMDEVMODREGR0 version number. */
770#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
771
772
773/** @name IRQ Level for use with the *SetIrq APIs.
774 * @{
775 */
776/** Assert the IRQ (can assume value 1). */
777#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
778/** Deassert the IRQ (can assume value 0). */
779#define PDM_IRQ_LEVEL_LOW 0
780/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
781 * automatically deasserts it after delivery to the APIC (IOAPIC).
782 * @note Only suitable for edge trigger interrupts. */
783#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) | PDM_IRQ_LEVEL_HIGH)
784/** @} */
785
786/**
787 * Registration record for MSI/MSI-X emulation.
788 */
789typedef struct PDMMSIREG
790{
791 /** Number of MSI interrupt vectors, 0 if MSI not supported */
792 uint16_t cMsiVectors;
793 /** Offset of MSI capability */
794 uint8_t iMsiCapOffset;
795 /** Offset of next capability to MSI */
796 uint8_t iMsiNextOffset;
797 /** If we support 64-bit MSI addressing */
798 bool fMsi64bit;
799 /** If we do not support per-vector masking */
800 bool fMsiNoMasking;
801
802 /** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
803 uint16_t cMsixVectors;
804 /** Offset of MSI-X capability */
805 uint8_t iMsixCapOffset;
806 /** Offset of next capability to MSI-X */
807 uint8_t iMsixNextOffset;
808 /** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
809 uint8_t iMsixBar;
810} PDMMSIREG;
811typedef PDMMSIREG *PPDMMSIREG;
812
813/**
814 * PCI Bus registration structure.
815 * All the callbacks, except the PCIBIOS hack, are working on PCI devices.
816 */
817typedef struct PDMPCIBUSREGR3
818{
819 /** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
820 uint32_t u32Version;
821
822 /**
823 * Registers the device with the default PCI bus.
824 *
825 * @returns VBox status code.
826 * @param pDevIns Device instance of the PCI Bus.
827 * @param pPciDev The PCI device structure.
828 * @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
829 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
830 * device number (0-31).
831 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
832 * function number (0-7).
833 * @param pszName Device name (static but not unique).
834 *
835 * @remarks Caller enters the PDM critical section.
836 */
837 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
838 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
839
840 /**
841 * Initialize MSI or MSI-X emulation support in a PCI device.
842 *
843 * This cannot handle all corner cases of the MSI/MSI-X spec, but for the
844 * vast majority of device emulation it covers everything necessary. It's
845 * fully automatic, taking care of all BAR and config space requirements,
846 * and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
847 * When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
848 * the vector number (otherwise it has the usual INTA-D meaning for PCI).
849 *
850 * A device not using this can still offer MSI/MSI-X. In this case it's
851 * completely up to the device (in the MSI-X case) to create/register the
852 * necessary MMIO BAR, handle all config space/BAR updating and take care
853 * of delivering the interrupts appropriately.
854 *
855 * @returns VBox status code.
856 * @param pDevIns Device instance of the PCI Bus.
857 * @param pPciDev The PCI device structure.
858 * @param pMsiReg MSI emulation registration structure
859 * @remarks Caller enters the PDM critical section.
860 */
861 DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
862
863 /**
864 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
865 *
866 * @returns VBox status code.
867 * @param pDevIns Device instance of the PCI Bus.
868 * @param pPciDev The PCI device structure.
869 * @param iRegion The region number.
870 * @param cbRegion Size of the region.
871 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
872 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
873 * PCI_ADDRESS_SPACE_BAR64 or'ed in.
874 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
875 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
876 * @a fFlags, UINT64_MAX if no handle is passed
877 * (old style).
878 * @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
879 * is given.
880 * @remarks Caller enters the PDM critical section.
881 */
882 DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
883 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
884 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
885
886 /**
887 * Register PCI configuration space read/write intercept callbacks.
888 *
889 * @param pDevIns Device instance of the PCI Bus.
890 * @param pPciDev The PCI device structure.
891 * @param pfnRead Pointer to the user defined PCI config read function.
892 * @param pfnWrite Pointer to the user defined PCI config write function.
893 * to call default PCI config write function. Can be NULL.
894 * @remarks Caller enters the PDM critical section.
895 * @thread EMT
896 */
897 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
898 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
899
900 /**
901 * Perform a PCI configuration space write, bypassing interception.
902 *
903 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
904 *
905 * @returns Strict VBox status code (mainly DBGFSTOP).
906 * @param pDevIns Device instance of the PCI Bus.
907 * @param pPciDev The PCI device which config space is being read.
908 * @param uAddress The config space address.
909 * @param cb The size of the read: 1, 2 or 4 bytes.
910 * @param u32Value The value to write.
911 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
912 * that the (root) bus will have done that already.
913 */
914 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
915 uint32_t uAddress, unsigned cb, uint32_t u32Value));
916
917 /**
918 * Perform a PCI configuration space read, bypassing interception.
919 *
920 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
921 *
922 * @returns Strict VBox status code (mainly DBGFSTOP).
923 * @param pDevIns Device instance of the PCI Bus.
924 * @param pPciDev The PCI device which config space is being read.
925 * @param uAddress The config space address.
926 * @param cb The size of the read: 1, 2 or 4 bytes.
927 * @param pu32Value Where to return the value.
928 * @note The caller (PDM) does not enter the PDM critsect, but it is possible
929 * that the (root) bus will have done that already.
930 */
931 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
932 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
933
934 /**
935 * Set the IRQ for a PCI device.
936 *
937 * @param pDevIns Device instance of the PCI Bus.
938 * @param pPciDev The PCI device structure.
939 * @param iIrq IRQ number to set.
940 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
941 * @param uTagSrc The IRQ tag and source (for tracing).
942 * @remarks Caller enters the PDM critical section.
943 */
944 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
945
946 /** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
947 uint32_t u32EndVersion;
948} PDMPCIBUSREGR3;
949/** Pointer to a PCI bus registration structure. */
950typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
951/** Current PDMPCIBUSREGR3 version number. */
952#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
953
954/**
955 * PCI Bus registration structure for ring-0.
956 */
957typedef struct PDMPCIBUSREGR0
958{
959 /** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
960 uint32_t u32Version;
961 /** The PCI bus number (from ring-3 registration). */
962 uint32_t iBus;
963 /**
964 * Set the IRQ for a PCI device.
965 *
966 * @param pDevIns Device instance of the PCI Bus.
967 * @param pPciDev The PCI device structure.
968 * @param iIrq IRQ number to set.
969 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
970 * @param uTagSrc The IRQ tag and source (for tracing).
971 * @remarks Caller enters the PDM critical section.
972 */
973 DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
974 /** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
975 uint32_t u32EndVersion;
976} PDMPCIBUSREGR0;
977/** Pointer to a PCI bus ring-0 registration structure. */
978typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
979/** Current PDMPCIBUSREGR0 version number. */
980#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
981
982/**
983 * PCI Bus registration structure for raw-mode.
984 */
985typedef struct PDMPCIBUSREGRC
986{
987 /** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
988 uint32_t u32Version;
989 /** The PCI bus number (from ring-3 registration). */
990 uint32_t iBus;
991 /**
992 * Set the IRQ for a PCI device.
993 *
994 * @param pDevIns Device instance of the PCI Bus.
995 * @param pPciDev The PCI device structure.
996 * @param iIrq IRQ number to set.
997 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
998 * @param uTagSrc The IRQ tag and source (for tracing).
999 * @remarks Caller enters the PDM critical section.
1000 */
1001 DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1002 /** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1003 uint32_t u32EndVersion;
1004} PDMPCIBUSREGRC;
1005/** Pointer to a PCI bus raw-mode registration structure. */
1006typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1007/** Current PDMPCIBUSREGRC version number. */
1008#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1009
1010/** PCI bus registration structure for the current context. */
1011typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1012/** Pointer to a PCI bus registration structure for the current context. */
1013typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1014/** PCI bus registration structure version for the current context. */
1015#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1016
1017
1018/**
1019 * PCI Bus RC helpers.
1020 */
1021typedef struct PDMPCIHLPRC
1022{
1023 /** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1024 uint32_t u32Version;
1025
1026 /**
1027 * Set an ISA IRQ.
1028 *
1029 * @param pDevIns PCI device instance.
1030 * @param iIrq IRQ number to set.
1031 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1032 * @param uTagSrc The IRQ tag and source (for tracing).
1033 * @thread EMT only.
1034 */
1035 DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1036
1037 /**
1038 * Set an I/O-APIC IRQ.
1039 *
1040 * @param pDevIns PCI device instance.
1041 * @param uBusDevFn The bus:device:function of the device initiating the
1042 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1043 * interrupt.
1044 * @param iIrq IRQ number to set.
1045 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1046 * @param uTagSrc The IRQ tag and source (for tracing).
1047 * @thread EMT only.
1048 */
1049 DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1050
1051 /**
1052 * Send an MSI.
1053 *
1054 * @param pDevIns PCI device instance.
1055 * @param uBusDevFn The bus:device:function of the device initiating the
1056 * MSI. Cannot be NIL_PCIBDF.
1057 * @param pMsi The MSI to send.
1058 * @param uTagSrc The IRQ tag and source (for tracing).
1059 * @thread EMT only.
1060 */
1061 DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1062
1063
1064 /**
1065 * Acquires the PDM lock.
1066 *
1067 * @returns VINF_SUCCESS on success.
1068 * @returns rc if we failed to acquire the lock.
1069 * @param pDevIns The PCI device instance.
1070 * @param rc What to return if we fail to acquire the lock.
1071 *
1072 * @sa PDMCritSectEnter
1073 */
1074 DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1075
1076 /**
1077 * Releases the PDM lock.
1078 *
1079 * @param pDevIns The PCI device instance.
1080 */
1081 DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1082
1083 /**
1084 * Gets a bus by it's PDM ordinal (typically the parent bus).
1085 *
1086 * @returns Pointer to the device instance of the bus.
1087 * @param pDevIns The PCI bus device instance.
1088 * @param idxPdmBus The PDM ordinal value of the bus to get.
1089 */
1090 DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1091
1092 /** Just a safety precaution. */
1093 uint32_t u32TheEnd;
1094} PDMPCIHLPRC;
1095/** Pointer to PCI helpers. */
1096typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1097/** Pointer to const PCI helpers. */
1098typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1099
1100/** Current PDMPCIHLPRC version number. */
1101#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1102
1103
1104/**
1105 * PCI Bus R0 helpers.
1106 */
1107typedef struct PDMPCIHLPR0
1108{
1109 /** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1110 uint32_t u32Version;
1111
1112 /**
1113 * Set an ISA IRQ.
1114 *
1115 * @param pDevIns PCI device instance.
1116 * @param iIrq IRQ number to set.
1117 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1118 * @param uTagSrc The IRQ tag and source (for tracing).
1119 * @thread EMT only.
1120 */
1121 DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1122
1123 /**
1124 * Set an I/O-APIC IRQ.
1125 *
1126 * @param pDevIns PCI device instance.
1127 * @param uBusDevFn The bus:device:function of the device initiating the
1128 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1129 * interrupt.
1130 * @param iIrq IRQ number to set.
1131 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1132 * @param uTagSrc The IRQ tag and source (for tracing).
1133 * @thread EMT only.
1134 */
1135 DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1136
1137 /**
1138 * Send an MSI.
1139 *
1140 * @param pDevIns PCI device instance.
1141 * @param uBusDevFn The bus:device:function of the device initiating the
1142 * MSI. Cannot be NIL_PCIBDF.
1143 * @param pMsi The MSI to send.
1144 * @param uTagSrc The IRQ tag and source (for tracing).
1145 * @thread EMT only.
1146 */
1147 DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1148
1149 /**
1150 * Acquires the PDM lock.
1151 *
1152 * @returns VINF_SUCCESS on success.
1153 * @returns rc if we failed to acquire the lock.
1154 * @param pDevIns The PCI device instance.
1155 * @param rc What to return if we fail to acquire the lock.
1156 *
1157 * @sa PDMCritSectEnter
1158 */
1159 DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1160
1161 /**
1162 * Releases the PDM lock.
1163 *
1164 * @param pDevIns The PCI device instance.
1165 */
1166 DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1167
1168 /**
1169 * Gets a bus by it's PDM ordinal (typically the parent bus).
1170 *
1171 * @returns Pointer to the device instance of the bus.
1172 * @param pDevIns The PCI bus device instance.
1173 * @param idxPdmBus The PDM ordinal value of the bus to get.
1174 */
1175 DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1176
1177 /** Just a safety precaution. */
1178 uint32_t u32TheEnd;
1179} PDMPCIHLPR0;
1180/** Pointer to PCI helpers. */
1181typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1182/** Pointer to const PCI helpers. */
1183typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1184
1185/** Current PDMPCIHLPR0 version number. */
1186#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1187
1188/**
1189 * PCI device helpers.
1190 */
1191typedef struct PDMPCIHLPR3
1192{
1193 /** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1194 uint32_t u32Version;
1195
1196 /**
1197 * Set an ISA IRQ.
1198 *
1199 * @param pDevIns The PCI device instance.
1200 * @param iIrq IRQ number to set.
1201 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1202 * @param uTagSrc The IRQ tag and source (for tracing).
1203 */
1204 DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1205
1206 /**
1207 * Set an I/O-APIC IRQ.
1208 *
1209 * @param pDevIns The PCI device instance.
1210 * @param uBusDevFn The bus:device:function of the device initiating the
1211 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1212 * interrupt.
1213 * @param iIrq IRQ number to set.
1214 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1215 * @param uTagSrc The IRQ tag and source (for tracing).
1216 */
1217 DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1218
1219 /**
1220 * Send an MSI.
1221 *
1222 * @param pDevIns PCI device instance.
1223 * @param uBusDevFn The bus:device:function of the device initiating the
1224 * MSI. Cannot be NIL_PCIBDF.
1225 * @param pMsi The MSI to send.
1226 * @param uTagSrc The IRQ tag and source (for tracing).
1227 */
1228 DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1229
1230 /**
1231 * Acquires the PDM lock.
1232 *
1233 * @returns VINF_SUCCESS on success.
1234 * @returns Fatal error on failure.
1235 * @param pDevIns The PCI device instance.
1236 * @param rc Dummy for making the interface identical to the RC and R0 versions.
1237 *
1238 * @sa PDMCritSectEnter
1239 */
1240 DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1241
1242 /**
1243 * Releases the PDM lock.
1244 *
1245 * @param pDevIns The PCI device instance.
1246 */
1247 DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1248
1249 /**
1250 * Gets a bus by it's PDM ordinal (typically the parent bus).
1251 *
1252 * @returns Pointer to the device instance of the bus.
1253 * @param pDevIns The PCI bus device instance.
1254 * @param idxPdmBus The PDM ordinal value of the bus to get.
1255 */
1256 DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1257
1258 /** Just a safety precaution. */
1259 uint32_t u32TheEnd;
1260} PDMPCIHLPR3;
1261/** Pointer to PCI helpers. */
1262typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1263/** Pointer to const PCI helpers. */
1264typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1265
1266/** Current PDMPCIHLPR3 version number. */
1267#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1268
1269
1270/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1271 * These flags are used for memory access transactions via the IOMMU interface.
1272 * @{ */
1273/** Memory read. */
1274#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1275/** Memory write. */
1276#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1277/** Valid flag mask. */
1278#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ | PDMIOMMU_MEM_F_WRITE)
1279/** @} */
1280
1281/**
1282 * IOMMU registration structure for ring-0.
1283 */
1284typedef struct PDMIOMMUREGR0
1285{
1286 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1287 * version. */
1288 uint32_t u32Version;
1289 /** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1290 uint32_t idxIommu;
1291
1292 /**
1293 * Translates the physical address for a memory transaction through the IOMMU.
1294 *
1295 * @returns VBox status code.
1296 * @param pDevIns The IOMMU device instance.
1297 * @param idDevice The device identifier (bus, device, function).
1298 * @param uIova The I/O virtual address being accessed.
1299 * @param cbIova The size of the access.
1300 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1301 * @param pGCPhysSpa Where to store the translated system physical address.
1302 * @param pcbContiguous Where to store the number of contiguous bytes translated
1303 * and permission-checked.
1304 *
1305 * @thread Any.
1306 */
1307 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1308 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1309
1310 /**
1311 * Translates in bulk physical page addresses for memory transactions through the
1312 * IOMMU.
1313 *
1314 * @returns VBox status code.
1315 * @param pDevIns The IOMMU device instance.
1316 * @param idDevice The device identifier (bus, device, function).
1317 * @param cIovas The number of I/O virtual addresses being accessed.
1318 * @param pauIovas The I/O virtual addresses being accessed.
1319 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1320 * @param paGCPhysSpa Where to store the translated system physical page
1321 * addresses.
1322 *
1323 * @thread Any.
1324 */
1325 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1326 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1327
1328 /**
1329 * Performs an interrupt remap request through the IOMMU.
1330 *
1331 * @returns VBox status code.
1332 * @param pDevIns The IOMMU device instance.
1333 * @param idDevice The device identifier (bus, device, function).
1334 * @param pMsiIn The source MSI.
1335 * @param pMsiOut Where to store the remapped MSI.
1336 *
1337 * @thread Any.
1338 */
1339 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1340
1341 /** Just a safety precaution. */
1342 uint32_t u32TheEnd;
1343} PDMIOMMUREGR0;
1344/** Pointer to a IOMMU registration structure. */
1345typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1346
1347/** Current PDMIOMMUREG version number. */
1348#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1349
1350
1351/**
1352 * IOMMU registration structure for raw-mode.
1353 */
1354typedef struct PDMIOMMUREGRC
1355{
1356 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1357 * version. */
1358 uint32_t u32Version;
1359 /** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1360 uint32_t idxIommu;
1361
1362 /**
1363 * Translates the physical address for a memory transaction through the IOMMU.
1364 *
1365 * @returns VBox status code.
1366 * @param pDevIns The IOMMU device instance.
1367 * @param idDevice The device identifier (bus, device, function).
1368 * @param uIova The I/O virtual address being accessed.
1369 * @param cbIova The size of the access.
1370 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1371 * @param pGCPhysSpa Where to store the translated system physical address.
1372 * @param pcbContiguous Where to store the number of contiguous bytes translated
1373 * and permission-checked.
1374 *
1375 * @thread Any.
1376 */
1377 DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1378 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1379
1380 /**
1381 * Translates in bulk physical page addresses for memory transactions through the
1382 * IOMMU.
1383 *
1384 * @returns VBox status code.
1385 * @param pDevIns The IOMMU device instance.
1386 * @param idDevice The device identifier (bus, device, function).
1387 * @param cIovas The number of I/O virtual addresses being accessed.
1388 * @param pauIovas The I/O virtual addresses being accessed.
1389 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1390 * @param paGCPhysSpa Where to store the translated system physical page
1391 * addresses.
1392 *
1393 * @thread Any.
1394 */
1395 DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1396 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1397
1398 /**
1399 * Performs an interrupt remap request through the IOMMU.
1400 *
1401 * @returns VBox status code.
1402 * @param pDevIns The IOMMU device instance.
1403 * @param idDevice The device identifier (bus, device, function).
1404 * @param pMsiIn The source MSI.
1405 * @param pMsiOut Where to store the remapped MSI.
1406 *
1407 * @thread Any.
1408 */
1409 DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1410
1411 /** Just a safety precaution. */
1412 uint32_t u32TheEnd;
1413} PDMIOMMUREGRC;
1414/** Pointer to a IOMMU registration structure. */
1415typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1416
1417/** Current PDMIOMMUREG version number. */
1418#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1419
1420
1421/**
1422 * IOMMU registration structure for ring-3.
1423 */
1424typedef struct PDMIOMMUREGR3
1425{
1426 /** Structure version number. PDM_IOMMUREG_VERSION defines the current
1427 * version. */
1428 uint32_t u32Version;
1429 /** Padding. */
1430 uint32_t uPadding0;
1431
1432 /**
1433 * Translates the physical address for a memory transaction through the IOMMU.
1434 *
1435 * @returns VBox status code.
1436 * @param pDevIns The IOMMU device instance.
1437 * @param idDevice The device identifier (bus, device, function).
1438 * @param uIova The I/O virtual address being accessed.
1439 * @param cbIova The size of the access.
1440 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1441 * @param pGCPhysSpa Where to store the translated system physical address.
1442 * @param pcbContiguous Where to store the number of contiguous bytes translated
1443 * and permission-checked.
1444 *
1445 * @thread Any.
1446 */
1447 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1448 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1449
1450 /**
1451 * Translates in bulk physical page addresses for memory transactions through the
1452 * IOMMU.
1453 *
1454 * @returns VBox status code.
1455 * @param pDevIns The IOMMU device instance.
1456 * @param idDevice The device identifier (bus, device, function).
1457 * @param cIovas The number of I/O virtual addresses being accessed.
1458 * @param pauIovas The I/O virtual addresses being accessed.
1459 * @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1460 * @param paGCPhysSpa Where to store the translated system physical page
1461 * addresses.
1462 *
1463 * @thread Any.
1464 */
1465 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1466 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1467
1468 /**
1469 * Performs an interrupt remap request through the IOMMU.
1470 *
1471 * @returns VBox status code.
1472 * @param pDevIns The IOMMU device instance.
1473 * @param idDevice The device identifier (bus, device, function).
1474 * @param pMsiIn The source MSI.
1475 * @param pMsiOut Where to store the remapped MSI.
1476 *
1477 * @thread Any.
1478 */
1479 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1480
1481 /** Just a safety precaution. */
1482 uint32_t u32TheEnd;
1483} PDMIOMMUREGR3;
1484/** Pointer to a IOMMU registration structure. */
1485typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1486
1487/** Current PDMIOMMUREG version number. */
1488#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1489
1490/** IOMMU registration structure for the current context. */
1491typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1492/** Pointer to an IOMMU registration structure for the current context. */
1493typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1494/** IOMMU registration structure version for the current context. */
1495#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1496
1497
1498/**
1499 * IOMMU helpers for ring-0.
1500 */
1501typedef struct PDMIOMMUHLPR0
1502{
1503 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1504 uint32_t u32Version;
1505
1506 /**
1507 * Acquires the PDM lock.
1508 *
1509 * @returns VINF_SUCCESS on success.
1510 * @returns rc if we failed to acquire the lock.
1511 * @param pDevIns The PCI device instance.
1512 * @param rc What to return if we fail to acquire the lock.
1513 *
1514 * @sa PDMCritSectEnter
1515 */
1516 DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1517
1518 /**
1519 * Releases the PDM lock.
1520 *
1521 * @param pDevIns The PCI device instance.
1522 */
1523 DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1524
1525 /**
1526 * Check whether the calling thread owns the PDM lock.
1527 *
1528 * @returns @c true if the PDM lock is owned, @c false otherwise.
1529 * @param pDevIns The PCI device instance.
1530 */
1531 DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1532
1533 /**
1534 * Send an MSI (when generated by the IOMMU device itself).
1535 *
1536 * @param pDevIns PCI device instance.
1537 * @param pMsi The MSI to send.
1538 * @param uTagSrc The IRQ tag and source (for tracing).
1539 */
1540 DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1541
1542 /** Just a safety precaution. */
1543 uint32_t u32TheEnd;
1544} PDMIOMMUHLPR0;
1545/** Pointer to IOMMU helpers for ring-0. */
1546typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1547/** Pointer to const IOMMU helpers for ring-0. */
1548typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1549
1550/** Current PDMIOMMUHLPR0 version number. */
1551#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1552
1553
1554/**
1555 * IOMMU helpers for raw-mode.
1556 */
1557typedef struct PDMIOMMUHLPRC
1558{
1559 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1560 uint32_t u32Version;
1561
1562 /**
1563 * Acquires the PDM lock.
1564 *
1565 * @returns VINF_SUCCESS on success.
1566 * @returns rc if we failed to acquire the lock.
1567 * @param pDevIns The PCI device instance.
1568 * @param rc What to return if we fail to acquire the lock.
1569 *
1570 * @sa PDMCritSectEnter
1571 */
1572 DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1573
1574 /**
1575 * Releases the PDM lock.
1576 *
1577 * @param pDevIns The PCI device instance.
1578 */
1579 DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1580
1581 /**
1582 * Check whether the threads owns the PDM lock.
1583 *
1584 * @returns @c true if the PDM lock is owned, @c false otherwise.
1585 * @param pDevIns The PCI device instance.
1586 */
1587 DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1588
1589 /**
1590 * Send an MSI (when generated by the IOMMU device itself).
1591 *
1592 * @param pDevIns PCI device instance.
1593 * @param pMsi The MSI to send.
1594 * @param uTagSrc The IRQ tag and source (for tracing).
1595 */
1596 DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1597
1598 /** Just a safety precaution. */
1599 uint32_t u32TheEnd;
1600} PDMIOMMUHLPRC;
1601/** Pointer to IOMMU helpers for raw-mode. */
1602typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1603/** Pointer to const IOMMU helpers for raw-mode. */
1604typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1605
1606/** Current PDMIOMMUHLPRC version number. */
1607#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1608
1609
1610/**
1611 * IOMMU helpers for ring-3.
1612 */
1613typedef struct PDMIOMMUHLPR3
1614{
1615 /** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1616 uint32_t u32Version;
1617
1618 /**
1619 * Acquires the PDM lock.
1620 *
1621 * @returns VINF_SUCCESS on success.
1622 * @returns rc if we failed to acquire the lock.
1623 * @param pDevIns The PCI device instance.
1624 * @param rc What to return if we fail to acquire the lock.
1625 *
1626 * @sa PDMCritSectEnter
1627 */
1628 DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1629
1630 /**
1631 * Releases the PDM lock.
1632 *
1633 * @param pDevIns The PCI device instance.
1634 */
1635 DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1636
1637 /**
1638 * Check whether the threads owns the PDM lock.
1639 *
1640 * @returns @c true if the PDM lock is owned, @c false otherwise.
1641 * @param pDevIns The PCI device instance.
1642 */
1643 DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1644
1645 /**
1646 * Send an MSI (when generated by the IOMMU device itself).
1647 *
1648 * @param pDevIns PCI device instance.
1649 * @param pMsi The MSI to send.
1650 * @param uTagSrc The IRQ tag and source (for tracing).
1651 */
1652 DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1653
1654 /** Just a safety precaution. */
1655 uint32_t u32TheEnd;
1656} PDMIOMMUHLPR3;
1657/** Pointer to IOMMU helpers for raw-mode. */
1658typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1659/** Pointer to const IOMMU helpers for raw-mode. */
1660typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1661
1662/** Current PDMIOMMUHLPR3 version number. */
1663#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1664
1665
1666/**
1667 * Programmable Interrupt Controller registration structure (all contexts).
1668 */
1669typedef struct PDMPICREG
1670{
1671 /** Structure version number. PDM_PICREG_VERSION defines the current version. */
1672 uint32_t u32Version;
1673
1674 /**
1675 * Set the an IRQ.
1676 *
1677 * @param pDevIns Device instance of the PIC.
1678 * @param iIrq IRQ number to set.
1679 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1680 * @param uTagSrc The IRQ tag and source (for tracing).
1681 * @remarks Caller enters the PDM critical section.
1682 */
1683 DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1684
1685 /**
1686 * Get a pending interrupt.
1687 *
1688 * @returns Pending interrupt number.
1689 * @param pDevIns Device instance of the PIC.
1690 * @param puTagSrc Where to return the IRQ tag and source.
1691 * @remarks Caller enters the PDM critical section.
1692 */
1693 DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1694
1695 /** Just a safety precaution. */
1696 uint32_t u32TheEnd;
1697} PDMPICREG;
1698/** Pointer to a PIC registration structure. */
1699typedef PDMPICREG *PPDMPICREG;
1700
1701/** Current PDMPICREG version number. */
1702#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1703
1704/**
1705 * PIC helpers, same in all contexts.
1706 */
1707typedef struct PDMPICHLP
1708{
1709 /** Structure version. PDM_PICHLP_VERSION defines the current version. */
1710 uint32_t u32Version;
1711
1712 /**
1713 * Set the interrupt force action flag.
1714 *
1715 * @param pDevIns Device instance of the PIC.
1716 */
1717 DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1718
1719 /**
1720 * Clear the interrupt force action flag.
1721 *
1722 * @param pDevIns Device instance of the PIC.
1723 */
1724 DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1725
1726 /**
1727 * Acquires the PDM lock.
1728 *
1729 * @returns VINF_SUCCESS on success.
1730 * @returns rc if we failed to acquire the lock.
1731 * @param pDevIns The PIC device instance.
1732 * @param rc What to return if we fail to acquire the lock.
1733 *
1734 * @sa PDMCritSectEnter
1735 */
1736 DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1737
1738 /**
1739 * Releases the PDM lock.
1740 *
1741 * @param pDevIns The PIC device instance.
1742 */
1743 DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1744
1745 /** Just a safety precaution. */
1746 uint32_t u32TheEnd;
1747} PDMPICHLP;
1748/** Pointer to PIC helpers. */
1749typedef PDMPICHLP *PPDMPICHLP;
1750/** Pointer to const PIC helpers. */
1751typedef const PDMPICHLP *PCPDMPICHLP;
1752
1753/** Current PDMPICHLP version number. */
1754#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1755
1756
1757/**
1758 * Firmware registration structure.
1759 */
1760typedef struct PDMFWREG
1761{
1762 /** Struct version+magic number (PDM_FWREG_VERSION). */
1763 uint32_t u32Version;
1764
1765 /**
1766 * Checks whether this is a hard or soft reset.
1767 *
1768 * The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1769 * is 5, 9 or 0xA.
1770 *
1771 * @returns true if hard reset, false if soft.
1772 * @param pDevIns Device instance of the firmware.
1773 * @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1774 */
1775 DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1776
1777 /** Just a safety precaution. */
1778 uint32_t u32TheEnd;
1779} PDMFWREG;
1780/** Pointer to a FW registration structure. */
1781typedef PDMFWREG *PPDMFWREG;
1782/** Pointer to a const FW registration structure. */
1783typedef PDMFWREG const *PCPDMFWREG;
1784
1785/** Current PDMFWREG version number. */
1786#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1787
1788/**
1789 * Firmware R3 helpers.
1790 */
1791typedef struct PDMFWHLPR3
1792{
1793 /** Structure version. PDM_FWHLP_VERSION defines the current version. */
1794 uint32_t u32Version;
1795
1796 /** Just a safety precaution. */
1797 uint32_t u32TheEnd;
1798} PDMFWHLPR3;
1799
1800/** Pointer to FW R3 helpers. */
1801typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1802/** Pointer to const FW R3 helpers. */
1803typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1804
1805/** Current PDMFWHLPR3 version number. */
1806#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1807
1808
1809/**
1810 * APIC mode argument for apicR3SetCpuIdFeatureLevel.
1811 *
1812 * Also used in saved-states, CFGM don't change existing values.
1813 */
1814typedef enum PDMAPICMODE
1815{
1816 /** Invalid 0 entry. */
1817 PDMAPICMODE_INVALID = 0,
1818 /** No APIC. */
1819 PDMAPICMODE_NONE,
1820 /** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1821 PDMAPICMODE_APIC,
1822 /** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1823 PDMAPICMODE_X2APIC,
1824 /** The usual 32-bit paranoia. */
1825 PDMAPICMODE_32BIT_HACK = 0x7fffffff
1826} PDMAPICMODE;
1827
1828/**
1829 * APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1830 */
1831typedef enum PDMAPICIRQ
1832{
1833 /** Invalid 0 entry. */
1834 PDMAPICIRQ_INVALID = 0,
1835 /** Normal hardware interrupt. */
1836 PDMAPICIRQ_HARDWARE,
1837 /** NMI. */
1838 PDMAPICIRQ_NMI,
1839 /** SMI. */
1840 PDMAPICIRQ_SMI,
1841 /** ExtINT (HW interrupt via PIC). */
1842 PDMAPICIRQ_EXTINT,
1843 /** Interrupt arrived, needs to be updated to the IRR. */
1844 PDMAPICIRQ_UPDATE_PENDING,
1845 /** The usual 32-bit paranoia. */
1846 PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1847} PDMAPICIRQ;
1848
1849
1850/**
1851 * I/O APIC registration structure (all contexts).
1852 */
1853typedef struct PDMIOAPICREG
1854{
1855 /** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1856 uint32_t u32Version;
1857
1858 /**
1859 * Set an IRQ.
1860 *
1861 * @param pDevIns Device instance of the I/O APIC.
1862 * @param uBusDevFn The bus:device:function of the device initiating the
1863 * IRQ. Can be NIL_PCIBDF.
1864 * @param iIrq IRQ number to set.
1865 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1866 * @param uTagSrc The IRQ tag and source (for tracing).
1867 *
1868 * @remarks Caller enters the PDM critical section
1869 * Actually, as per 2018-07-21 this isn't true (bird).
1870 */
1871 DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1872
1873 /**
1874 * Send a MSI.
1875 *
1876 * @param pDevIns Device instance of the I/O APIC.
1877 * @param uBusDevFn The bus:device:function of the device initiating the
1878 * MSI. Cannot be NIL_PCIBDF.
1879 * @param pMsi The MSI to send.
1880 * @param uTagSrc The IRQ tag and source (for tracing).
1881 *
1882 * @remarks Caller enters the PDM critical section
1883 * Actually, as per 2018-07-21 this isn't true (bird).
1884 */
1885 DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1886
1887 /**
1888 * Set the EOI for an interrupt vector.
1889 *
1890 * @param pDevIns Device instance of the I/O APIC.
1891 * @param u8Vector The vector.
1892 *
1893 * @remarks Caller enters the PDM critical section
1894 * Actually, as per 2018-07-21 this isn't true (bird).
1895 */
1896 DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1897
1898 /** Just a safety precaution. */
1899 uint32_t u32TheEnd;
1900} PDMIOAPICREG;
1901/** Pointer to an APIC registration structure. */
1902typedef PDMIOAPICREG *PPDMIOAPICREG;
1903
1904/** Current PDMAPICREG version number. */
1905#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1906
1907
1908/**
1909 * IOAPIC helpers, same in all contexts.
1910 */
1911typedef struct PDMIOAPICHLP
1912{
1913 /** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1914 uint32_t u32Version;
1915
1916 /**
1917 * Private interface between the IOAPIC and APIC.
1918 *
1919 * @returns status code.
1920 * @param pDevIns Device instance of the IOAPIC.
1921 * @param u8Dest See APIC implementation.
1922 * @param u8DestMode See APIC implementation.
1923 * @param u8DeliveryMode See APIC implementation.
1924 * @param uVector See APIC implementation.
1925 * @param u8Polarity See APIC implementation.
1926 * @param u8TriggerMode See APIC implementation.
1927 * @param uTagSrc The IRQ tag and source (for tracing).
1928 *
1929 * @sa APICBusDeliver()
1930 */
1931 DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1932 uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1933
1934 /**
1935 * Acquires the PDM lock.
1936 *
1937 * @returns VINF_SUCCESS on success.
1938 * @returns rc if we failed to acquire the lock.
1939 * @param pDevIns The IOAPIC device instance.
1940 * @param rc What to return if we fail to acquire the lock.
1941 *
1942 * @sa PDMCritSectEnter
1943 */
1944 DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1945
1946 /**
1947 * Releases the PDM lock.
1948 *
1949 * @param pDevIns The IOAPIC device instance.
1950 */
1951 DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1952
1953 /**
1954 * Checks if the calling thread owns the PDM lock.
1955 *
1956 * @param pDevIns The IOAPIC device instance.
1957 */
1958 DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1959
1960 /**
1961 * Private interface between the IOAPIC and IOMMU.
1962 *
1963 * @returns status code.
1964 * @param pDevIns Device instance of the IOAPIC.
1965 * @param idDevice The device identifier (bus, device, function).
1966 * @param pMsiIn The source MSI.
1967 * @param pMsiOut Where to store the remapped MSI (only updated when
1968 * VINF_SUCCESS is returned).
1969 */
1970 DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1971
1972 /** Just a safety precaution. */
1973 uint32_t u32TheEnd;
1974} PDMIOAPICHLP;
1975/** Pointer to IOAPIC helpers. */
1976typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1977/** Pointer to const IOAPIC helpers. */
1978typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1979
1980/** Current PDMIOAPICHLP version number. */
1981#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1982
1983
1984/**
1985 * HPET registration structure.
1986 */
1987typedef struct PDMHPETREG
1988{
1989 /** Struct version+magic number (PDM_HPETREG_VERSION). */
1990 uint32_t u32Version;
1991} PDMHPETREG;
1992/** Pointer to an HPET registration structure. */
1993typedef PDMHPETREG *PPDMHPETREG;
1994
1995/** Current PDMHPETREG version number. */
1996#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1997
1998/**
1999 * HPET RC helpers.
2000 *
2001 * @remarks Keep this around in case HPET will need PDM interaction in again RC
2002 * at some later point.
2003 */
2004typedef struct PDMHPETHLPRC
2005{
2006 /** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2007 uint32_t u32Version;
2008
2009 /** Just a safety precaution. */
2010 uint32_t u32TheEnd;
2011} PDMHPETHLPRC;
2012
2013/** Pointer to HPET RC helpers. */
2014typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2015/** Pointer to const HPET RC helpers. */
2016typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2017
2018/** Current PDMHPETHLPRC version number. */
2019#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2020
2021
2022/**
2023 * HPET R0 helpers.
2024 *
2025 * @remarks Keep this around in case HPET will need PDM interaction in again R0
2026 * at some later point.
2027 */
2028typedef struct PDMHPETHLPR0
2029{
2030 /** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2031 uint32_t u32Version;
2032
2033 /** Just a safety precaution. */
2034 uint32_t u32TheEnd;
2035} PDMHPETHLPR0;
2036
2037/** Pointer to HPET R0 helpers. */
2038typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2039/** Pointer to const HPET R0 helpers. */
2040typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2041
2042/** Current PDMHPETHLPR0 version number. */
2043#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2044
2045/**
2046 * HPET R3 helpers.
2047 */
2048typedef struct PDMHPETHLPR3
2049{
2050 /** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2051 uint32_t u32Version;
2052
2053 /**
2054 * Set legacy mode on PIT and RTC.
2055 *
2056 * @returns VINF_SUCCESS on success.
2057 * @returns rc if we failed to set legacy mode.
2058 * @param pDevIns Device instance of the HPET.
2059 * @param fActivated Whether legacy mode is activated or deactivated.
2060 */
2061 DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2062
2063
2064 /**
2065 * Set IRQ, bypassing ISA bus override rules.
2066 *
2067 * @returns VINF_SUCCESS on success.
2068 * @returns rc if we failed to set legacy mode.
2069 * @param pDevIns Device instance of the HPET.
2070 * @param iIrq IRQ number to set.
2071 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2072 */
2073 DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2074
2075 /** Just a safety precaution. */
2076 uint32_t u32TheEnd;
2077} PDMHPETHLPR3;
2078
2079/** Pointer to HPET R3 helpers. */
2080typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2081/** Pointer to const HPET R3 helpers. */
2082typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2083
2084/** Current PDMHPETHLPR3 version number. */
2085#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2086
2087
2088/**
2089 * Raw PCI device registration structure.
2090 */
2091typedef struct PDMPCIRAWREG
2092{
2093 /** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2094 uint32_t u32Version;
2095 /** Just a safety precaution. */
2096 uint32_t u32TheEnd;
2097} PDMPCIRAWREG;
2098/** Pointer to a raw PCI registration structure. */
2099typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2100
2101/** Current PDMPCIRAWREG version number. */
2102#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2103
2104/**
2105 * Raw PCI device raw-mode context helpers.
2106 */
2107typedef struct PDMPCIRAWHLPRC
2108{
2109 /** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2110 uint32_t u32Version;
2111 /** Just a safety precaution. */
2112 uint32_t u32TheEnd;
2113} PDMPCIRAWHLPRC;
2114/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2115typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2116/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2117typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2118
2119/** Current PDMPCIRAWHLPRC version number. */
2120#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2121
2122/**
2123 * Raw PCI device ring-0 context helpers.
2124 */
2125typedef struct PDMPCIRAWHLPR0
2126{
2127 /** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2128 uint32_t u32Version;
2129 /** Just a safety precaution. */
2130 uint32_t u32TheEnd;
2131} PDMPCIRAWHLPR0;
2132/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2133typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2134/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2135typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2136
2137/** Current PDMPCIRAWHLPR0 version number. */
2138#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2139
2140
2141/**
2142 * Raw PCI device ring-3 context helpers.
2143 */
2144typedef struct PDMPCIRAWHLPR3
2145{
2146 /** Undefined structure version and magic number. */
2147 uint32_t u32Version;
2148
2149 /**
2150 * Gets the address of the RC raw PCI device helpers.
2151 *
2152 * This should be called at both construction and relocation time to obtain
2153 * the correct address of the RC helpers.
2154 *
2155 * @returns RC pointer to the raw PCI device helpers.
2156 * @param pDevIns Device instance of the raw PCI device.
2157 */
2158 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2159
2160 /**
2161 * Gets the address of the R0 raw PCI device helpers.
2162 *
2163 * This should be called at both construction and relocation time to obtain
2164 * the correct address of the R0 helpers.
2165 *
2166 * @returns R0 pointer to the raw PCI device helpers.
2167 * @param pDevIns Device instance of the raw PCI device.
2168 */
2169 DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2170
2171 /** Just a safety precaution. */
2172 uint32_t u32TheEnd;
2173} PDMPCIRAWHLPR3;
2174/** Pointer to raw PCI R3 helpers. */
2175typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2176/** Pointer to const raw PCI R3 helpers. */
2177typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2178
2179/** Current PDMPCIRAWHLPR3 version number. */
2180#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2181
2182
2183#ifdef IN_RING3
2184
2185/**
2186 * DMA Transfer Handler.
2187 *
2188 * @returns Number of bytes transferred.
2189 * @param pDevIns The device instance that registered the handler.
2190 * @param pvUser User pointer.
2191 * @param uChannel Channel number.
2192 * @param off DMA position.
2193 * @param cb Block size.
2194 * @remarks The device lock is take before the callback (in fact, the locks of
2195 * DMA devices and the DMA controller itself are taken).
2196 */
2197typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2198 uint32_t off, uint32_t cb));
2199/** Pointer to a FNDMATRANSFERHANDLER(). */
2200typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2201
2202/**
2203 * DMA Controller registration structure.
2204 */
2205typedef struct PDMDMAREG
2206{
2207 /** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2208 uint32_t u32Version;
2209
2210 /**
2211 * Execute pending transfers.
2212 *
2213 * @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2214 * @param pDevIns Device instance of the DMAC.
2215 * @remarks No locks held, called on EMT(0) as a form of serialization.
2216 */
2217 DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2218
2219 /**
2220 * Register transfer function for DMA channel.
2221 *
2222 * @param pDevIns Device instance of the DMAC.
2223 * @param uChannel Channel number.
2224 * @param pDevInsHandler The device instance of the device making the
2225 * regstration (will be passed to the callback).
2226 * @param pfnTransferHandler Device specific transfer function.
2227 * @param pvUser User pointer to be passed to the callback.
2228 * @remarks No locks held, called on an EMT.
2229 */
2230 DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2231 PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2232
2233 /**
2234 * Read memory
2235 *
2236 * @returns Number of bytes read.
2237 * @param pDevIns Device instance of the DMAC.
2238 * @param uChannel Channel number.
2239 * @param pvBuffer Pointer to target buffer.
2240 * @param off DMA position.
2241 * @param cbBlock Block size.
2242 * @remarks No locks held, called on an EMT.
2243 */
2244 DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2245
2246 /**
2247 * Write memory
2248 *
2249 * @returns Number of bytes written.
2250 * @param pDevIns Device instance of the DMAC.
2251 * @param uChannel Channel number.
2252 * @param pvBuffer Memory to write.
2253 * @param off DMA position.
2254 * @param cbBlock Block size.
2255 * @remarks No locks held, called on an EMT.
2256 */
2257 DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2258
2259 /**
2260 * Set the DREQ line.
2261 *
2262 * @param pDevIns Device instance of the DMAC.
2263 * @param uChannel Channel number.
2264 * @param uLevel Level of the line.
2265 * @remarks No locks held, called on an EMT.
2266 */
2267 DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2268
2269 /**
2270 * Get channel mode
2271 *
2272 * @returns Channel mode.
2273 * @param pDevIns Device instance of the DMAC.
2274 * @param uChannel Channel number.
2275 * @remarks No locks held, called on an EMT.
2276 */
2277 DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2278
2279} PDMDMACREG;
2280/** Pointer to a DMAC registration structure. */
2281typedef PDMDMACREG *PPDMDMACREG;
2282
2283/** Current PDMDMACREG version number. */
2284#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2285
2286
2287/**
2288 * DMA Controller device helpers.
2289 */
2290typedef struct PDMDMACHLP
2291{
2292 /** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2293 uint32_t u32Version;
2294
2295 /* to-be-defined */
2296
2297} PDMDMACHLP;
2298/** Pointer to DMAC helpers. */
2299typedef PDMDMACHLP *PPDMDMACHLP;
2300/** Pointer to const DMAC helpers. */
2301typedef const PDMDMACHLP *PCPDMDMACHLP;
2302
2303/** Current PDMDMACHLP version number. */
2304#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2305
2306#endif /* IN_RING3 */
2307
2308
2309
2310/**
2311 * RTC registration structure.
2312 */
2313typedef struct PDMRTCREG
2314{
2315 /** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2316 uint32_t u32Version;
2317 uint32_t u32Alignment; /**< structure size alignment. */
2318
2319 /**
2320 * Write to a CMOS register and update the checksum if necessary.
2321 *
2322 * @returns VBox status code.
2323 * @param pDevIns Device instance of the RTC.
2324 * @param iReg The CMOS register index.
2325 * @param u8Value The CMOS register value.
2326 * @remarks Caller enters the device critical section.
2327 */
2328 DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2329
2330 /**
2331 * Read a CMOS register.
2332 *
2333 * @returns VBox status code.
2334 * @param pDevIns Device instance of the RTC.
2335 * @param iReg The CMOS register index.
2336 * @param pu8Value Where to store the CMOS register value.
2337 * @remarks Caller enters the device critical section.
2338 */
2339 DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2340
2341} PDMRTCREG;
2342/** Pointer to a RTC registration structure. */
2343typedef PDMRTCREG *PPDMRTCREG;
2344/** Pointer to a const RTC registration structure. */
2345typedef const PDMRTCREG *PCPDMRTCREG;
2346
2347/** Current PDMRTCREG version number. */
2348#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2349
2350
2351/**
2352 * RTC device helpers.
2353 */
2354typedef struct PDMRTCHLP
2355{
2356 /** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2357 uint32_t u32Version;
2358
2359 /* to-be-defined */
2360
2361} PDMRTCHLP;
2362/** Pointer to RTC helpers. */
2363typedef PDMRTCHLP *PPDMRTCHLP;
2364/** Pointer to const RTC helpers. */
2365typedef const PDMRTCHLP *PCPDMRTCHLP;
2366
2367/** Current PDMRTCHLP version number. */
2368#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2369
2370
2371
2372/** @name Flags for PCI I/O region registration
2373 * @{ */
2374/** No handle is passed. */
2375#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2376/** An I/O port handle is passed. */
2377#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2378/** An MMIO range handle is passed. */
2379#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2380/** An MMIO2 handle is passed. */
2381#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2382/** Handle type mask. */
2383#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2384/** New-style (mostly wrt callbacks). */
2385#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2386/** Mask of valid flags. */
2387#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2388/** @} */
2389
2390
2391/** @name Flags for the guest physical read/write helpers
2392 * @{ */
2393/** Default flag with no indication whether the data is processed by the device or just passed through. */
2394#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2395/** The data is user data which is just passed through between the guest and the source or destination and not processed
2396 * by the device in any way. */
2397#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2398/** The data is metadata and being processed by the device in some way. */
2399#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2400/** @} */
2401
2402
2403#ifdef IN_RING3
2404
2405/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2406 * @{ */
2407/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2408 * This is handy when registering multiple PCI device functions and the device
2409 * number is left up to the PCI bus. In order to facilitate one PDM device
2410 * instance for each PCI function, this searches earlier PDM device
2411 * instances as well. */
2412# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2413/** Use the first unused device number (all functions must be unused). */
2414# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2415/** Use the first unused device function. */
2416# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2417
2418/** The device and function numbers are not mandatory, just suggestions. */
2419# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2420/** Registering a PCI bridge device. */
2421# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2422/** Valid flag mask. */
2423# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2424/** @} */
2425
2426/** Current PDMDEVHLPR3 version number. */
2427#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 60, 0)
2428
2429/**
2430 * PDM Device API.
2431 */
2432typedef struct PDMDEVHLPR3
2433{
2434 /** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2435 uint32_t u32Version;
2436
2437 /** @name I/O ports
2438 * @{ */
2439 /**
2440 * Creates a range of I/O ports for a device.
2441 *
2442 * The I/O port range must be mapped in a separately call. Any ring-0 and
2443 * raw-mode context callback handlers needs to be set up in the respective
2444 * contexts.
2445 *
2446 * @returns VBox status.
2447 * @param pDevIns The device instance to register the ports with.
2448 * @param cPorts Number of ports to register.
2449 * @param fFlags IOM_IOPORT_F_XXX.
2450 * @param pPciDev The PCI device the range is associated with, if
2451 * applicable.
2452 * @param iPciRegion The PCI device region in the high 16-bit word and
2453 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2454 * @param pfnOut Pointer to function which is gonna handle OUT
2455 * operations. Optional.
2456 * @param pfnIn Pointer to function which is gonna handle IN operations.
2457 * Optional.
2458 * @param pfnOutStr Pointer to function which is gonna handle string OUT
2459 * operations. Optional.
2460 * @param pfnInStr Pointer to function which is gonna handle string IN
2461 * operations. Optional.
2462 * @param pvUser User argument to pass to the callbacks.
2463 * @param pszDesc Pointer to description string. This must not be freed.
2464 * @param paExtDescs Extended per-port descriptions, optional. Partial range
2465 * coverage is allowed. This must not be freed.
2466 * @param phIoPorts Where to return the I/O port range handle.
2467 *
2468 * @remarks Caller enters the device critical section prior to invoking the
2469 * registered callback methods.
2470 *
2471 * @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2472 * PDMDevHlpIoPortUnmap.
2473 */
2474 DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2475 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2476 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2477 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2478
2479 /**
2480 * Maps an I/O port range.
2481 *
2482 * @returns VBox status.
2483 * @param pDevIns The device instance to register the ports with.
2484 * @param hIoPorts The I/O port range handle.
2485 * @param Port Where to map the range.
2486 * @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2487 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2488 */
2489 DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2490
2491 /**
2492 * Unmaps an I/O port range.
2493 *
2494 * @returns VBox status.
2495 * @param pDevIns The device instance to register the ports with.
2496 * @param hIoPorts The I/O port range handle.
2497 * @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2498 * PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2499 */
2500 DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2501
2502 /**
2503 * Gets the mapping address of the I/O port range @a hIoPorts.
2504 *
2505 * @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2506 * parameters).
2507 * @param pDevIns The device instance to register the ports with.
2508 * @param hIoPorts The I/O port range handle.
2509 */
2510 DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2511
2512 /**
2513 * Writes to an I/O port register.
2514 *
2515 * @returns Strict VBox status code. Informational status codes other than the one documented
2516 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2517 * @retval VINF_SUCCESS Success.
2518 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2519 * status code must be passed on to EM.
2520 *
2521 * @param pDevIns The device instance to register the ports with.
2522 * @param Port The port to write to.
2523 * @param u32Value The value to write.
2524 * @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2525 *
2526 * @thread EMT
2527 * @todo r=aeichner This is only used by DevPCI.cpp to write the ELCR of the PIC. This shouldn't be done that way
2528 * and removed again as soon as possible (no time right now)...
2529 */
2530 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortWrite,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue));
2531 /** @} */
2532
2533 /** @name MMIO
2534 * @{ */
2535 /**
2536 * Creates a memory mapped I/O (MMIO) region for a device.
2537 *
2538 * The MMIO region must be mapped in a separately call. Any ring-0 and
2539 * raw-mode context callback handlers needs to be set up in the respective
2540 * contexts.
2541 *
2542 * @returns VBox status.
2543 * @param pDevIns The device instance to register the ports with.
2544 * @param cbRegion The size of the region in bytes.
2545 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2546 * @param pPciDev The PCI device the range is associated with, if
2547 * applicable.
2548 * @param iPciRegion The PCI device region in the high 16-bit word and
2549 * sub-region in the low 16-bit word. UINT32_MAX if NA.
2550 * @param pfnWrite Pointer to function which is gonna handle Write
2551 * operations.
2552 * @param pfnRead Pointer to function which is gonna handle Read
2553 * operations.
2554 * @param pfnFill Pointer to function which is gonna handle Fill/memset
2555 * operations. (optional)
2556 * @param pvUser User argument to pass to the callbacks.
2557 * @param pszDesc Pointer to description string. This must not be freed.
2558 * @param phRegion Where to return the MMIO region handle.
2559 *
2560 * @remarks Caller enters the device critical section prior to invoking the
2561 * registered callback methods.
2562 *
2563 * @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2564 */
2565 DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2566 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2567 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2568 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion));
2569
2570 /**
2571 * Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2572 *
2573 * @returns VBox status.
2574 * @param pDevIns The device instance the region is associated with.
2575 * @param hRegion The MMIO region handle.
2576 * @param GCPhys Where to map the region.
2577 * @note An MMIO range may overlap with base memory if a lot of RAM is
2578 * configured for the VM, in which case we'll drop the base memory
2579 * pages. Presently we will make no attempt to preserve anything that
2580 * happens to be present in the base memory that is replaced, this is
2581 * technically incorrect but it's just not worth the effort to do
2582 * right, at least not at this point.
2583 * @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2584 * PDMDevHlpMmioSetUpContext
2585 */
2586 DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2587
2588 /**
2589 * Unmaps a memory mapped I/O (MMIO) region.
2590 *
2591 * @returns VBox status.
2592 * @param pDevIns The device instance the region is associated with.
2593 * @param hRegion The MMIO region handle.
2594 * @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2595 * PDMDevHlpMmioSetUpContext
2596 */
2597 DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2598
2599 /**
2600 * Reduces the length of a MMIO range.
2601 *
2602 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2603 * only work during saved state restore. It will not call the PCI bus code, as
2604 * that is expected to restore the saved resource configuration.
2605 *
2606 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2607 * called it will only map @a cbRegion bytes and not the value set during
2608 * registration.
2609 *
2610 * @return VBox status code.
2611 * @param pDevIns The device owning the range.
2612 * @param hRegion The MMIO region handle.
2613 * @param cbRegion The new size, must be smaller.
2614 */
2615 DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2616
2617 /**
2618 * Gets the mapping address of the MMIO region @a hRegion.
2619 *
2620 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2621 * @param pDevIns The device instance to register the ports with.
2622 * @param hRegion The MMIO region handle.
2623 */
2624 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2625 /** @} */
2626
2627 /** @name MMIO2
2628 * @{ */
2629 /**
2630 * Creates a MMIO2 region.
2631 *
2632 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2633 * associated with a device. It is also non-shared memory with a permanent
2634 * ring-3 mapping and page backing (presently).
2635 *
2636 * @returns VBox status.
2637 * @param pDevIns The device instance.
2638 * @param pPciDev The PCI device the region is associated with, or
2639 * NULL if no PCI device association.
2640 * @param iPciRegion The region number. Use the PCI region number as
2641 * this must be known to the PCI bus device too. If
2642 * it's not associated with the PCI device, then
2643 * any number up to UINT8_MAX is fine.
2644 * @param cbRegion The size (in bytes) of the region.
2645 * @param fFlags Reserved for future use, must be zero.
2646 * @param pszDesc Pointer to description string. This must not be
2647 * freed.
2648 * @param ppvMapping Where to store the address of the ring-3 mapping
2649 * of the memory.
2650 * @param phRegion Where to return the MMIO2 region handle.
2651 *
2652 * @thread EMT(0)
2653 */
2654 DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2655 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion));
2656
2657 /**
2658 * Destroys a MMIO2 region, unmapping it and freeing the memory.
2659 *
2660 * Any physical access handlers registered for the region must be deregistered
2661 * before calling this function.
2662 *
2663 * @returns VBox status code.
2664 * @param pDevIns The device instance.
2665 * @param hRegion The MMIO2 region handle.
2666 * @thread EMT.
2667 */
2668 DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2669
2670 /**
2671 * Maps a MMIO2 region (into the guest physical address space).
2672 *
2673 * @returns VBox status.
2674 * @param pDevIns The device instance the region is associated with.
2675 * @param hRegion The MMIO2 region handle.
2676 * @param GCPhys Where to map the region.
2677 * @note A MMIO2 region overlap with base memory if a lot of RAM is
2678 * configured for the VM, in which case we'll drop the base memory
2679 * pages. Presently we will make no attempt to preserve anything that
2680 * happens to be present in the base memory that is replaced, this is
2681 * technically incorrect but it's just not worth the effort to do
2682 * right, at least not at this point.
2683 * @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2684 */
2685 DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2686
2687 /**
2688 * Unmaps a MMIO2 region.
2689 *
2690 * @returns VBox status.
2691 * @param pDevIns The device instance the region is associated with.
2692 * @param hRegion The MMIO2 region handle.
2693 * @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2694 */
2695 DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2696
2697 /**
2698 * Reduces the length of a MMIO range.
2699 *
2700 * This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2701 * only work during saved state restore. It will not call the PCI bus code, as
2702 * that is expected to restore the saved resource configuration.
2703 *
2704 * It just adjusts the mapping length of the region so that when pfnMmioMap is
2705 * called it will only map @a cbRegion bytes and not the value set during
2706 * registration.
2707 *
2708 * @return VBox status code.
2709 * @param pDevIns The device owning the range.
2710 * @param hRegion The MMIO2 region handle.
2711 * @param cbRegion The new size, must be smaller.
2712 */
2713 DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2714
2715 /**
2716 * Gets the mapping address of the MMIO region @a hRegion.
2717 *
2718 * @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2719 * @param pDevIns The device instance to register the ports with.
2720 * @param hRegion The MMIO2 region handle.
2721 */
2722 DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2723
2724 /**
2725 * Changes the number of an MMIO2 or pre-registered MMIO region.
2726 *
2727 * This should only be used to deal with saved state problems, so there is no
2728 * convenience inline wrapper for this method.
2729 *
2730 * @returns VBox status code.
2731 * @param pDevIns The device instance.
2732 * @param hRegion The MMIO2 region handle.
2733 * @param iNewRegion The new region index.
2734 *
2735 * @sa @bugref{9359}
2736 */
2737 DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2738
2739 /**
2740 * Mapping an MMIO2 page in place of an MMIO page for direct access.
2741 *
2742 * This is a special optimization used by the VGA device. Call
2743 * PDMDevHlpMmioResetRegion() to undo the mapping.
2744 *
2745 * @returns VBox status code. This API may return VINF_SUCCESS even if no
2746 * remapping is made.
2747 * @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
2748 *
2749 * @param pDevIns The device instance @a hRegion and @a hMmio2 are
2750 * associated with.
2751 * @param hRegion The handle to the MMIO region.
2752 * @param offRegion The offset into @a hRegion of the page to be
2753 * remapped.
2754 * @param hMmio2 The MMIO2 handle.
2755 * @param offMmio2 Offset into @a hMmio2 of the page to be use for the
2756 * mapping.
2757 * @param fPageFlags Page flags to set. Must be (X86_PTE_RW | X86_PTE_P)
2758 * for the time being.
2759 */
2760 DECLR3CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
2761 uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
2762
2763 /**
2764 * Reset a previously modified MMIO region; restore the access flags.
2765 *
2766 * This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
2767 * intended for some ancient VGA hack. However, it would be great to extend it
2768 * beyond VT-x and/or nested-paging.
2769 *
2770 * @returns VBox status code.
2771 *
2772 * @param pDevIns The device instance @a hRegion is associated with.
2773 * @param hRegion The handle to the MMIO region.
2774 */
2775 DECLR3CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2776 /** @} */
2777
2778 /**
2779 * Register a ROM (BIOS) region.
2780 *
2781 * It goes without saying that this is read-only memory. The memory region must be
2782 * in unassigned memory. I.e. from the top of the address space or on the PC in
2783 * the 0xa0000-0xfffff range.
2784 *
2785 * @returns VBox status.
2786 * @param pDevIns The device instance owning the ROM region.
2787 * @param GCPhysStart First physical address in the range.
2788 * Must be page aligned!
2789 * @param cbRange The size of the range (in bytes).
2790 * Must be page aligned!
2791 * @param pvBinary Pointer to the binary data backing the ROM image.
2792 * @param cbBinary The size of the binary pointer. This must
2793 * be equal or smaller than @a cbRange.
2794 * @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2795 * @param pszDesc Pointer to description string. This must not be freed.
2796 *
2797 * @remark There is no way to remove the rom, automatically on device cleanup or
2798 * manually from the device yet. At present I doubt we need such features...
2799 */
2800 DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2801 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc));
2802
2803 /**
2804 * Changes the protection of shadowed ROM mapping.
2805 *
2806 * This is intented for use by the system BIOS, chipset or device in question to
2807 * change the protection of shadowed ROM code after init and on reset.
2808 *
2809 * @param pDevIns The device instance.
2810 * @param GCPhysStart Where the mapping starts.
2811 * @param cbRange The size of the mapping.
2812 * @param enmProt The new protection type.
2813 */
2814 DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2815
2816 /**
2817 * Register a save state data unit.
2818 *
2819 * @returns VBox status.
2820 * @param pDevIns The device instance.
2821 * @param uVersion Data layout version number.
2822 * @param cbGuess The approximate amount of data in the unit.
2823 * Only for progress indicators.
2824 * @param pszBefore Name of data unit which we should be put in
2825 * front of. Optional (NULL).
2826 *
2827 * @param pfnLivePrep Prepare live save callback, optional.
2828 * @param pfnLiveExec Execute live save callback, optional.
2829 * @param pfnLiveVote Vote live save callback, optional.
2830 *
2831 * @param pfnSavePrep Prepare save callback, optional.
2832 * @param pfnSaveExec Execute save callback, optional.
2833 * @param pfnSaveDone Done save callback, optional.
2834 *
2835 * @param pfnLoadPrep Prepare load callback, optional.
2836 * @param pfnLoadExec Execute load callback, optional.
2837 * @param pfnLoadDone Done load callback, optional.
2838 * @remarks Caller enters the device critical section prior to invoking the
2839 * registered callback methods.
2840 */
2841 DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2842 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2843 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2844 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2845
2846 /** @name Exported SSM Functions
2847 * @{ */
2848 DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2849 DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2850 DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2851 DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2852 DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2853 DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2854 DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2855 DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2856 DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2857 DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2858 DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2859 DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2860 DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2861 DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2862 DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2863 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2864 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2865 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2866 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2867 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2868 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2869 DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2870 DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2871 DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2872 DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2873 DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2874 DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2875 DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2876 DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void *pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void *pvUser));
2877 DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2878 DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2879 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2880 DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2881 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2882 DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2883 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2884 DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2885 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2886 DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2887 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2888 DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2889 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2890 DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2891 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2892 DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2893 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2894 DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2895 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2896 DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2897 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2898 DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2899 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2900 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2901 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2902 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2903 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2904 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2905 DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2906 DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2907 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2908 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2909 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2910 DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2911 DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2912 DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2913 DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2914 DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2915 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2916 DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char *psz, size_t cbMax, size_t *pcbStr));
2917 DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2918 DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2919 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2920 DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2921 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2922 DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2923 DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2924 DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2925 DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2926 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2927 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2928 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2929 DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2930 DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2931 /** @} */
2932
2933 /**
2934 * Creates a timer w/ a cross context handle.
2935 *
2936 * @returns VBox status.
2937 * @param pDevIns The device instance.
2938 * @param enmClock The clock to use on this timer.
2939 * @param pfnCallback Callback function.
2940 * @param pvUser User argument for the callback.
2941 * @param fFlags Flags, see TMTIMER_FLAGS_*.
2942 * @param pszDesc Pointer to description string which must stay around
2943 * until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2944 * @param phTimer Where to store the timer handle on success.
2945 * @remarks Caller enters the device critical section prior to invoking the
2946 * callback.
2947 */
2948 DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2949 void *pvUser, uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer));
2950
2951 /** @name Timer handle method wrappers
2952 * @{ */
2953 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2954 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2955 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2956 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2957 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2958 DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2959 DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2960 DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2961 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2962 /** Takes the clock lock then enters the specified critical section. */
2963 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2964 DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2965 DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2966 DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2967 DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2968 DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2969 DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2970 DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2971 DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2972 DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2973 DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2974 DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2975 DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2976 DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2977 /** @sa TMR3TimerSkip */
2978 DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2979 /** @} */
2980
2981 /**
2982 * Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2983 *
2984 * @returns pTime.
2985 * @param pDevIns The device instance.
2986 * @param pTime Where to store the time.
2987 */
2988 DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2989
2990 /** @name Exported CFGM Functions.
2991 * @{ */
2992 DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2993 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2994 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char *pszName, size_t *pcb));
2995 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
2996 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
2997 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString));
2998 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char *pszName, char *pszString, size_t cchString, const char *pszDef));
2999 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char *pszName, void *pvData, size_t cbData));
3000 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64));
3001 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char *pszName, uint64_t *pu64, uint64_t u64Def));
3002 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char *pszName, int64_t *pi64));
3003 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char *pszName, int64_t *pi64, int64_t i64Def));
3004 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32));
3005 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char *pszName, uint32_t *pu32, uint32_t u32Def));
3006 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char *pszName, int32_t *pi32));
3007 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char *pszName, int32_t *pi32, int32_t i32Def));
3008 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16));
3009 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char *pszName, uint16_t *pu16, uint16_t u16Def));
3010 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char *pszName, int16_t *pi16));
3011 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char *pszName, int16_t *pi16, int16_t i16Def));
3012 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8));
3013 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char *pszName, uint8_t *pu8, uint8_t u8Def));
3014 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char *pszName, int8_t *pi8));
3015 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char *pszName, int8_t *pi8, int8_t i8Def));
3016 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char *pszName, bool *pf));
3017 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char *pszName, bool *pf, bool fDef));
3018 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3019 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3020 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char *pszName, unsigned int *pu));
3021 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char *pszName, unsigned int *pu, unsigned int uDef));
3022 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char *pszName, signed int *pi));
3023 DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char *pszName, signed int *pi, signed int iDef));
3024 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char *pszName, void **ppv));
3025 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char *pszName, void **ppv, void *pvDef));
3026 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3027 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3028 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3029 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3030 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3031 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3032 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char *pszName, char **ppszString));
3033 DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char *pszName, char **ppszString, const char *pszDef));
3034 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3035 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3036 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3037 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3038 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3039 DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3040 DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3041 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3042 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3043 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3044 DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3045 DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3046 DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3047 DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3048 DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3049 DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3050 const char *pszValidValues, const char *pszValidNodes,
3051 const char *pszWho, uint32_t uInstance));
3052 /** @} */
3053
3054 /**
3055 * Read physical memory.
3056 *
3057 * @returns VINF_SUCCESS (for now).
3058 * @param pDevIns The device instance.
3059 * @param GCPhys Physical address start reading from.
3060 * @param pvBuf Where to put the read bits.
3061 * @param cbRead How many bytes to read.
3062 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3063 * @thread Any thread, but the call may involve the emulation thread.
3064 */
3065 DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3066
3067 /**
3068 * Write to physical memory.
3069 *
3070 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3071 * @param pDevIns The device instance.
3072 * @param GCPhys Physical address to write to.
3073 * @param pvBuf What to write.
3074 * @param cbWrite How many bytes to write.
3075 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3076 * @thread Any thread, but the call may involve the emulation thread.
3077 */
3078 DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3079
3080 /**
3081 * Requests the mapping of a guest page into ring-3.
3082 *
3083 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3084 * release it.
3085 *
3086 * This API will assume your intention is to write to the page, and will
3087 * therefore replace shared and zero pages. If you do not intend to modify the
3088 * page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3089 *
3090 * @returns VBox status code.
3091 * @retval VINF_SUCCESS on success.
3092 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3093 * backing or if the page has any active access handlers. The caller
3094 * must fall back on using PGMR3PhysWriteExternal.
3095 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3096 *
3097 * @param pDevIns The device instance.
3098 * @param GCPhys The guest physical address of the page that
3099 * should be mapped.
3100 * @param fFlags Flags reserved for future use, MBZ.
3101 * @param ppv Where to store the address corresponding to
3102 * GCPhys.
3103 * @param pLock Where to store the lock information that
3104 * pfnPhysReleasePageMappingLock needs.
3105 *
3106 * @remark Avoid calling this API from within critical sections (other than the
3107 * PGM one) because of the deadlock risk when we have to delegating the
3108 * task to an EMT.
3109 * @thread Any.
3110 */
3111 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3112 PPGMPAGEMAPLOCK pLock));
3113
3114 /**
3115 * Requests the mapping of a guest page into ring-3, external threads.
3116 *
3117 * When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3118 * release it.
3119 *
3120 * @returns VBox status code.
3121 * @retval VINF_SUCCESS on success.
3122 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3123 * backing or if the page as an active ALL access handler. The caller
3124 * must fall back on using PGMPhysRead.
3125 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3126 *
3127 * @param pDevIns The device instance.
3128 * @param GCPhys The guest physical address of the page that
3129 * should be mapped.
3130 * @param fFlags Flags reserved for future use, MBZ.
3131 * @param ppv Where to store the address corresponding to
3132 * GCPhys.
3133 * @param pLock Where to store the lock information that
3134 * pfnPhysReleasePageMappingLock needs.
3135 *
3136 * @remark Avoid calling this API from within critical sections.
3137 * @thread Any.
3138 */
3139 DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3140 void const **ppv, PPGMPAGEMAPLOCK pLock));
3141
3142 /**
3143 * Release the mapping of a guest page.
3144 *
3145 * This is the counter part of pfnPhysGCPhys2CCPtr and
3146 * pfnPhysGCPhys2CCPtrReadOnly.
3147 *
3148 * @param pDevIns The device instance.
3149 * @param pLock The lock structure initialized by the mapping
3150 * function.
3151 */
3152 DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3153
3154 /**
3155 * Read guest physical memory by virtual address.
3156 *
3157 * @param pDevIns The device instance.
3158 * @param pvDst Where to put the read bits.
3159 * @param GCVirtSrc Guest virtual address to start reading from.
3160 * @param cb How many bytes to read.
3161 * @thread The emulation thread.
3162 */
3163 DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3164
3165 /**
3166 * Write to guest physical memory by virtual address.
3167 *
3168 * @param pDevIns The device instance.
3169 * @param GCVirtDst Guest virtual address to write to.
3170 * @param pvSrc What to write.
3171 * @param cb How many bytes to write.
3172 * @thread The emulation thread.
3173 */
3174 DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3175
3176 /**
3177 * Convert a guest virtual address to a guest physical address.
3178 *
3179 * @returns VBox status code.
3180 * @param pDevIns The device instance.
3181 * @param GCPtr Guest virtual address.
3182 * @param pGCPhys Where to store the GC physical address
3183 * corresponding to GCPtr.
3184 * @thread The emulation thread.
3185 * @remark Careful with page boundaries.
3186 */
3187 DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3188
3189 /**
3190 * Checks if a GC physical address is a normal page,
3191 * i.e. not ROM, MMIO or reserved.
3192 *
3193 * @returns true if normal.
3194 * @returns false if invalid, ROM, MMIO or reserved page.
3195 * @param pDevIns The device instance.
3196 * @param GCPhys The physical address to check.
3197 */
3198 DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3199
3200 /**
3201 * Inflate or deflate a memory balloon
3202 *
3203 * @returns VBox status code.
3204 * @param pDevIns The device instance.
3205 * @param fInflate Inflate or deflate memory balloon
3206 * @param cPages Number of pages to free
3207 * @param paPhysPage Array of guest physical addresses
3208 */
3209 DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3210
3211 /**
3212 * Allocate memory which is associated with current VM instance
3213 * and automatically freed on it's destruction.
3214 *
3215 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3216 * @param pDevIns The device instance.
3217 * @param cb Number of bytes to allocate.
3218 */
3219 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3220
3221 /**
3222 * Allocate memory which is associated with current VM instance
3223 * and automatically freed on it's destruction. The memory is ZEROed.
3224 *
3225 * @returns Pointer to allocated memory. The memory is *NOT* zero-ed.
3226 * @param pDevIns The device instance.
3227 * @param cb Number of bytes to allocate.
3228 */
3229 DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3230
3231 /**
3232 * Allocating string printf.
3233 *
3234 * @returns Pointer to the string.
3235 * @param pDevIns The device instance.
3236 * @param enmTag The statistics tag.
3237 * @param pszFormat The format string.
3238 * @param va Format arguments.
3239 */
3240 DECLR3CALLBACKMEMBER(char *, pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char *pszFormat, va_list va));
3241
3242 /**
3243 * Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3244 *
3245 * @param pDevIns The device instance.
3246 * @param pv Pointer to the memory to free.
3247 */
3248 DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3249
3250 /**
3251 * Returns the physical RAM size of the VM.
3252 *
3253 * @returns RAM size in bytes.
3254 * @param pDevIns The device instance.
3255 */
3256 DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3257
3258 /**
3259 * Returns the physical RAM size of the VM below the 4GB boundary.
3260 *
3261 * @returns RAM size in bytes.
3262 * @param pDevIns The device instance.
3263 */
3264 DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3265
3266 /**
3267 * Returns the physical RAM size of the VM above the 4GB boundary.
3268 *
3269 * @returns RAM size in bytes.
3270 * @param pDevIns The device instance.
3271 */
3272 DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3273
3274 /**
3275 * Gets the VM state.
3276 *
3277 * @returns VM state.
3278 * @param pDevIns The device instance.
3279 * @thread Any thread (just keep in mind that it's volatile info).
3280 */
3281 DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3282
3283 /**
3284 * Checks if the VM was teleported and hasn't been fully resumed yet.
3285 *
3286 * @returns true / false.
3287 * @param pDevIns The device instance.
3288 * @thread Any thread.
3289 */
3290 DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3291
3292 /**
3293 * Set the VM error message
3294 *
3295 * @returns rc.
3296 * @param pDevIns The device instance.
3297 * @param rc VBox status code.
3298 * @param SRC_POS Use RT_SRC_POS.
3299 * @param pszFormat Error message format string.
3300 * @param va Error message arguments.
3301 */
3302 DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3303 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3304
3305 /**
3306 * Set the VM runtime error message
3307 *
3308 * @returns VBox status code.
3309 * @param pDevIns The device instance.
3310 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3311 * @param pszErrorId Error ID string.
3312 * @param pszFormat Error message format string.
3313 * @param va Error message arguments.
3314 */
3315 DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3316 const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3317
3318 /**
3319 * Special interface for implementing a HLT-like port on a device.
3320 *
3321 * This can be called directly from device code, provide the device is trusted
3322 * to access the VMM directly. Since we may not have an accurate register set
3323 * and the caller certainly shouldn't (device code does not access CPU
3324 * registers), this function will return when interrupts are pending regardless
3325 * of the actual EFLAGS.IF state.
3326 *
3327 * @returns VBox error status (never informational statuses).
3328 * @param pDevIns The device instance.
3329 * @param idCpu The id of the calling EMT.
3330 */
3331 DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3332
3333 /**
3334 * Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3335 *
3336 * @returns VBox error status (never informational statuses).
3337 * @param pDevIns The device instance.
3338 * @param idCpu The id of the calling EMT.
3339 */
3340 DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3341
3342 /**
3343 * Convenience wrapper for VMR3ReqCallU.
3344 *
3345 * This assumes (1) you're calling a function that returns an VBox status code
3346 * and that you do not wish to wait for it to complete.
3347 *
3348 * @returns VBox status code returned by VMR3ReqCallVU.
3349 *
3350 * @param pDevIns The device instance.
3351 * @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3352 * one of the following special values:
3353 * VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3354 * @param pfnFunction Pointer to the function to call.
3355 * @param cArgs Number of arguments following in the ellipsis.
3356 * @param Args Argument vector.
3357 *
3358 * @remarks See remarks on VMR3ReqCallVU.
3359 */
3360 DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3361
3362 /**
3363 * Convenience wrapper for VMR3ReqCallU.
3364 *
3365 * This assumes (1) you're calling a function that returns void, (2) that you
3366 * wish to wait for ever for it to return, and (3) that it's priority request
3367 * that can be safely be handled during async suspend and power off.
3368 *
3369 * @returns VBox status code of VMR3ReqCallVU.
3370 *
3371 * @param pDevIns The device instance.
3372 * @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3373 * one of the following special values:
3374 * VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3375 * @param pfnFunction Pointer to the function to call.
3376 * @param cArgs Number of arguments following in the ellipsis.
3377 * @param Args Argument vector.
3378 *
3379 * @remarks See remarks on VMR3ReqCallVU.
3380 */
3381 DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, va_list Args));
3382
3383 /**
3384 * Stops the VM and enters the debugger to look at the guest state.
3385 *
3386 * Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3387 * invoking this function directly.
3388 *
3389 * @returns VBox status code which must be passed up to the VMM.
3390 * @param pDevIns The device instance.
3391 * @param pszFile Filename of the assertion location.
3392 * @param iLine The linenumber of the assertion location.
3393 * @param pszFunction Function of the assertion location.
3394 * @param pszFormat Message. (optional)
3395 * @param args Message parameters.
3396 */
3397 DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction,
3398 const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3399
3400 /**
3401 * Register a info handler with DBGF.
3402 *
3403 * @returns VBox status code.
3404 * @param pDevIns The device instance.
3405 * @param pszName The identifier of the info.
3406 * @param pszDesc The description of the info and any arguments
3407 * the handler may take.
3408 * @param pfnHandler The handler function to be called to display the
3409 * info.
3410 */
3411 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3412
3413 /**
3414 * Register a info handler with DBGF, argv style.
3415 *
3416 * @returns VBox status code.
3417 * @param pDevIns The device instance.
3418 * @param pszName The identifier of the info.
3419 * @param pszDesc The description of the info and any arguments
3420 * the handler may take.
3421 * @param pfnHandler The handler function to be called to display the
3422 * info.
3423 */
3424 DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3425
3426 /**
3427 * Registers a set of registers for a device.
3428 *
3429 * The @a pvUser argument of the getter and setter callbacks will be
3430 * @a pDevIns. The register names will be prefixed by the device name followed
3431 * immediately by the instance number.
3432 *
3433 * @returns VBox status code.
3434 * @param pDevIns The device instance.
3435 * @param paRegisters The register descriptors.
3436 *
3437 * @remarks The device critical section is NOT entered prior to working the
3438 * callbacks registered via this helper!
3439 */
3440 DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3441
3442 /**
3443 * Gets the trace buffer handle.
3444 *
3445 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3446 * really inteded for direct usage, thus no inline wrapper function.
3447 *
3448 * @returns Trace buffer handle or NIL_RTTRACEBUF.
3449 * @param pDevIns The device instance.
3450 */
3451 DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3452
3453 /**
3454 * Report a bug check.
3455 *
3456 * @returns
3457 * @param pDevIns The device instance.
3458 * @param enmEvent The kind of BSOD event this is.
3459 * @param uBugCheck The bug check number.
3460 * @param uP1 The bug check parameter \#1.
3461 * @param uP2 The bug check parameter \#2.
3462 * @param uP3 The bug check parameter \#3.
3463 * @param uP4 The bug check parameter \#4.
3464 *
3465 * @thread EMT
3466 */
3467 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnDBGFReportBugCheck,(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
3468 uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4));
3469
3470 /**
3471 * Write core dump of the guest.
3472 *
3473 * @returns VBox status code.
3474 * @param pDevIns The device instance.
3475 * @param pszFilename The name of the file to which the guest core
3476 * dump should be written.
3477 * @param fReplaceFile Whether to replace the file or not.
3478 *
3479 * @remarks The VM may need to be suspended before calling this function in
3480 * order to truly stop all device threads and drivers. This function
3481 * only synchronizes EMTs.
3482 */
3483 DECLR3CALLBACKMEMBER(int, pfnDBGFCoreWrite,(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile));
3484
3485 /**
3486 * Gets the logger info helper.
3487 * The returned info helper will unconditionally write all output to the log.
3488 *
3489 * @returns Pointer to the logger info helper.
3490 * @param pDevIns The device instance.
3491 */
3492 DECLR3CALLBACKMEMBER(PCDBGFINFOHLP, pfnDBGFInfoLogHlp,(PPDMDEVINS pDevIns));
3493
3494 /**
3495 * Queries a 64-bit register value.
3496 *
3497 * @retval VINF_SUCCESS
3498 * @retval VERR_INVALID_VM_HANDLE
3499 * @retval VERR_INVALID_CPU_ID
3500 * @retval VERR_DBGF_REGISTER_NOT_FOUND
3501 * @retval VERR_DBGF_UNSUPPORTED_CAST
3502 * @retval VINF_DBGF_TRUNCATED_REGISTER
3503 * @retval VINF_DBGF_ZERO_EXTENDED_REGISTER
3504 *
3505 * @param pDevIns The device instance.
3506 * @param idDefCpu The default target CPU ID, VMCPUID_ANY if not
3507 * applicable. Can be OR'ed with
3508 * DBGFREG_HYPER_VMCPUID.
3509 * @param pszReg The register that's being queried. Except for
3510 * CPU registers, this must be on the form
3511 * "set.reg[.sub]".
3512 * @param pu64 Where to store the register value.
3513 */
3514 DECLR3CALLBACKMEMBER(int, pfnDBGFRegNmQueryU64,(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char *pszReg, uint64_t *pu64));
3515
3516 /**
3517 * Format a set of registers.
3518 *
3519 * This is restricted to registers from one CPU, that specified by @a idCpu.
3520 *
3521 * @returns VBox status code.
3522 * @param pDevIns The device instance.
3523 * @param idCpu The CPU ID of any CPU registers that may be
3524 * printed, pass VMCPUID_ANY if not applicable.
3525 * @param pszBuf The output buffer.
3526 * @param cbBuf The size of the output buffer.
3527 * @param pszFormat The format string. Register names are given by
3528 * %VR{name}, they take no arguments.
3529 * @param va Other format arguments.
3530 */
3531 DECLR3CALLBACKMEMBER(int, pfnDBGFRegPrintfV,(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
3532 const char *pszFormat, va_list va));
3533
3534 /**
3535 * Registers a statistics sample.
3536 *
3537 * @param pDevIns Device instance of the DMA.
3538 * @param pvSample Pointer to the sample.
3539 * @param enmType Sample type. This indicates what pvSample is
3540 * pointing at.
3541 * @param pszName Sample name, unix path style. If this does not
3542 * start with a '/', the default prefix will be
3543 * prepended, otherwise it will be used as-is.
3544 * @param enmUnit Sample unit.
3545 * @param pszDesc Sample description.
3546 */
3547 DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc));
3548
3549 /**
3550 * Same as pfnSTAMRegister except that the name is specified in a
3551 * RTStrPrintfV like fashion.
3552 *
3553 * @returns VBox status.
3554 * @param pDevIns Device instance of the DMA.
3555 * @param pvSample Pointer to the sample.
3556 * @param enmType Sample type. This indicates what pvSample is
3557 * pointing at.
3558 * @param enmVisibility Visibility type specifying whether unused
3559 * statistics should be visible or not.
3560 * @param enmUnit Sample unit.
3561 * @param pszDesc Sample description.
3562 * @param pszName Sample name format string, unix path style. If
3563 * this does not start with a '/', the default
3564 * prefix will be prepended, otherwise it will be
3565 * used as-is.
3566 * @param args Arguments to the format string.
3567 */
3568 DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3569 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3570 const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3571
3572 /**
3573 * Registers a PCI device with the default PCI bus.
3574 *
3575 * If a PDM device has more than one PCI device, they must be registered in the
3576 * order of PDMDEVINSR3::apPciDevs.
3577 *
3578 * @returns VBox status code.
3579 * @param pDevIns The device instance.
3580 * @param pPciDev The PCI device structure.
3581 * This must be kept in the instance data.
3582 * The PCI configuration must be initialized before registration.
3583 * @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3584 * PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3585 * @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3586 * PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3587 * device number (0-31). This will be ignored if
3588 * the CFGM configuration contains a PCIDeviceNo
3589 * value.
3590 * @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3591 * function number (0-7). This will be ignored if
3592 * the CFGM configuration contains a PCIFunctionNo
3593 * value.
3594 * @param pszName Device name, if NULL PDMDEVREG::szName is used.
3595 * The pointer is saved, so don't free or changed.
3596 * @note The PCI device configuration is now implicit from the apPciDevs
3597 * index, meaning that the zero'th entry is the primary one and
3598 * subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3599 */
3600 DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3601 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3602
3603 /**
3604 * Initialize MSI or MSI-X emulation support for the given PCI device.
3605 *
3606 * @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3607 *
3608 * @returns VBox status code.
3609 * @param pDevIns The device instance.
3610 * @param pPciDev The PCI device. NULL is an alias for the first
3611 * one registered.
3612 * @param pMsiReg MSI emulation registration structure.
3613 */
3614 DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3615
3616 /**
3617 * Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3618 *
3619 * @returns VBox status code.
3620 * @param pDevIns The device instance.
3621 * @param pPciDev The PCI device structure. If NULL the default
3622 * PCI device for this device instance is used.
3623 * @param iRegion The region number.
3624 * @param cbRegion Size of the region.
3625 * @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3626 * @param fFlags PDMPCIDEV_IORGN_F_XXX.
3627 * @param hHandle An I/O port, MMIO or MMIO2 handle according to
3628 * @a fFlags, UINT64_MAX if no handle is passed
3629 * (old style).
3630 * @param pfnMapUnmap Callback for doing the mapping, optional when a
3631 * handle is specified. The callback will be
3632 * invoked holding only the PDM lock. The device
3633 * lock will _not_ be taken (due to lock order).
3634 */
3635 DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3636 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3637 uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3638
3639 /**
3640 * Register PCI configuration space read/write callbacks.
3641 *
3642 * @returns VBox status code.
3643 * @param pDevIns The device instance.
3644 * @param pPciDev The PCI device structure. If NULL the default
3645 * PCI device for this device instance is used.
3646 * @param pfnRead Pointer to the user defined PCI config read function.
3647 * to call default PCI config read function. Can be NULL.
3648 * @param pfnWrite Pointer to the user defined PCI config write function.
3649 * @remarks The callbacks will be invoked holding the PDM lock. The device lock
3650 * is NOT take because that is very likely be a lock order violation.
3651 * @thread EMT(0)
3652 * @note Only callable during VM creation.
3653 * @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3654 */
3655 DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3656 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3657
3658 /**
3659 * Perform a PCI configuration space write.
3660 *
3661 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3662 *
3663 * @returns Strict VBox status code (mainly DBGFSTOP).
3664 * @param pDevIns The device instance.
3665 * @param pPciDev The PCI device which config space is being read.
3666 * @param uAddress The config space address.
3667 * @param cb The size of the read: 1, 2 or 4 bytes.
3668 * @param u32Value The value to write.
3669 */
3670 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3671 uint32_t uAddress, unsigned cb, uint32_t u32Value));
3672
3673 /**
3674 * Perform a PCI configuration space read.
3675 *
3676 * This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3677 *
3678 * @returns Strict VBox status code (mainly DBGFSTOP).
3679 * @param pDevIns The device instance.
3680 * @param pPciDev The PCI device which config space is being read.
3681 * @param uAddress The config space address.
3682 * @param cb The size of the read: 1, 2 or 4 bytes.
3683 * @param pu32Value Where to return the value.
3684 */
3685 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3686 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3687
3688 /**
3689 * Bus master physical memory read.
3690 *
3691 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3692 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3693 * @param pDevIns The device instance.
3694 * @param pPciDev The PCI device structure. If NULL the default
3695 * PCI device for this device instance is used.
3696 * @param GCPhys Physical address start reading from.
3697 * @param pvBuf Where to put the read bits.
3698 * @param cbRead How many bytes to read.
3699 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3700 * @thread Any thread, but the call may involve the emulation thread.
3701 */
3702 DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3703
3704 /**
3705 * Bus master physical memory write.
3706 *
3707 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3708 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
3709 * @param pDevIns The device instance.
3710 * @param pPciDev The PCI device structure. If NULL the default
3711 * PCI device for this device instance is used.
3712 * @param GCPhys Physical address to write to.
3713 * @param pvBuf What to write.
3714 * @param cbWrite How many bytes to write.
3715 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3716 * @thread Any thread, but the call may involve the emulation thread.
3717 */
3718 DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3719
3720 /**
3721 * Requests the mapping of a guest page into ring-3 in preparation for a bus master
3722 * physical memory write operation.
3723 *
3724 * Refer pfnPhysGCPhys2CCPtr() for further details.
3725 *
3726 * @returns VBox status code.
3727 * @param pDevIns The device instance.
3728 * @param pPciDev The PCI device structure. If NULL the default
3729 * PCI device for this device instance is used.
3730 * @param GCPhys The guest physical address of the page that should be
3731 * mapped.
3732 * @param fFlags Flags reserved for future use, MBZ.
3733 * @param ppv Where to store the address corresponding to GCPhys.
3734 * @param pLock Where to store the lock information that
3735 * pfnPhysReleasePageMappingLock needs.
3736 *
3737 * @remarks Avoid calling this API from within critical sections (other than the PGM
3738 * one) because of the deadlock risk when we have to delegating the task to
3739 * an EMT.
3740 * @thread Any.
3741 */
3742 DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3743 void **ppv, PPGMPAGEMAPLOCK pLock));
3744
3745 /**
3746 * Requests the mapping of a guest page into ring-3, external threads, in prepartion
3747 * for a bus master physical memory read operation.
3748 *
3749 * Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3750 *
3751 * @returns VBox status code.
3752 * @param pDevIns The device instance.
3753 * @param pPciDev The PCI device structure. If NULL the default
3754 * PCI device for this device instance is used.
3755 * @param GCPhys The guest physical address of the page that
3756 * should be mapped.
3757 * @param fFlags Flags reserved for future use, MBZ.
3758 * @param ppv Where to store the address corresponding to
3759 * GCPhys.
3760 * @param pLock Where to store the lock information that
3761 * pfnPhysReleasePageMappingLock needs.
3762 *
3763 * @remarks Avoid calling this API from within critical sections.
3764 * @thread Any.
3765 */
3766 DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3767 uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3768
3769 /**
3770 * Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3771 * master physical memory write operation.
3772 *
3773 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3774 * ASAP to release them.
3775 *
3776 * Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3777 *
3778 * @returns VBox status code.
3779 * @param pDevIns The device instance.
3780 * @param pPciDev The PCI device structure. If NULL the default
3781 * PCI device for this device instance is used.
3782 * @param cPages Number of pages to lock.
3783 * @param paGCPhysPages The guest physical address of the pages that
3784 * should be mapped (@a cPages entries).
3785 * @param fFlags Flags reserved for future use, MBZ.
3786 * @param papvPages Where to store the ring-3 mapping addresses
3787 * corresponding to @a paGCPhysPages.
3788 * @param paLocks Where to store the locking information that
3789 * pfnPhysBulkReleasePageMappingLock needs (@a cPages
3790 * in length).
3791 */
3792 DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3793 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3794 PPGMPAGEMAPLOCK paLocks));
3795
3796 /**
3797 * Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3798 * master physical memory read operation.
3799 *
3800 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3801 * ASAP to release them.
3802 *
3803 * Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3804 *
3805 * @returns VBox status code.
3806 * @param pDevIns The device instance.
3807 * @param pPciDev The PCI device structure. If NULL the default
3808 * PCI device for this device instance is used.
3809 * @param cPages Number of pages to lock.
3810 * @param paGCPhysPages The guest physical address of the pages that
3811 * should be mapped (@a cPages entries).
3812 * @param fFlags Flags reserved for future use, MBZ.
3813 * @param papvPages Where to store the ring-3 mapping addresses
3814 * corresponding to @a paGCPhysPages.
3815 * @param paLocks Where to store the lock information that
3816 * pfnPhysReleasePageMappingLock needs (@a cPages
3817 * in length).
3818 */
3819 DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3820 PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3821 void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3822
3823 /**
3824 * Sets the IRQ for the given PCI device.
3825 *
3826 * @param pDevIns The device instance.
3827 * @param pPciDev The PCI device structure. If NULL the default
3828 * PCI device for this device instance is used.
3829 * @param iIrq IRQ number to set.
3830 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3831 * @thread Any thread, but will involve the emulation thread.
3832 */
3833 DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3834
3835 /**
3836 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3837 * the request when not called from EMT.
3838 *
3839 * @param pDevIns The device instance.
3840 * @param pPciDev The PCI device structure. If NULL the default
3841 * PCI device for this device instance is used.
3842 * @param iIrq IRQ number to set.
3843 * @param iLevel IRQ level.
3844 * @thread Any thread, but will involve the emulation thread.
3845 */
3846 DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3847
3848 /**
3849 * Set ISA IRQ for a device.
3850 *
3851 * @param pDevIns The device instance.
3852 * @param iIrq IRQ number to set.
3853 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3854 * @thread Any thread, but will involve the emulation thread.
3855 */
3856 DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3857
3858 /**
3859 * Set the ISA IRQ for a device, but don't wait for EMT to process
3860 * the request when not called from EMT.
3861 *
3862 * @param pDevIns The device instance.
3863 * @param iIrq IRQ number to set.
3864 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3865 * @thread Any thread, but will involve the emulation thread.
3866 */
3867 DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3868
3869 /**
3870 * Attaches a driver (chain) to the device.
3871 *
3872 * The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3873 * the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3874 *
3875 * @returns VBox status code.
3876 * @param pDevIns The device instance.
3877 * @param iLun The logical unit to attach.
3878 * @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3879 * @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3880 * @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3881 * for the live of the device instance.
3882 */
3883 DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3884 PPDMIBASE *ppBaseInterface, const char *pszDesc));
3885
3886 /**
3887 * Detaches an attached driver (chain) from the device again.
3888 *
3889 * @returns VBox status code.
3890 * @param pDevIns The device instance.
3891 * @param pDrvIns The driver instance to detach.
3892 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3893 */
3894 DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3895
3896 /**
3897 * Reconfigures the driver chain for a LUN, detaching any driver currently
3898 * present there.
3899 *
3900 * Caller will have attach it, of course.
3901 *
3902 * @returns VBox status code.
3903 * @param pDevIns The device instance.
3904 * @param iLun The logical unit to reconfigure.
3905 * @param cDepth The depth of the driver chain. Determins the
3906 * size of @a papszDrivers and @a papConfigs.
3907 * @param papszDrivers The names of the drivers to configure in the
3908 * chain, first entry is the one immediately
3909 * below the device/LUN
3910 * @param papConfigs The configurations for each of the drivers
3911 * in @a papszDrivers array. NULL entries
3912 * corresponds to empty 'Config' nodes. This
3913 * function will take ownership of non-NULL
3914 * CFGM sub-trees and set the array member to
3915 * NULL, so the caller can do cleanups on
3916 * failure. This parameter is optional.
3917 * @param fFlags Reserved, MBZ.
3918 */
3919 DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3920 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags));
3921
3922 /** @name Exported PDM Queue Functions
3923 * @{ */
3924 /**
3925 * Create a queue.
3926 *
3927 * @returns VBox status code.
3928 * @param pDevIns The device instance.
3929 * @param cbItem The size of a queue item.
3930 * @param cItems The number of items in the queue.
3931 * @param cMilliesInterval The number of milliseconds between polling the queue.
3932 * If 0 then the emulation thread will be notified whenever an item arrives.
3933 * @param pfnCallback The consumer function.
3934 * @param fRZEnabled Set if the queue should work in RC and R0.
3935 * @param pszName The queue base name. The instance number will be
3936 * appended automatically.
3937 * @param phQueue Where to store the queue handle on success.
3938 * @thread EMT(0)
3939 * @remarks The device critical section will NOT be entered before calling the
3940 * callback. No locks will be held, but for now it's safe to assume
3941 * that only one EMT will do queue callbacks at any one time.
3942 */
3943 DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3944 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3945 PDMQUEUEHANDLE *phQueue));
3946
3947 DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3948 DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3949 DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3950 /** @} */
3951
3952 /** @name PDM Task
3953 * @{ */
3954 /**
3955 * Create an asynchronous ring-3 task.
3956 *
3957 * @returns VBox status code.
3958 * @param pDevIns The device instance.
3959 * @param fFlags PDMTASK_F_XXX
3960 * @param pszName The function name or similar. Used for statistics,
3961 * so no slashes.
3962 * @param pfnCallback The task function.
3963 * @param pvUser User argument for the task function.
3964 * @param phTask Where to return the task handle.
3965 * @thread EMT(0)
3966 */
3967 DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3968 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask));
3969 /**
3970 * Triggers the running the given task.
3971 *
3972 * @returns VBox status code.
3973 * @retval VINF_ALREADY_POSTED is the task is already pending.
3974 * @param pDevIns The device instance.
3975 * @param hTask The task to trigger.
3976 * @thread Any thread.
3977 */
3978 DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3979 /** @} */
3980
3981 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
3982 * These semaphores can be signalled from ring-0.
3983 * @{ */
3984 /** @sa SUPSemEventCreate */
3985 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3986 /** @sa SUPSemEventClose */
3987 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3988 /** @sa SUPSemEventSignal */
3989 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3990 /** @sa SUPSemEventWaitNoResume */
3991 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3992 /** @sa SUPSemEventWaitNsAbsIntr */
3993 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3994 /** @sa SUPSemEventWaitNsRelIntr */
3995 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3996 /** @sa SUPSemEventGetResolution */
3997 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3998 /** @} */
3999
4000 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
4001 * These semaphores can be signalled from ring-0.
4002 * @{ */
4003 /** @sa SUPSemEventMultiCreate */
4004 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
4005 /** @sa SUPSemEventMultiClose */
4006 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4007 /** @sa SUPSemEventMultiSignal */
4008 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4009 /** @sa SUPSemEventMultiReset */
4010 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4011 /** @sa SUPSemEventMultiWaitNoResume */
4012 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
4013 /** @sa SUPSemEventMultiWaitNsAbsIntr */
4014 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
4015 /** @sa SUPSemEventMultiWaitNsRelIntr */
4016 DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
4017 /** @sa SUPSemEventMultiGetResolution */
4018 DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
4019 /** @} */
4020
4021 /**
4022 * Initializes a PDM critical section.
4023 *
4024 * The PDM critical sections are derived from the IPRT critical sections, but
4025 * works in RC and R0 as well.
4026 *
4027 * @returns VBox status code.
4028 * @param pDevIns The device instance.
4029 * @param pCritSect Pointer to the critical section.
4030 * @param SRC_POS Use RT_SRC_POS.
4031 * @param pszNameFmt Format string for naming the critical section.
4032 * For statistics and lock validation.
4033 * @param va Arguments for the format string.
4034 */
4035 DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
4036 const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4037
4038 /**
4039 * Gets the NOP critical section.
4040 *
4041 * @returns The ring-3 address of the NOP critical section.
4042 * @param pDevIns The device instance.
4043 */
4044 DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4045
4046 /**
4047 * Changes the device level critical section from the automatically created
4048 * default to one desired by the device constructor.
4049 *
4050 * For ring-0 and raw-mode capable devices, the call must be repeated in each of
4051 * the additional contexts.
4052 *
4053 * @returns VBox status code.
4054 * @param pDevIns The device instance.
4055 * @param pCritSect The critical section to use. NULL is not
4056 * valid, instead use the NOP critical
4057 * section.
4058 */
4059 DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4060
4061 /** @name Exported PDM Critical Section Functions
4062 * @{ */
4063 DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4064 DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4065 DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4066 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4067 DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4068 DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4069 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4070 DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4071 DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4072 DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4073 DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
4074 DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4075 /** @} */
4076
4077 /** @name Exported PDM Read/Write Critical Section Functions
4078 * @{ */
4079 DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
4080 const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4081 DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4082
4083 DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4084 DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4085 DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4086 DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4087 DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4088
4089 DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4090 DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4091 DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4092 DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4093 DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4094
4095 DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4096 DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4097 DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4098 DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4099 DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4100 DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4101 /** @} */
4102
4103 /**
4104 * Creates a PDM thread.
4105 *
4106 * This differs from the RTThreadCreate() API in that PDM takes care of suspending,
4107 * resuming, and destroying the thread as the VM state changes.
4108 *
4109 * @returns VBox status code.
4110 * @param pDevIns The device instance.
4111 * @param ppThread Where to store the thread 'handle'.
4112 * @param pvUser The user argument to the thread function.
4113 * @param pfnThread The thread function.
4114 * @param pfnWakeup The wakup callback. This is called on the EMT
4115 * thread when a state change is pending.
4116 * @param cbStack See RTThreadCreate.
4117 * @param enmType See RTThreadCreate.
4118 * @param pszName See RTThreadCreate.
4119 * @remarks The device critical section will NOT be entered prior to invoking
4120 * the function pointers.
4121 */
4122 DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
4123 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
4124
4125 /** @name Exported PDM Thread Functions
4126 * @{ */
4127 DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
4128 DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
4129 DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
4130 DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
4131 DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
4132 DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
4133 /** @} */
4134
4135 /**
4136 * Set up asynchronous handling of a suspend, reset or power off notification.
4137 *
4138 * This shall only be called when getting the notification. It must be called
4139 * for each one.
4140 *
4141 * @returns VBox status code.
4142 * @param pDevIns The device instance.
4143 * @param pfnAsyncNotify The callback.
4144 * @thread EMT(0)
4145 * @remarks The caller will enter the device critical section prior to invoking
4146 * the callback.
4147 */
4148 DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4149
4150 /**
4151 * Notify EMT(0) that the device has completed the asynchronous notification
4152 * handling.
4153 *
4154 * This can be called at any time, spurious calls will simply be ignored.
4155 *
4156 * @param pDevIns The device instance.
4157 * @thread Any
4158 */
4159 DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4160
4161 /**
4162 * Register the RTC device.
4163 *
4164 * @returns VBox status code.
4165 * @param pDevIns The device instance.
4166 * @param pRtcReg Pointer to a RTC registration structure.
4167 * @param ppRtcHlp Where to store the pointer to the helper
4168 * functions.
4169 */
4170 DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4171
4172 /**
4173 * Register a PCI Bus.
4174 *
4175 * @returns VBox status code, but the positive values 0..31 are used to indicate
4176 * bus number rather than informational status codes.
4177 * @param pDevIns The device instance.
4178 * @param pPciBusReg Pointer to PCI bus registration structure.
4179 * @param ppPciHlp Where to store the pointer to the PCI Bus
4180 * helpers.
4181 * @param piBus Where to return the PDM bus number. Optional.
4182 */
4183 DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4184 PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus));
4185
4186 /**
4187 * Register the IOMMU device.
4188 *
4189 * @returns VBox status code.
4190 * @param pDevIns The device instance.
4191 * @param pIommuReg Pointer to a IOMMU registration structure.
4192 * @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4193 * helpers.
4194 * @param pidxIommu Where to return the IOMMU index. Optional.
4195 */
4196 DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4197 uint32_t *pidxIommu));
4198
4199 /**
4200 * Register the PIC device.
4201 *
4202 * @returns VBox status code.
4203 * @param pDevIns The device instance.
4204 * @param pPicReg Pointer to a PIC registration structure.
4205 * @param ppPicHlp Where to store the pointer to the ring-3 PIC
4206 * helpers.
4207 * @sa PDMDevHlpPICSetUpContext
4208 */
4209 DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4210
4211 /**
4212 * Register the APIC device.
4213 *
4214 * @returns VBox status code.
4215 * @param pDevIns The device instance.
4216 */
4217 DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4218
4219 /**
4220 * Register the I/O APIC device.
4221 *
4222 * @returns VBox status code.
4223 * @param pDevIns The device instance.
4224 * @param pIoApicReg Pointer to a I/O APIC registration structure.
4225 * @param ppIoApicHlp Where to store the pointer to the IOAPIC
4226 * helpers.
4227 */
4228 DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4229
4230 /**
4231 * Register the HPET device.
4232 *
4233 * @returns VBox status code.
4234 * @param pDevIns The device instance.
4235 * @param pHpetReg Pointer to a HPET registration structure.
4236 * @param ppHpetHlpR3 Where to store the pointer to the HPET
4237 * helpers.
4238 */
4239 DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4240
4241 /**
4242 * Register a raw PCI device.
4243 *
4244 * @returns VBox status code.
4245 * @param pDevIns The device instance.
4246 * @param pPciRawReg Pointer to a raw PCI registration structure.
4247 * @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4248 * device helpers.
4249 */
4250 DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4251
4252 /**
4253 * Register the DMA device.
4254 *
4255 * @returns VBox status code.
4256 * @param pDevIns The device instance.
4257 * @param pDmacReg Pointer to a DMAC registration structure.
4258 * @param ppDmacHlp Where to store the pointer to the DMA helpers.
4259 */
4260 DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4261
4262 /**
4263 * Register transfer function for DMA channel.
4264 *
4265 * @returns VBox status code.
4266 * @param pDevIns The device instance.
4267 * @param uChannel Channel number.
4268 * @param pfnTransferHandler Device specific transfer callback function.
4269 * @param pvUser User pointer to pass to the callback.
4270 * @thread EMT
4271 */
4272 DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4273
4274 /**
4275 * Read memory.
4276 *
4277 * @returns VBox status code.
4278 * @param pDevIns The device instance.
4279 * @param uChannel Channel number.
4280 * @param pvBuffer Pointer to target buffer.
4281 * @param off DMA position.
4282 * @param cbBlock Block size.
4283 * @param pcbRead Where to store the number of bytes which was
4284 * read. optional.
4285 * @thread EMT
4286 */
4287 DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead));
4288
4289 /**
4290 * Write memory.
4291 *
4292 * @returns VBox status code.
4293 * @param pDevIns The device instance.
4294 * @param uChannel Channel number.
4295 * @param pvBuffer Memory to write.
4296 * @param off DMA position.
4297 * @param cbBlock Block size.
4298 * @param pcbWritten Where to store the number of bytes which was
4299 * written. optional.
4300 * @thread EMT
4301 */
4302 DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten));
4303
4304 /**
4305 * Set the DREQ line.
4306 *
4307 * @returns VBox status code.
4308 * @param pDevIns Device instance.
4309 * @param uChannel Channel number.
4310 * @param uLevel Level of the line.
4311 * @thread EMT
4312 */
4313 DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4314
4315 /**
4316 * Get channel mode.
4317 *
4318 * @returns Channel mode. See specs.
4319 * @param pDevIns The device instance.
4320 * @param uChannel Channel number.
4321 * @thread EMT
4322 */
4323 DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4324
4325 /**
4326 * Schedule DMA execution.
4327 *
4328 * @param pDevIns The device instance.
4329 * @thread Any thread.
4330 */
4331 DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4332
4333 /**
4334 * Write CMOS value and update the checksum(s).
4335 *
4336 * @returns VBox status code.
4337 * @param pDevIns The device instance.
4338 * @param iReg The CMOS register index.
4339 * @param u8Value The CMOS register value.
4340 * @thread EMT
4341 */
4342 DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4343
4344 /**
4345 * Read CMOS value.
4346 *
4347 * @returns VBox status code.
4348 * @param pDevIns The device instance.
4349 * @param iReg The CMOS register index.
4350 * @param pu8Value Where to store the CMOS register value.
4351 * @thread EMT
4352 */
4353 DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4354
4355 /**
4356 * Assert that the current thread is the emulation thread.
4357 *
4358 * @returns True if correct.
4359 * @returns False if wrong.
4360 * @param pDevIns The device instance.
4361 * @param pszFile Filename of the assertion location.
4362 * @param iLine The linenumber of the assertion location.
4363 * @param pszFunction Function of the assertion location.
4364 */
4365 DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
4366
4367 /**
4368 * Assert that the current thread is NOT the emulation thread.
4369 *
4370 * @returns True if correct.
4371 * @returns False if wrong.
4372 * @param pDevIns The device instance.
4373 * @param pszFile Filename of the assertion location.
4374 * @param iLine The linenumber of the assertion location.
4375 * @param pszFunction Function of the assertion location.
4376 */
4377 DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction));
4378
4379 /**
4380 * Resolves the symbol for a raw-mode context interface.
4381 *
4382 * @returns VBox status code.
4383 * @param pDevIns The device instance.
4384 * @param pvInterface The interface structure.
4385 * @param cbInterface The size of the interface structure.
4386 * @param pszSymPrefix What to prefix the symbols in the list with
4387 * before resolving them. This must start with
4388 * 'dev' and contain the driver name.
4389 * @param pszSymList List of symbols corresponding to the interface.
4390 * There is generally a there is generally a define
4391 * holding this list associated with the interface
4392 * definition (INTERFACE_SYM_LIST). For more
4393 * details see PDMR3LdrGetInterfaceSymbols.
4394 * @thread EMT
4395 */
4396 DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4397 const char *pszSymPrefix, const char *pszSymList));
4398
4399 /**
4400 * Resolves the symbol for a ring-0 context interface.
4401 *
4402 * @returns VBox status code.
4403 * @param pDevIns The device instance.
4404 * @param pvInterface The interface structure.
4405 * @param cbInterface The size of the interface structure.
4406 * @param pszSymPrefix What to prefix the symbols in the list with
4407 * before resolving them. This must start with
4408 * 'dev' and contain the driver name.
4409 * @param pszSymList List of symbols corresponding to the interface.
4410 * There is generally a there is generally a define
4411 * holding this list associated with the interface
4412 * definition (INTERFACE_SYM_LIST). For more
4413 * details see PDMR3LdrGetInterfaceSymbols.
4414 * @thread EMT
4415 */
4416 DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4417 const char *pszSymPrefix, const char *pszSymList));
4418
4419 /**
4420 * Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4421 *
4422 * @returns VBox status code.
4423 * @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4424 * @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4425 *
4426 * @param pDevIns The device instance.
4427 * @param uOperation The operation to perform.
4428 * @param u64Arg 64-bit integer argument.
4429 * @thread EMT
4430 */
4431 DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4432
4433 /**
4434 * Gets the reason for the most recent VM suspend.
4435 *
4436 * @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4437 * suspend has been made or if the pDevIns is invalid.
4438 * @param pDevIns The device instance.
4439 */
4440 DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4441
4442 /**
4443 * Gets the reason for the most recent VM resume.
4444 *
4445 * @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4446 * resume has been made or if the pDevIns is invalid.
4447 * @param pDevIns The device instance.
4448 */
4449 DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4450
4451 /**
4452 * Requests the mapping of multiple guest page into ring-3.
4453 *
4454 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4455 * ASAP to release them.
4456 *
4457 * This API will assume your intention is to write to the pages, and will
4458 * therefore replace shared and zero pages. If you do not intend to modify the
4459 * pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4460 *
4461 * @returns VBox status code.
4462 * @retval VINF_SUCCESS on success.
4463 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4464 * backing or if any of the pages the page has any active access
4465 * handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4466 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4467 * an invalid physical address.
4468 *
4469 * @param pDevIns The device instance.
4470 * @param cPages Number of pages to lock.
4471 * @param paGCPhysPages The guest physical address of the pages that
4472 * should be mapped (@a cPages entries).
4473 * @param fFlags Flags reserved for future use, MBZ.
4474 * @param papvPages Where to store the ring-3 mapping addresses
4475 * corresponding to @a paGCPhysPages.
4476 * @param paLocks Where to store the locking information that
4477 * pfnPhysBulkReleasePageMappingLock needs (@a cPages
4478 * in length).
4479 *
4480 * @remark Avoid calling this API from within critical sections (other than the
4481 * PGM one) because of the deadlock risk when we have to delegating the
4482 * task to an EMT.
4483 * @thread Any.
4484 * @since 6.0.6
4485 */
4486 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4487 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4488
4489 /**
4490 * Requests the mapping of multiple guest page into ring-3, for reading only.
4491 *
4492 * When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4493 * ASAP to release them.
4494 *
4495 * @returns VBox status code.
4496 * @retval VINF_SUCCESS on success.
4497 * @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4498 * backing or if any of the pages the page has an active ALL access
4499 * handler. The caller must fall back on using PGMR3PhysWriteExternal.
4500 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4501 * an invalid physical address.
4502 *
4503 * @param pDevIns The device instance.
4504 * @param cPages Number of pages to lock.
4505 * @param paGCPhysPages The guest physical address of the pages that
4506 * should be mapped (@a cPages entries).
4507 * @param fFlags Flags reserved for future use, MBZ.
4508 * @param papvPages Where to store the ring-3 mapping addresses
4509 * corresponding to @a paGCPhysPages.
4510 * @param paLocks Where to store the lock information that
4511 * pfnPhysReleasePageMappingLock needs (@a cPages
4512 * in length).
4513 *
4514 * @remark Avoid calling this API from within critical sections.
4515 * @thread Any.
4516 * @since 6.0.6
4517 */
4518 DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4519 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4520
4521 /**
4522 * Release the mappings of multiple guest pages.
4523 *
4524 * This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4525 * pfnPhysBulkGCPhys2CCPtrReadOnly.
4526 *
4527 * @param pDevIns The device instance.
4528 * @param cPages Number of pages to unlock.
4529 * @param paLocks The lock structures initialized by the mapping
4530 * function (@a cPages in length).
4531 * @thread Any.
4532 * @since 6.0.6
4533 */
4534 DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4535
4536 /**
4537 * Returns the micro architecture used for the guest.
4538 *
4539 * @returns CPU micro architecture enum.
4540 * @param pDevIns The device instance.
4541 */
4542 DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4543
4544 /**
4545 * Get the number of physical and linear address bits supported by the guest.
4546 *
4547 * @param pDevIns The device instance.
4548 * @param pcPhysAddrWidth Where to store the number of physical address bits
4549 * supported by the guest.
4550 * @param pcLinearAddrWidth Where to store the number of linear address bits
4551 * supported by the guest.
4552 */
4553 DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4554 uint8_t *pcLinearAddrWidth));
4555
4556 /**
4557 * Gets the scalable bus frequency.
4558 *
4559 * The bus frequency is used as a base in several MSRs that gives the CPU and
4560 * other frequency ratios.
4561 *
4562 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
4563 * @param pDevIns The device instance.
4564 */
4565 DECLR3CALLBACKMEMBER(uint64_t, pfnCpuGetGuestScalableBusFrequency,(PPDMDEVINS pDevIns));
4566
4567 /** Space reserved for future members.
4568 * @{ */
4569 /**
4570 * Deregister zero or more samples given their name prefix.
4571 *
4572 * @returns VBox status code.
4573 * @param pDevIns The device instance.
4574 * @param pszPrefix The name prefix of the samples to remove. If this does
4575 * not start with a '/', the default prefix will be
4576 * prepended, otherwise it will be used as-is.
4577 */
4578 DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4579 DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4580 DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4581 DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4582 DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4583 DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4584 DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4585 DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4586 DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4587 DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4588 /** @} */
4589
4590
4591 /** API available to trusted devices only.
4592 *
4593 * These APIs are providing unrestricted access to the guest and the VM,
4594 * or they are interacting intimately with PDM.
4595 *
4596 * @{
4597 */
4598
4599 /**
4600 * Gets the user mode VM handle. Restricted API.
4601 *
4602 * @returns User mode VM Handle.
4603 * @param pDevIns The device instance.
4604 */
4605 DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4606
4607 /**
4608 * Gets the global VM handle. Restricted API.
4609 *
4610 * @returns VM Handle.
4611 * @param pDevIns The device instance.
4612 */
4613 DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4614
4615 /**
4616 * Gets the VMCPU handle. Restricted API.
4617 *
4618 * @returns VMCPU Handle.
4619 * @param pDevIns The device instance.
4620 */
4621 DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4622
4623 /**
4624 * The the VM CPU ID of the current thread (restricted API).
4625 *
4626 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4627 * @param pDevIns The device instance.
4628 */
4629 DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4630
4631 /**
4632 * Registers the VMM device heap or notifies about mapping/unmapping.
4633 *
4634 * This interface serves three purposes:
4635 *
4636 * -# Register the VMM device heap during device construction
4637 * for the HM to use.
4638 * -# Notify PDM/HM that it's mapped into guest address
4639 * space (i.e. usable).
4640 * -# Notify PDM/HM that it is being unmapped from the guest
4641 * address space (i.e. not usable).
4642 *
4643 * @returns VBox status code.
4644 * @param pDevIns The device instance.
4645 * @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4646 * not mapped.
4647 * @param pvHeap Ring 3 heap pointer.
4648 * @param cbHeap Size of the heap.
4649 * @thread EMT.
4650 */
4651 DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4652
4653 /**
4654 * Registers the firmware (BIOS, EFI) device with PDM.
4655 *
4656 * The firmware provides a callback table and gets a special PDM helper table.
4657 * There can only be one firmware device for a VM.
4658 *
4659 * @returns VBox status code.
4660 * @param pDevIns The device instance.
4661 * @param pFwReg Firmware registration structure.
4662 * @param ppFwHlp Where to return the firmware helper structure.
4663 * @remarks Only valid during device construction.
4664 * @thread EMT(0)
4665 */
4666 DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4667
4668 /**
4669 * Resets the VM.
4670 *
4671 * @returns The appropriate VBox status code to pass around on reset.
4672 * @param pDevIns The device instance.
4673 * @param fFlags PDMVMRESET_F_XXX flags.
4674 * @thread The emulation thread.
4675 */
4676 DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4677
4678 /**
4679 * Suspends the VM.
4680 *
4681 * @returns The appropriate VBox status code to pass around on suspend.
4682 * @param pDevIns The device instance.
4683 * @thread The emulation thread.
4684 */
4685 DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4686
4687 /**
4688 * Suspends, saves and powers off the VM.
4689 *
4690 * @returns The appropriate VBox status code to pass around.
4691 * @param pDevIns The device instance.
4692 * @thread An emulation thread.
4693 */
4694 DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4695
4696 /**
4697 * Power off the VM.
4698 *
4699 * @returns The appropriate VBox status code to pass around on power off.
4700 * @param pDevIns The device instance.
4701 * @thread The emulation thread.
4702 */
4703 DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4704
4705 /**
4706 * Checks if the Gate A20 is enabled or not.
4707 *
4708 * @returns true if A20 is enabled.
4709 * @returns false if A20 is disabled.
4710 * @param pDevIns The device instance.
4711 * @thread The emulation thread.
4712 */
4713 DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4714
4715 /**
4716 * Enables or disables the Gate A20.
4717 *
4718 * @param pDevIns The device instance.
4719 * @param fEnable Set this flag to enable the Gate A20; clear it
4720 * to disable.
4721 * @thread The emulation thread.
4722 */
4723 DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4724
4725 /**
4726 * Get the specified CPUID leaf for the virtual CPU associated with the calling
4727 * thread.
4728 *
4729 * @param pDevIns The device instance.
4730 * @param iLeaf The CPUID leaf to get.
4731 * @param pEax Where to store the EAX value.
4732 * @param pEbx Where to store the EBX value.
4733 * @param pEcx Where to store the ECX value.
4734 * @param pEdx Where to store the EDX value.
4735 * @thread EMT.
4736 */
4737 DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx));
4738
4739 /**
4740 * Get the current virtual clock time in a VM. The clock frequency must be
4741 * queried separately.
4742 *
4743 * @returns Current clock time.
4744 * @param pDevIns The device instance.
4745 */
4746 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4747
4748 /**
4749 * Get the frequency of the virtual clock.
4750 *
4751 * @returns The clock frequency (not variable at run-time).
4752 * @param pDevIns The device instance.
4753 */
4754 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4755
4756 /**
4757 * Get the current virtual clock time in a VM, in nanoseconds.
4758 *
4759 * @returns Current clock time (in ns).
4760 * @param pDevIns The device instance.
4761 */
4762 DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4763
4764 /**
4765 * Get the timestamp frequency.
4766 *
4767 * @returns Number of ticks per second.
4768 * @param pDevIns The device instance.
4769 */
4770 DECLR3CALLBACKMEMBER(uint64_t, pfnTMCpuTicksPerSecond,(PPDMDEVINS pDevIns));
4771
4772 /**
4773 * Gets the support driver session.
4774 *
4775 * This is intended for working with the semaphore API.
4776 *
4777 * @returns Support driver session handle.
4778 * @param pDevIns The device instance.
4779 */
4780 DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4781
4782 /**
4783 * Queries a generic object from the VMM user.
4784 *
4785 * @returns Pointer to the object if found, NULL if not.
4786 * @param pDevIns The device instance.
4787 * @param pUuid The UUID of what's being queried. The UUIDs and
4788 * the usage conventions are defined by the user.
4789 *
4790 * @note It is strictly forbidden to call this internally in VBox! This
4791 * interface is exclusively for hacks in externally developed devices.
4792 */
4793 DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4794
4795 /**
4796 * Register a physical page access handler type.
4797 *
4798 * @returns VBox status code.
4799 * @param pDevIns The device instance.
4800 * @param enmKind The kind of access handler.
4801 * @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4802 * @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4803 * handler should be called.
4804 * @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4805 * ring-3 handler should be called.
4806 * @param pszHandlerRC The name of the raw-mode context handler, NULL if
4807 * the ring-3 handler should be called.
4808 * @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4809 * if the ring-3 handler should be called.
4810 * @param pszDesc The type description.
4811 * @param phType Where to return the type handle (cross context
4812 * safe).
4813 */
4814 DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4815 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4816 const char *pszHandlerR0, const char *pszPfHandlerR0,
4817 const char *pszHandlerRC, const char *pszPfHandlerRC,
4818 const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4819
4820 /**
4821 * Register a access handler for a physical range.
4822 *
4823 * @returns VBox status code.
4824 * @retval VINF_SUCCESS when successfully installed.
4825 * @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4826 * the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4827 * flagged together with a pool clearing.
4828 * @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4829 * one. A debug assertion is raised.
4830 *
4831 * @param pDevIns The device instance.
4832 * @param GCPhys Start physical address.
4833 * @param GCPhysLast Last physical address. (inclusive)
4834 * @param hType The handler type registration handle.
4835 * @param pvUserR3 User argument to the R3 handler.
4836 * @param pvUserR0 User argument to the R0 handler.
4837 * @param pvUserRC User argument to the RC handler. This can be a value
4838 * less that 0x10000 or a (non-null) pointer that is
4839 * automatically relocated.
4840 * @param pszDesc Description of this handler. If NULL, the type
4841 * description will be used instead.
4842 */
4843 DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4844 PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4845 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc));
4846
4847 /**
4848 * Deregister a physical page access handler.
4849 *
4850 * @returns VBox status code.
4851 * @param pDevIns The device instance.
4852 * @param GCPhys Start physical address.
4853 */
4854 DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4855
4856 /**
4857 * Temporarily turns off the access monitoring of a page within a monitored
4858 * physical write/all page access handler region.
4859 *
4860 * Use this when no further \#PFs are required for that page. Be aware that
4861 * a page directory sync might reset the flags, and turn on access monitoring
4862 * for the page.
4863 *
4864 * The caller must do required page table modifications.
4865 *
4866 * @returns VBox status code.
4867 * @param pDevIns The device instance.
4868 * @param GCPhys The start address of the access handler. This
4869 * must be a fully page aligned range or we risk
4870 * messing up other handlers installed for the
4871 * start and end pages.
4872 * @param GCPhysPage The physical address of the page to turn off
4873 * access monitoring for.
4874 */
4875 DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4876
4877 /**
4878 * Resets any modifications to individual pages in a physical page access
4879 * handler region.
4880 *
4881 * This is used in pair with PGMHandlerPhysicalPageTempOff(),
4882 * PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4883 *
4884 * @returns VBox status code.
4885 * @param pDevIns The device instance.
4886 * @param GCPhys The start address of the handler regions, i.e. what you
4887 * passed to PGMR3HandlerPhysicalRegister(),
4888 * PGMHandlerPhysicalRegisterEx() or
4889 * PGMHandlerPhysicalModify().
4890 */
4891 DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4892
4893 /**
4894 * Registers the guest memory range that can be used for patching.
4895 *
4896 * @returns VBox status code.
4897 * @param pDevIns The device instance.
4898 * @param GCPtrPatchMem Patch memory range.
4899 * @param cbPatchMem Size of the memory range.
4900 */
4901 DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4902
4903 /**
4904 * Deregisters the guest memory range that can be used for patching.
4905 *
4906 * @returns VBox status code.
4907 * @param pDevIns The device instance.
4908 * @param GCPtrPatchMem Patch memory range.
4909 * @param cbPatchMem Size of the memory range.
4910 */
4911 DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4912
4913 /**
4914 * Registers a new shared module for the VM
4915 *
4916 * @returns VBox status code.
4917 * @param pDevIns The device instance.
4918 * @param enmGuestOS Guest OS type.
4919 * @param pszModuleName Module name.
4920 * @param pszVersion Module version.
4921 * @param GCBaseAddr Module base address.
4922 * @param cbModule Module size.
4923 * @param cRegions Number of shared region descriptors.
4924 * @param paRegions Shared region(s).
4925 */
4926 DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char *pszModuleName, char *pszVersion,
4927 RTGCPTR GCBaseAddr, uint32_t cbModule,
4928 uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4929
4930 /**
4931 * Unregisters a shared module for the VM
4932 *
4933 * @returns VBox status code.
4934 * @param pDevIns The device instance.
4935 * @param pszModuleName Module name.
4936 * @param pszVersion Module version.
4937 * @param GCBaseAddr Module base address.
4938 * @param cbModule Module size.
4939 */
4940 DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char *pszModuleName, char *pszVersion,
4941 RTGCPTR GCBaseAddr, uint32_t cbModule));
4942
4943 /**
4944 * Query the state of a page in a shared module
4945 *
4946 * @returns VBox status code.
4947 * @param pDevIns The device instance.
4948 * @param GCPtrPage Page address.
4949 * @param pfShared Shared status (out).
4950 * @param pfPageFlags Page flags (out).
4951 */
4952 DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared, uint64_t *pfPageFlags));
4953
4954 /**
4955 * Check all registered modules for changes.
4956 *
4957 * @returns VBox status code.
4958 * @param pDevIns The device instance.
4959 */
4960 DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
4961
4962 /**
4963 * Query the interface of the top level driver on a LUN.
4964 *
4965 * @returns VBox status code.
4966 * @param pDevIns The device instance.
4967 * @param pszDevice Device name.
4968 * @param iInstance Device instance.
4969 * @param iLun The Logical Unit to obtain the interface of.
4970 * @param ppBase Where to store the base interface pointer.
4971 *
4972 * @remark We're not doing any locking ATM, so don't try call this at times when the
4973 * device chain is known to be updated.
4974 */
4975 DECLR3CALLBACKMEMBER(int, pfnQueryLun,(PPDMDEVINS pDevIns, const char *pszDevice, unsigned iInstance, unsigned iLun, PPPDMIBASE ppBase));
4976
4977 /**
4978 * Registers the GIM device with VMM.
4979 *
4980 * @param pDevIns Pointer to the GIM device instance.
4981 * @param pDbg Pointer to the GIM device debug structure, can be
4982 * NULL.
4983 */
4984 DECLR3CALLBACKMEMBER(void, pfnGIMDeviceRegister,(PPDMDEVINS pDevIns, PGIMDEBUG pDbg));
4985
4986 /**
4987 * Gets debug setup specified by the provider.
4988 *
4989 * @returns VBox status code.
4990 * @param pDevIns Pointer to the GIM device instance.
4991 * @param pDbgSetup Where to store the debug setup details.
4992 */
4993 DECLR3CALLBACKMEMBER(int, pfnGIMGetDebugSetup,(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup));
4994
4995 /**
4996 * Returns the array of MMIO2 regions that are expected to be registered and
4997 * later mapped into the guest-physical address space for the GIM provider
4998 * configured for the VM.
4999 *
5000 * @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
5001 * @param pDevIns Pointer to the GIM device instance.
5002 * @param pcRegions Where to store the number of items in the array.
5003 *
5004 * @remarks The caller does not own and therefore must -NOT- try to free the
5005 * returned pointer.
5006 */
5007 DECLR3CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
5008
5009 /** @} */
5010
5011 /** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
5012 uint32_t u32TheEnd;
5013} PDMDEVHLPR3;
5014#endif /* !IN_RING3 || DOXYGEN_RUNNING */
5015/** Pointer to the R3 PDM Device API. */
5016typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
5017/** Pointer to the R3 PDM Device API, const variant. */
5018typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
5019
5020
5021/**
5022 * PDM Device API - RC Variant.
5023 */
5024typedef struct PDMDEVHLPRC
5025{
5026 /** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
5027 uint32_t u32Version;
5028
5029 /**
5030 * Sets up raw-mode context callback handlers for an I/O port range.
5031 *
5032 * The range must have been registered in ring-3 first using
5033 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5034 *
5035 * @returns VBox status.
5036 * @param pDevIns The device instance to register the ports with.
5037 * @param hIoPorts The I/O port range handle.
5038 * @param pfnOut Pointer to function which is gonna handle OUT
5039 * operations. Optional.
5040 * @param pfnIn Pointer to function which is gonna handle IN operations.
5041 * Optional.
5042 * @param pfnOutStr Pointer to function which is gonna handle string OUT
5043 * operations. Optional.
5044 * @param pfnInStr Pointer to function which is gonna handle string IN
5045 * operations. Optional.
5046 * @param pvUser User argument to pass to the callbacks.
5047 *
5048 * @remarks Caller enters the device critical section prior to invoking the
5049 * registered callback methods.
5050 *
5051 * @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
5052 * PDMDevHlpIoPortUnmap.
5053 */
5054 DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5055 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5056 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5057 void *pvUser));
5058
5059 /**
5060 * Sets up raw-mode context callback handlers for an MMIO region.
5061 *
5062 * The region must have been registered in ring-3 first using
5063 * PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
5064 *
5065 * @returns VBox status.
5066 * @param pDevIns The device instance to register the ports with.
5067 * @param hRegion The MMIO region handle.
5068 * @param pfnWrite Pointer to function which is gonna handle Write
5069 * operations.
5070 * @param pfnRead Pointer to function which is gonna handle Read
5071 * operations.
5072 * @param pfnFill Pointer to function which is gonna handle Fill/memset
5073 * operations. (optional)
5074 * @param pvUser User argument to pass to the callbacks.
5075 *
5076 * @remarks Caller enters the device critical section prior to invoking the
5077 * registered callback methods.
5078 *
5079 * @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
5080 * PDMDevHlpMmioUnmap.
5081 */
5082 DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5083 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5084
5085 /**
5086 * Sets up a raw-mode mapping for an MMIO2 region.
5087 *
5088 * The region must have been created in ring-3 first using
5089 * PDMDevHlpMmio2Create().
5090 *
5091 * @returns VBox status.
5092 * @param pDevIns The device instance to register the ports with.
5093 * @param hRegion The MMIO2 region handle.
5094 * @param offSub Start of what to map into raw-mode. Must be page aligned.
5095 * @param cbSub Number of bytes to map into raw-mode. Must be page
5096 * aligned. Zero is an alias for everything.
5097 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
5098 * @thread EMT(0)
5099 * @note Only available at VM creation time.
5100 *
5101 * @sa PDMDevHlpMmio2Create().
5102 */
5103 DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
5104 size_t offSub, size_t cbSub, void **ppvMapping));
5105
5106 /**
5107 * Bus master physical memory read from the given PCI device.
5108 *
5109 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
5110 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
5111 * @param pDevIns The device instance.
5112 * @param pPciDev The PCI device structure. If NULL the default
5113 * PCI device for this device instance is used.
5114 * @param GCPhys Physical address start reading from.
5115 * @param pvBuf Where to put the read bits.
5116 * @param cbRead How many bytes to read.
5117 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5118 * @thread Any thread, but the call may involve the emulation thread.
5119 */
5120 DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5121 void *pvBuf, size_t cbRead, uint32_t fFlags));
5122
5123 /**
5124 * Bus master physical memory write from the given PCI device.
5125 *
5126 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
5127 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
5128 * @param pDevIns The device instance.
5129 * @param pPciDev The PCI device structure. If NULL the default
5130 * PCI device for this device instance is used.
5131 * @param GCPhys Physical address to write to.
5132 * @param pvBuf What to write.
5133 * @param cbWrite How many bytes to write.
5134 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5135 * @thread Any thread, but the call may involve the emulation thread.
5136 */
5137 DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5138 const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5139
5140 /**
5141 * Set the IRQ for the given PCI device.
5142 *
5143 * @param pDevIns Device instance.
5144 * @param pPciDev The PCI device structure. If NULL the default
5145 * PCI device for this device instance is used.
5146 * @param iIrq IRQ number to set.
5147 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5148 * @thread Any thread, but will involve the emulation thread.
5149 */
5150 DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5151
5152 /**
5153 * Set ISA IRQ for a device.
5154 *
5155 * @param pDevIns Device instance.
5156 * @param iIrq IRQ number to set.
5157 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5158 * @thread Any thread, but will involve the emulation thread.
5159 */
5160 DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5161
5162 /**
5163 * Read physical memory.
5164 *
5165 * @returns VINF_SUCCESS (for now).
5166 * @param pDevIns Device instance.
5167 * @param GCPhys Physical address start reading from.
5168 * @param pvBuf Where to put the read bits.
5169 * @param cbRead How many bytes to read.
5170 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5171 */
5172 DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5173
5174 /**
5175 * Write to physical memory.
5176 *
5177 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5178 * @param pDevIns Device instance.
5179 * @param GCPhys Physical address to write to.
5180 * @param pvBuf What to write.
5181 * @param cbWrite How many bytes to write.
5182 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5183 */
5184 DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5185
5186 /**
5187 * Checks if the Gate A20 is enabled or not.
5188 *
5189 * @returns true if A20 is enabled.
5190 * @returns false if A20 is disabled.
5191 * @param pDevIns Device instance.
5192 * @thread The emulation thread.
5193 */
5194 DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5195
5196 /**
5197 * Gets the VM state.
5198 *
5199 * @returns VM state.
5200 * @param pDevIns The device instance.
5201 * @thread Any thread (just keep in mind that it's volatile info).
5202 */
5203 DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5204
5205 /**
5206 * Gets the VM handle. Restricted API.
5207 *
5208 * @returns VM Handle.
5209 * @param pDevIns Device instance.
5210 */
5211 DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5212
5213 /**
5214 * Gets the VMCPU handle. Restricted API.
5215 *
5216 * @returns VMCPU Handle.
5217 * @param pDevIns The device instance.
5218 */
5219 DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5220
5221 /**
5222 * The the VM CPU ID of the current thread (restricted API).
5223 *
5224 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5225 * @param pDevIns The device instance.
5226 */
5227 DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5228
5229 /**
5230 * Get the current virtual clock time in a VM. The clock frequency must be
5231 * queried separately.
5232 *
5233 * @returns Current clock time.
5234 * @param pDevIns The device instance.
5235 */
5236 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5237
5238 /**
5239 * Get the frequency of the virtual clock.
5240 *
5241 * @returns The clock frequency (not variable at run-time).
5242 * @param pDevIns The device instance.
5243 */
5244 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5245
5246 /**
5247 * Get the current virtual clock time in a VM, in nanoseconds.
5248 *
5249 * @returns Current clock time (in ns).
5250 * @param pDevIns The device instance.
5251 */
5252 DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5253
5254 /**
5255 * Gets the NOP critical section.
5256 *
5257 * @returns The ring-3 address of the NOP critical section.
5258 * @param pDevIns The device instance.
5259 */
5260 DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5261
5262 /**
5263 * Changes the device level critical section from the automatically created
5264 * default to one desired by the device constructor.
5265 *
5266 * Must first be done in ring-3.
5267 *
5268 * @returns VBox status code.
5269 * @param pDevIns The device instance.
5270 * @param pCritSect The critical section to use. NULL is not
5271 * valid, instead use the NOP critical
5272 * section.
5273 */
5274 DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5275
5276 /** @name Exported PDM Critical Section Functions
5277 * @{ */
5278 DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5279 DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5280 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5281 DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5282 DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5283 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5284 DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5285 DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5286 DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5287 /** @} */
5288
5289 /** @name Exported PDM Read/Write Critical Section Functions
5290 * @{ */
5291 DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5292 DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5293 DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5294 DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5295 DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5296
5297 DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5298 DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5299 DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5300 DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5301 DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5302
5303 DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5304 DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5305 DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5306 DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5307 DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5308 DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5309 /** @} */
5310
5311 /**
5312 * Gets the trace buffer handle.
5313 *
5314 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5315 * really inteded for direct usage, thus no inline wrapper function.
5316 *
5317 * @returns Trace buffer handle or NIL_RTTRACEBUF.
5318 * @param pDevIns The device instance.
5319 */
5320 DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5321
5322 /**
5323 * Sets up the PCI bus for the raw-mode context.
5324 *
5325 * This must be called after ring-3 has registered the PCI bus using
5326 * PDMDevHlpPCIBusRegister().
5327 *
5328 * @returns VBox status code.
5329 * @param pDevIns The device instance.
5330 * @param pPciBusReg The PCI bus registration information for raw-mode,
5331 * considered volatile.
5332 * @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5333 */
5334 DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5335
5336 /**
5337 * Sets up the IOMMU for the raw-mode context.
5338 *
5339 * This must be called after ring-3 has registered the IOMMU using
5340 * PDMDevHlpIommuRegister().
5341 *
5342 * @returns VBox status code.
5343 * @param pDevIns The device instance.
5344 * @param pIommuReg The IOMMU registration information for raw-mode,
5345 * considered volatile.
5346 * @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5347 */
5348 DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5349
5350 /**
5351 * Sets up the PIC for the ring-0 context.
5352 *
5353 * This must be called after ring-3 has registered the PIC using
5354 * PDMDevHlpPICRegister().
5355 *
5356 * @returns VBox status code.
5357 * @param pDevIns The device instance.
5358 * @param pPicReg The PIC registration information for ring-0,
5359 * considered volatile and copied.
5360 * @param ppPicHlp Where to return the ring-0 PIC helpers.
5361 */
5362 DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5363
5364 /**
5365 * Sets up the APIC for the raw-mode context.
5366 *
5367 * This must be called after ring-3 has registered the APIC using
5368 * PDMDevHlpApicRegister().
5369 *
5370 * @returns VBox status code.
5371 * @param pDevIns The device instance.
5372 */
5373 DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5374
5375 /**
5376 * Sets up the IOAPIC for the ring-0 context.
5377 *
5378 * This must be called after ring-3 has registered the PIC using
5379 * PDMDevHlpIoApicRegister().
5380 *
5381 * @returns VBox status code.
5382 * @param pDevIns The device instance.
5383 * @param pIoApicReg The PIC registration information for ring-0,
5384 * considered volatile and copied.
5385 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5386 */
5387 DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5388
5389 /**
5390 * Sets up the HPET for the raw-mode context.
5391 *
5392 * This must be called after ring-3 has registered the PIC using
5393 * PDMDevHlpHpetRegister().
5394 *
5395 * @returns VBox status code.
5396 * @param pDevIns The device instance.
5397 * @param pHpetReg The PIC registration information for raw-mode,
5398 * considered volatile and copied.
5399 * @param ppHpetHlp Where to return the raw-mode HPET helpers.
5400 */
5401 DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5402
5403 /** Space reserved for future members.
5404 * @{ */
5405 DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5406 DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5407 DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5408 DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5409 DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5410 DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5411 DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5412 DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5413 DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5414 DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5415 /** @} */
5416
5417 /** Just a safety precaution. */
5418 uint32_t u32TheEnd;
5419} PDMDEVHLPRC;
5420/** Pointer PDM Device RC API. */
5421typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5422/** Pointer PDM Device RC API. */
5423typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5424
5425/** Current PDMDEVHLP version number. */
5426#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 18, 0)
5427
5428
5429/**
5430 * PDM Device API - R0 Variant.
5431 */
5432typedef struct PDMDEVHLPR0
5433{
5434 /** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5435 uint32_t u32Version;
5436
5437 /**
5438 * Sets up ring-0 callback handlers for an I/O port range.
5439 *
5440 * The range must have been created in ring-3 first using
5441 * PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5442 *
5443 * @returns VBox status.
5444 * @param pDevIns The device instance to register the ports with.
5445 * @param hIoPorts The I/O port range handle.
5446 * @param pfnOut Pointer to function which is gonna handle OUT
5447 * operations. Optional.
5448 * @param pfnIn Pointer to function which is gonna handle IN operations.
5449 * Optional.
5450 * @param pfnOutStr Pointer to function which is gonna handle string OUT
5451 * operations. Optional.
5452 * @param pfnInStr Pointer to function which is gonna handle string IN
5453 * operations. Optional.
5454 * @param pvUser User argument to pass to the callbacks.
5455 *
5456 * @remarks Caller enters the device critical section prior to invoking the
5457 * registered callback methods.
5458 *
5459 * @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5460 * PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5461 */
5462 DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5463 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5464 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5465 void *pvUser));
5466
5467 /**
5468 * Sets up ring-0 callback handlers for an MMIO region.
5469 *
5470 * The region must have been created in ring-3 first using
5471 * PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5472 * PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5473 *
5474 * @returns VBox status.
5475 * @param pDevIns The device instance to register the ports with.
5476 * @param hRegion The MMIO region handle.
5477 * @param pfnWrite Pointer to function which is gonna handle Write
5478 * operations.
5479 * @param pfnRead Pointer to function which is gonna handle Read
5480 * operations.
5481 * @param pfnFill Pointer to function which is gonna handle Fill/memset
5482 * operations. (optional)
5483 * @param pvUser User argument to pass to the callbacks.
5484 *
5485 * @remarks Caller enters the device critical section prior to invoking the
5486 * registered callback methods.
5487 *
5488 * @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5489 * PDMDevHlpMmioUnmap().
5490 */
5491 DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5492 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5493
5494 /**
5495 * Sets up a ring-0 mapping for an MMIO2 region.
5496 *
5497 * The region must have been created in ring-3 first using
5498 * PDMDevHlpMmio2Create().
5499 *
5500 * @returns VBox status.
5501 * @param pDevIns The device instance to register the ports with.
5502 * @param hRegion The MMIO2 region handle.
5503 * @param offSub Start of what to map into ring-0. Must be page aligned.
5504 * @param cbSub Number of bytes to map into ring-0. Must be page
5505 * aligned. Zero is an alias for everything.
5506 * @param ppvMapping Where to return the mapping corresponding to @a offSub.
5507 *
5508 * @thread EMT(0)
5509 * @note Only available at VM creation time.
5510 *
5511 * @sa PDMDevHlpMmio2Create().
5512 */
5513 DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5514 void **ppvMapping));
5515
5516 /**
5517 * Bus master physical memory read from the given PCI device.
5518 *
5519 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5520 * VERR_EM_MEMORY.
5521 * @param pDevIns The device instance.
5522 * @param pPciDev The PCI device structure. If NULL the default
5523 * PCI device for this device instance is used.
5524 * @param GCPhys Physical address start reading from.
5525 * @param pvBuf Where to put the read bits.
5526 * @param cbRead How many bytes to read.
5527 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5528 * @thread Any thread, but the call may involve the emulation thread.
5529 */
5530 DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5531 void *pvBuf, size_t cbRead, uint32_t fFlags));
5532
5533 /**
5534 * Bus master physical memory write from the given PCI device.
5535 *
5536 * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5537 * VERR_EM_MEMORY.
5538 * @param pDevIns The device instance.
5539 * @param pPciDev The PCI device structure. If NULL the default
5540 * PCI device for this device instance is used.
5541 * @param GCPhys Physical address to write to.
5542 * @param pvBuf What to write.
5543 * @param cbWrite How many bytes to write.
5544 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5545 * @thread Any thread, but the call may involve the emulation thread.
5546 */
5547 DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5548 const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5549
5550 /**
5551 * Set the IRQ for the given PCI device.
5552 *
5553 * @param pDevIns Device instance.
5554 * @param pPciDev The PCI device structure. If NULL the default
5555 * PCI device for this device instance is used.
5556 * @param iIrq IRQ number to set.
5557 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5558 * @thread Any thread, but will involve the emulation thread.
5559 */
5560 DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5561
5562 /**
5563 * Set ISA IRQ for a device.
5564 *
5565 * @param pDevIns Device instance.
5566 * @param iIrq IRQ number to set.
5567 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5568 * @thread Any thread, but will involve the emulation thread.
5569 */
5570 DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5571
5572 /**
5573 * Read physical memory.
5574 *
5575 * @returns VINF_SUCCESS (for now).
5576 * @param pDevIns Device instance.
5577 * @param GCPhys Physical address start reading from.
5578 * @param pvBuf Where to put the read bits.
5579 * @param cbRead How many bytes to read.
5580 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5581 */
5582 DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5583
5584 /**
5585 * Write to physical memory.
5586 *
5587 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5588 * @param pDevIns Device instance.
5589 * @param GCPhys Physical address to write to.
5590 * @param pvBuf What to write.
5591 * @param cbWrite How many bytes to write.
5592 * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5593 */
5594 DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5595
5596 /**
5597 * Checks if the Gate A20 is enabled or not.
5598 *
5599 * @returns true if A20 is enabled.
5600 * @returns false if A20 is disabled.
5601 * @param pDevIns Device instance.
5602 * @thread The emulation thread.
5603 */
5604 DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5605
5606 /**
5607 * Gets the VM state.
5608 *
5609 * @returns VM state.
5610 * @param pDevIns The device instance.
5611 * @thread Any thread (just keep in mind that it's volatile info).
5612 */
5613 DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5614
5615 /**
5616 * Gets the VM handle. Restricted API.
5617 *
5618 * @returns VM Handle.
5619 * @param pDevIns Device instance.
5620 */
5621 DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5622
5623 /**
5624 * Gets the VMCPU handle. Restricted API.
5625 *
5626 * @returns VMCPU Handle.
5627 * @param pDevIns The device instance.
5628 */
5629 DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5630
5631 /**
5632 * The the VM CPU ID of the current thread (restricted API).
5633 *
5634 * @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5635 * @param pDevIns The device instance.
5636 */
5637 DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5638
5639 /** @name Timer handle method wrappers
5640 * @{ */
5641 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5642 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5643 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5644 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5645 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5646 DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5647 DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5648 DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5649 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5650 /** Takes the clock lock then enters the specified critical section. */
5651 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5652 DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5653 DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5654 DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5655 DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5656 DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5657 DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5658 DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5659 DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5660 DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5661 /** @} */
5662
5663 /**
5664 * Get the current virtual clock time in a VM. The clock frequency must be
5665 * queried separately.
5666 *
5667 * @returns Current clock time.
5668 * @param pDevIns The device instance.
5669 */
5670 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5671
5672 /**
5673 * Get the frequency of the virtual clock.
5674 *
5675 * @returns The clock frequency (not variable at run-time).
5676 * @param pDevIns The device instance.
5677 */
5678 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5679
5680 /**
5681 * Get the current virtual clock time in a VM, in nanoseconds.
5682 *
5683 * @returns Current clock time (in ns).
5684 * @param pDevIns The device instance.
5685 */
5686 DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5687
5688 /** @name Exported PDM Queue Functions
5689 * @{ */
5690 DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5691 DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5692 DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5693 /** @} */
5694
5695 /** @name PDM Task
5696 * @{ */
5697 /**
5698 * Triggers the running the given task.
5699 *
5700 * @returns VBox status code.
5701 * @retval VINF_ALREADY_POSTED is the task is already pending.
5702 * @param pDevIns The device instance.
5703 * @param hTask The task to trigger.
5704 * @thread Any thread.
5705 */
5706 DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5707 /** @} */
5708
5709 /** @name SUP Event Semaphore Wrappers (single release / auto reset)
5710 * These semaphores can be signalled from ring-0.
5711 * @{ */
5712 /** @sa SUPSemEventSignal */
5713 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5714 /** @sa SUPSemEventWaitNoResume */
5715 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5716 /** @sa SUPSemEventWaitNsAbsIntr */
5717 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5718 /** @sa SUPSemEventWaitNsRelIntr */
5719 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5720 /** @sa SUPSemEventGetResolution */
5721 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5722 /** @} */
5723
5724 /** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5725 * These semaphores can be signalled from ring-0.
5726 * @{ */
5727 /** @sa SUPSemEventMultiSignal */
5728 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5729 /** @sa SUPSemEventMultiReset */
5730 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5731 /** @sa SUPSemEventMultiWaitNoResume */
5732 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5733 /** @sa SUPSemEventMultiWaitNsAbsIntr */
5734 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5735 /** @sa SUPSemEventMultiWaitNsRelIntr */
5736 DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5737 /** @sa SUPSemEventMultiGetResolution */
5738 DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5739 /** @} */
5740
5741 /**
5742 * Gets the NOP critical section.
5743 *
5744 * @returns The ring-3 address of the NOP critical section.
5745 * @param pDevIns The device instance.
5746 */
5747 DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5748
5749 /**
5750 * Changes the device level critical section from the automatically created
5751 * default to one desired by the device constructor.
5752 *
5753 * Must first be done in ring-3.
5754 *
5755 * @returns VBox status code.
5756 * @param pDevIns The device instance.
5757 * @param pCritSect The critical section to use. NULL is not
5758 * valid, instead use the NOP critical
5759 * section.
5760 */
5761 DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5762
5763 /** @name Exported PDM Critical Section Functions
5764 * @{ */
5765 DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5766 DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5767 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5768 DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5769 DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5770 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5771 DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5772 DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5773 DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5774 DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5775 /** @} */
5776
5777 /** @name Exported PDM Read/Write Critical Section Functions
5778 * @{ */
5779 DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5780 DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5781 DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5782 DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5783 DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5784
5785 DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5786 DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5787 DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5788 DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5789 DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5790
5791 DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5792 DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5793 DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5794 DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5795 DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5796 DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5797 /** @} */
5798
5799 /**
5800 * Gets the trace buffer handle.
5801 *
5802 * This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5803 * really inteded for direct usage, thus no inline wrapper function.
5804 *
5805 * @returns Trace buffer handle or NIL_RTTRACEBUF.
5806 * @param pDevIns The device instance.
5807 */
5808 DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5809
5810 /**
5811 * Sets up the PCI bus for the ring-0 context.
5812 *
5813 * This must be called after ring-3 has registered the PCI bus using
5814 * PDMDevHlpPCIBusRegister().
5815 *
5816 * @returns VBox status code.
5817 * @param pDevIns The device instance.
5818 * @param pPciBusReg The PCI bus registration information for ring-0,
5819 * considered volatile and copied.
5820 * @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5821 */
5822 DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5823
5824 /**
5825 * Sets up the IOMMU for the ring-0 context.
5826 *
5827 * This must be called after ring-3 has registered the IOMMU using
5828 * PDMDevHlpIommuRegister().
5829 *
5830 * @returns VBox status code.
5831 * @param pDevIns The device instance.
5832 * @param pIommuReg The IOMMU registration information for ring-0,
5833 * considered volatile and copied.
5834 * @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5835 */
5836 DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5837
5838 /**
5839 * Sets up the PIC for the ring-0 context.
5840 *
5841 * This must be called after ring-3 has registered the PIC using
5842 * PDMDevHlpPICRegister().
5843 *
5844 * @returns VBox status code.
5845 * @param pDevIns The device instance.
5846 * @param pPicReg The PIC registration information for ring-0,
5847 * considered volatile and copied.
5848 * @param ppPicHlp Where to return the ring-0 PIC helpers.
5849 */
5850 DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5851
5852 /**
5853 * Sets up the APIC for the ring-0 context.
5854 *
5855 * This must be called after ring-3 has registered the APIC using
5856 * PDMDevHlpApicRegister().
5857 *
5858 * @returns VBox status code.
5859 * @param pDevIns The device instance.
5860 */
5861 DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5862
5863 /**
5864 * Sets up the IOAPIC for the ring-0 context.
5865 *
5866 * This must be called after ring-3 has registered the PIC using
5867 * PDMDevHlpIoApicRegister().
5868 *
5869 * @returns VBox status code.
5870 * @param pDevIns The device instance.
5871 * @param pIoApicReg The PIC registration information for ring-0,
5872 * considered volatile and copied.
5873 * @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5874 */
5875 DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5876
5877 /**
5878 * Sets up the HPET for the ring-0 context.
5879 *
5880 * This must be called after ring-3 has registered the PIC using
5881 * PDMDevHlpHpetRegister().
5882 *
5883 * @returns VBox status code.
5884 * @param pDevIns The device instance.
5885 * @param pHpetReg The PIC registration information for ring-0,
5886 * considered volatile and copied.
5887 * @param ppHpetHlp Where to return the ring-0 HPET helpers.
5888 */
5889 DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5890
5891 /**
5892 * Temporarily turns off the access monitoring of a page within a monitored
5893 * physical write/all page access handler region.
5894 *
5895 * Use this when no further \#PFs are required for that page. Be aware that
5896 * a page directory sync might reset the flags, and turn on access monitoring
5897 * for the page.
5898 *
5899 * The caller must do required page table modifications.
5900 *
5901 * @returns VBox status code.
5902 * @param pDevIns The device instance.
5903 * @param GCPhys The start address of the access handler. This
5904 * must be a fully page aligned range or we risk
5905 * messing up other handlers installed for the
5906 * start and end pages.
5907 * @param GCPhysPage The physical address of the page to turn off
5908 * access monitoring for.
5909 */
5910 DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
5911
5912 /**
5913 * Mapping an MMIO2 page in place of an MMIO page for direct access.
5914 *
5915 * This is a special optimization used by the VGA device. Call
5916 * PDMDevHlpMmioResetRegion() to undo the mapping.
5917 *
5918 * @returns VBox status code. This API may return VINF_SUCCESS even if no
5919 * remapping is made.
5920 * @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
5921 *
5922 * @param pDevIns The device instance @a hRegion and @a hMmio2 are
5923 * associated with.
5924 * @param hRegion The handle to the MMIO region.
5925 * @param offRegion The offset into @a hRegion of the page to be
5926 * remapped.
5927 * @param hMmio2 The MMIO2 handle.
5928 * @param offMmio2 Offset into @a hMmio2 of the page to be use for the
5929 * mapping.
5930 * @param fPageFlags Page flags to set. Must be (X86_PTE_RW | X86_PTE_P)
5931 * for the time being.
5932 */
5933 DECLR0CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
5934 uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
5935
5936 /**
5937 * Reset a previously modified MMIO region; restore the access flags.
5938 *
5939 * This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
5940 * intended for some ancient VGA hack. However, it would be great to extend it
5941 * beyond VT-x and/or nested-paging.
5942 *
5943 * @returns VBox status code.
5944 *
5945 * @param pDevIns The device instance @a hRegion is associated with.
5946 * @param hRegion The handle to the MMIO region.
5947 */
5948 DECLR0CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
5949
5950 /**
5951 * Returns the array of MMIO2 regions that are expected to be registered and
5952 * later mapped into the guest-physical address space for the GIM provider
5953 * configured for the VM.
5954 *
5955 * @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
5956 * @param pDevIns Pointer to the GIM device instance.
5957 * @param pcRegions Where to store the number of items in the array.
5958 *
5959 * @remarks The caller does not own and therefore must -NOT- try to free the
5960 * returned pointer.
5961 */
5962 DECLR0CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
5963
5964 /** Space reserved for future members.
5965 * @{ */
5966 DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5967 DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5968 DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5969 DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5970 DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5971 DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5972 DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5973 DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5974 DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5975 DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5976 /** @} */
5977
5978 /** Just a safety precaution. */
5979 uint32_t u32TheEnd;
5980} PDMDEVHLPR0;
5981/** Pointer PDM Device R0 API. */
5982typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5983/** Pointer PDM Device GC API. */
5984typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5985
5986/** Current PDMDEVHLP version number. */
5987#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 25, 0)
5988
5989
5990/**
5991 * PDM Device Instance.
5992 */
5993typedef struct PDMDEVINSR3
5994{
5995 /** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5996 uint32_t u32Version;
5997 /** Device instance number. */
5998 uint32_t iInstance;
5999 /** Size of the ring-3, raw-mode and shared bits. */
6000 uint32_t cbRing3;
6001 /** Set if ring-0 context is enabled. */
6002 bool fR0Enabled;
6003 /** Set if raw-mode context is enabled. */
6004 bool fRCEnabled;
6005 /** Alignment padding. */
6006 bool afReserved[2];
6007 /** Pointer the HC PDM Device API. */
6008 PCPDMDEVHLPR3 pHlpR3;
6009 /** Pointer to the shared device instance data. */
6010 RTR3PTR pvInstanceDataR3;
6011 /** Pointer to the device instance data for ring-3. */
6012 RTR3PTR pvInstanceDataForR3;
6013 /** The critical section for the device.
6014 *
6015 * TM and IOM will enter this critical section before calling into the device
6016 * code. PDM will when doing power on, power off, reset, suspend and resume
6017 * notifications. SSM will currently not, but this will be changed later on.
6018 *
6019 * The device gets a critical section automatically assigned to it before
6020 * the constructor is called. If the constructor wishes to use a different
6021 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6022 * very early on.
6023 */
6024 R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
6025 /** Pointer to device registration structure. */
6026 R3PTRTYPE(PCPDMDEVREG) pReg;
6027 /** Configuration handle. */
6028 R3PTRTYPE(PCFGMNODE) pCfg;
6029 /** The base interface of the device.
6030 *
6031 * The device constructor initializes this if it has any
6032 * device level interfaces to export. To obtain this interface
6033 * call PDMR3QueryDevice(). */
6034 PDMIBASE IBase;
6035
6036 /** Tracing indicator. */
6037 uint32_t fTracing;
6038 /** The tracing ID of this device. */
6039 uint32_t idTracing;
6040
6041 /** Ring-3 pointer to the raw-mode device instance. */
6042 R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
6043 /** Raw-mode address of the raw-mode device instance. */
6044 RTRGPTR pDevInsForRC;
6045 /** Ring-3 pointer to the raw-mode instance data. */
6046 RTR3PTR pvInstanceDataForRCR3;
6047
6048 /** PCI device structure size. */
6049 uint32_t cbPciDev;
6050 /** Number of PCI devices in apPciDevs. */
6051 uint32_t cPciDevs;
6052 /** Pointer to the PCI devices for this device.
6053 * (Allocated after the shared instance data.)
6054 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6055 * two devices ever needing it can use cbPciDev and do the address
6056 * calculations that for entries 8+. */
6057 R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6058
6059 /** Temporarily. */
6060 R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
6061 /** Temporarily. */
6062 RTR0PTR pvInstanceDataR0;
6063 /** Temporarily. */
6064 RTRCPTR pvInstanceDataRC;
6065 /** Align the internal data more naturally. */
6066 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
6067
6068 /** Internal data. */
6069 union
6070 {
6071#ifdef PDMDEVINSINT_DECLARED
6072 PDMDEVINSINTR3 s;
6073#endif
6074 uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
6075 } Internal;
6076
6077 /** Device instance data for ring-3. The size of this area is defined
6078 * in the PDMDEVREG::cbInstanceR3 field. */
6079 char achInstanceData[8];
6080} PDMDEVINSR3;
6081
6082/** Current PDMDEVINSR3 version number. */
6083#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
6084
6085/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
6086#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
6087
6088
6089/**
6090 * PDM ring-0 device instance.
6091 */
6092typedef struct PDMDEVINSR0
6093{
6094 /** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
6095 uint32_t u32Version;
6096 /** Device instance number. */
6097 uint32_t iInstance;
6098
6099 /** Pointer the HC PDM Device API. */
6100 PCPDMDEVHLPR0 pHlpR0;
6101 /** Pointer to the shared device instance data. */
6102 RTR0PTR pvInstanceDataR0;
6103 /** Pointer to the device instance data for ring-0. */
6104 RTR0PTR pvInstanceDataForR0;
6105 /** The critical section for the device.
6106 *
6107 * TM and IOM will enter this critical section before calling into the device
6108 * code. PDM will when doing power on, power off, reset, suspend and resume
6109 * notifications. SSM will currently not, but this will be changed later on.
6110 *
6111 * The device gets a critical section automatically assigned to it before
6112 * the constructor is called. If the constructor wishes to use a different
6113 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6114 * very early on.
6115 */
6116 R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
6117 /** Pointer to the ring-0 device registration structure. */
6118 R0PTRTYPE(PCPDMDEVREGR0) pReg;
6119 /** Ring-3 address of the ring-3 device instance. */
6120 R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
6121 /** Ring-0 pointer to the ring-3 device instance. */
6122 R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
6123 /** Ring-0 pointer to the ring-3 instance data. */
6124 RTR0PTR pvInstanceDataForR3R0;
6125 /** Raw-mode address of the raw-mode device instance. */
6126 RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
6127 /** Ring-0 pointer to the raw-mode device instance. */
6128 R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
6129 /** Ring-0 pointer to the raw-mode instance data. */
6130 RTR0PTR pvInstanceDataForRCR0;
6131
6132 /** PCI device structure size. */
6133 uint32_t cbPciDev;
6134 /** Number of PCI devices in apPciDevs. */
6135 uint32_t cPciDevs;
6136 /** Pointer to the PCI devices for this device.
6137 * (Allocated after the shared instance data.)
6138 * @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6139 * two devices ever needing it can use cbPciDev and do the address
6140 * calculations that for entries 8+. */
6141 R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6142
6143 /** Align the internal data more naturally. */
6144 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
6145
6146 /** Internal data. */
6147 union
6148 {
6149#ifdef PDMDEVINSINT_DECLARED
6150 PDMDEVINSINTR0 s;
6151#endif
6152 uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
6153 } Internal;
6154
6155 /** Device instance data for ring-0. The size of this area is defined
6156 * in the PDMDEVREG::cbInstanceR0 field. */
6157 char achInstanceData[8];
6158} PDMDEVINSR0;
6159
6160/** Current PDMDEVINSR0 version number. */
6161#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
6162
6163
6164/**
6165 * PDM raw-mode device instance.
6166 */
6167typedef struct PDMDEVINSRC
6168{
6169 /** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
6170 uint32_t u32Version;
6171 /** Device instance number. */
6172 uint32_t iInstance;
6173
6174 /** Pointer the HC PDM Device API. */
6175 PCPDMDEVHLPRC pHlpRC;
6176 /** Pointer to the shared device instance data. */
6177 RTRGPTR pvInstanceDataRC;
6178 /** Pointer to the device instance data for raw-mode. */
6179 RTRGPTR pvInstanceDataForRC;
6180 /** The critical section for the device.
6181 *
6182 * TM and IOM will enter this critical section before calling into the device
6183 * code. PDM will when doing power on, power off, reset, suspend and resume
6184 * notifications. SSM will currently not, but this will be changed later on.
6185 *
6186 * The device gets a critical section automatically assigned to it before
6187 * the constructor is called. If the constructor wishes to use a different
6188 * critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6189 * very early on.
6190 */
6191 RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
6192 /** Pointer to the raw-mode device registration structure. */
6193 RGPTRTYPE(PCPDMDEVREGRC) pReg;
6194
6195 /** PCI device structure size. */
6196 uint32_t cbPciDev;
6197 /** Number of PCI devices in apPciDevs. */
6198 uint32_t cPciDevs;
6199 /** Pointer to the PCI devices for this device.
6200 * (Allocated after the shared instance data.) */
6201 RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6202
6203 /** Align the internal data more naturally. */
6204 uint32_t au32Padding[14];
6205
6206 /** Internal data. */
6207 union
6208 {
6209#ifdef PDMDEVINSINT_DECLARED
6210 PDMDEVINSINTRC s;
6211#endif
6212 uint8_t padding[0x10];
6213 } Internal;
6214
6215 /** Device instance data for ring-0. The size of this area is defined
6216 * in the PDMDEVREG::cbInstanceR0 field. */
6217 char achInstanceData[8];
6218} PDMDEVINSRC;
6219
6220/** Current PDMDEVINSR0 version number. */
6221#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
6222
6223
6224/** @def PDM_DEVINS_VERSION
6225 * Current PDMDEVINS version number. */
6226/** @typedef PDMDEVINS
6227 * The device instance structure for the current context. */
6228#ifdef IN_RING3
6229# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
6230typedef PDMDEVINSR3 PDMDEVINS;
6231#elif defined(IN_RING0)
6232# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
6233typedef PDMDEVINSR0 PDMDEVINS;
6234#elif defined(IN_RC)
6235# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
6236typedef PDMDEVINSRC PDMDEVINS;
6237#else
6238# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
6239#endif
6240
6241/**
6242 * Get the pointer to an PCI device.
6243 * @note Returns NULL if @a a_idxPciDev is out of bounds.
6244 */
6245#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
6246 ( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
6247 : PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
6248
6249/**
6250 * Calc the pointer to of a given PCI device.
6251 * @note Returns NULL if @a a_idxPciDev is out of bounds.
6252 */
6253#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
6254 ( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
6255 ? (PPDMPCIDEV)((uint8_t *)((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) * (uintptr_t)(a_idxPciDev)) \
6256 : (PPDMPCIDEV)NULL )
6257
6258
6259/**
6260 * Checks the structure versions of the device instance and device helpers,
6261 * returning if they are incompatible.
6262 *
6263 * This is for use in the constructor.
6264 *
6265 * @param pDevIns The device instance pointer.
6266 */
6267#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6268 do \
6269 { \
6270 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6271 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6272 ("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6273 VERR_PDM_DEVINS_VERSION_MISMATCH); \
6274 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6275 ("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6276 VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6277 } while (0)
6278
6279/**
6280 * Quietly checks the structure versions of the device instance and device
6281 * helpers, returning if they are incompatible.
6282 *
6283 * This is for use in the destructor.
6284 *
6285 * @param pDevIns The device instance pointer.
6286 */
6287#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6288 do \
6289 { \
6290 PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6291 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6292 { /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6293 if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6294 { /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6295 } while (0)
6296
6297/**
6298 * Wrapper around CFGMR3ValidateConfig for the root config for use in the
6299 * constructor - returns on failure.
6300 *
6301 * This should be invoked after having initialized the instance data
6302 * sufficiently for the correct operation of the destructor. The destructor is
6303 * always called!
6304 *
6305 * @param pDevIns Pointer to the PDM device instance.
6306 * @param pszValidValues Patterns describing the valid value names. See
6307 * RTStrSimplePatternMultiMatch for details on the
6308 * pattern syntax.
6309 * @param pszValidNodes Patterns describing the valid node (key) names.
6310 * Pass empty string if no valid nodes.
6311 */
6312#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6313 do \
6314 { \
6315 int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6316 (pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6317 if (RT_SUCCESS(rcValCfg)) \
6318 { /* likely */ } else return rcValCfg; \
6319 } while (0)
6320
6321/** @def PDMDEV_ASSERT_EMT
6322 * Assert that the current thread is the emulation thread.
6323 */
6324#ifdef VBOX_STRICT
6325# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6326#else
6327# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6328#endif
6329
6330/** @def PDMDEV_ASSERT_OTHER
6331 * Assert that the current thread is NOT the emulation thread.
6332 */
6333#ifdef VBOX_STRICT
6334# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6335#else
6336# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6337#endif
6338
6339/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6340 * Assert that the current thread is owner of the VM lock.
6341 */
6342#ifdef VBOX_STRICT
6343# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6344#else
6345# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6346#endif
6347
6348/** @def PDMDEV_SET_ERROR
6349 * Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6350 */
6351#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6352 PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6353
6354/** @def PDMDEV_SET_RUNTIME_ERROR
6355 * Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6356 */
6357#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6358 PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6359
6360/** @def PDMDEVINS_2_RCPTR
6361 * Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6362 */
6363#ifdef IN_RC
6364# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6365#else
6366# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6367#endif
6368
6369/** @def PDMDEVINS_2_R3PTR
6370 * Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6371 */
6372#ifdef IN_RING3
6373# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6374#else
6375# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6376#endif
6377
6378/** @def PDMDEVINS_2_R0PTR
6379 * Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6380 */
6381#ifdef IN_RING0
6382# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6383#else
6384# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6385#endif
6386
6387/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6388 * Converts a PDM device instance data pointer to a ring-0 one.
6389 * @deprecated
6390 */
6391#ifdef IN_RING0
6392# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6393#else
6394# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6395#endif
6396
6397
6398/** @def PDMDEVINS_2_DATA
6399 * This is a safer edition of PDMINS_2_DATA that checks that the size of the
6400 * target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6401 *
6402 * @note Do no use this macro in common code working on a core structure which
6403 * device specific code has expanded.
6404 */
6405#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6406# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6407 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6408 { \
6409 a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6410 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6411 return pLambdaRet; \
6412 }(a_pDevIns))
6413#else
6414# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6415#endif
6416
6417/** @def PDMDEVINS_2_DATA_CC
6418 * This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6419 * target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6420 *
6421 * @note Do no use this macro in common code working on a core structure which
6422 * device specific code has expanded.
6423 */
6424#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6425# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6426 ([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6427 { \
6428 a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6429 Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6430 return pLambdaRet; \
6431 }(a_pDevIns))
6432#else
6433# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6434#endif
6435
6436
6437#ifdef IN_RING3
6438
6439/**
6440 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6441 */
6442DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6443 PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6444 PIOMIOPORTHANDLE phIoPorts)
6445{
6446 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6447 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6448 if (RT_SUCCESS(rc))
6449 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6450 return rc;
6451}
6452
6453/**
6454 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6455 */
6456DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6457 PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6458 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6459{
6460 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6461 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6462 if (RT_SUCCESS(rc))
6463 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6464 return rc;
6465}
6466
6467/**
6468 * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6469 */
6470DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6471 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6472 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6473{
6474 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6475 pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6476 if (RT_SUCCESS(rc))
6477 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6478 return rc;
6479}
6480
6481/**
6482 * Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6483 */
6484DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6485 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6486 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6487 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6488{
6489 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6490 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6491 if (RT_SUCCESS(rc))
6492 rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6493 return rc;
6494}
6495
6496/**
6497 * @sa PDMDevHlpIoPortCreateEx
6498 */
6499DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6500 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
6501 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6502{
6503 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6504 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6505}
6506
6507
6508/**
6509 * @sa PDMDevHlpIoPortCreateEx
6510 */
6511DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6512 PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
6513 PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6514{
6515 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6516 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6517}
6518
6519/**
6520 * @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6521 */
6522DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6523 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6524 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6525 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6526{
6527 return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6528 pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6529}
6530
6531/**
6532 * @copydoc PDMDEVHLPR3::pfnIoPortMap
6533 */
6534DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6535{
6536 return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6537}
6538
6539/**
6540 * @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6541 */
6542DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6543{
6544 return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6545}
6546
6547/**
6548 * @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6549 */
6550DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6551{
6552 return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6553}
6554
6555
6556#endif /* IN_RING3 */
6557#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6558
6559/**
6560 * @sa PDMDevHlpIoPortSetUpContextEx
6561 */
6562DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6563 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6564{
6565 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6566}
6567
6568/**
6569 * @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6570 */
6571DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6572 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6573 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6574{
6575 return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6576}
6577
6578#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6579#ifdef IN_RING3
6580
6581/**
6582 * @sa PDMDevHlpMmioCreateEx
6583 */
6584DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6585 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6586 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6587{
6588 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6589 pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6590}
6591
6592/**
6593 * @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6594 */
6595DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6596 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6597 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6598 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6599{
6600 return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6601 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6602}
6603
6604/**
6605 * @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6606 */
6607DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6608 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6609 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6610{
6611 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /*pPciDev*/, UINT32_MAX /*iPciRegion*/,
6612 pfnWrite, pfnRead, NULL /*pfnFill*/, NULL /*pvUser*/, pszDesc, phRegion);
6613 if (RT_SUCCESS(rc))
6614 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6615 return rc;
6616}
6617
6618/**
6619 * @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6620 */
6621DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6622 PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6623 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6624 const char *pszDesc, PIOMMMIOHANDLE phRegion)
6625{
6626 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6627 pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6628 if (RT_SUCCESS(rc))
6629 rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6630 return rc;
6631}
6632
6633/**
6634 * @copydoc PDMDEVHLPR3::pfnMmioMap
6635 */
6636DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6637{
6638 return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6639}
6640
6641/**
6642 * @copydoc PDMDEVHLPR3::pfnMmioUnmap
6643 */
6644DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6645{
6646 return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6647}
6648
6649/**
6650 * @copydoc PDMDEVHLPR3::pfnMmioReduce
6651 */
6652DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6653{
6654 return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6655}
6656
6657/**
6658 * @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6659 */
6660DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6661{
6662 return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6663}
6664
6665#endif /* IN_RING3 */
6666#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6667
6668/**
6669 * @sa PDMDevHlpMmioSetUpContextEx
6670 */
6671DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6672 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6673{
6674 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6675}
6676
6677/**
6678 * @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6679 */
6680DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6681 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6682{
6683 return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6684}
6685
6686#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6687#ifdef IN_RING3
6688
6689/**
6690 * @copydoc PDMDEVHLPR3::pfnMmio2Create
6691 */
6692DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6693 uint32_t fFlags, const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
6694{
6695 return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6696}
6697
6698/**
6699 * @copydoc PDMDEVHLPR3::pfnMmio2Map
6700 */
6701DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6702{
6703 return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6704}
6705
6706/**
6707 * @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6708 */
6709DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6710{
6711 return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6712}
6713
6714/**
6715 * @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6716 */
6717DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6718{
6719 return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6720}
6721
6722/**
6723 * @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6724 */
6725DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6726{
6727 return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6728}
6729
6730#endif /* IN_RING3 */
6731
6732/**
6733 * @copydoc PDMDEVHLPR3::pfnMmioMapMmio2Page
6734 */
6735DECLINLINE(RTGCPHYS) PDMDevHlpMmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6736 uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
6737{
6738 return pDevIns->CTX_SUFF(pHlp)->pfnMmioMapMmio2Page(pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
6739}
6740
6741/**
6742 * @copydoc PDMDEVHLPR3::pfnMmioResetRegion
6743 */
6744DECLINLINE(RTGCPHYS) PDMDevHlpMmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6745{
6746 return pDevIns->CTX_SUFF(pHlp)->pfnMmioResetRegion(pDevIns, hRegion);
6747}
6748
6749#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
6750
6751/**
6752 * @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6753 */
6754DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6755 size_t offSub, size_t cbSub, void **ppvMapping)
6756{
6757 return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6758}
6759
6760#endif /* !IN_RING3 || DOXYGEN_RUNNING */
6761#ifdef IN_RING3
6762
6763/**
6764 * @copydoc PDMDEVHLPR3::pfnROMRegister
6765 */
6766DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6767 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc)
6768{
6769 return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6770}
6771
6772/**
6773 * @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6774 */
6775DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6776{
6777 return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6778}
6779
6780/**
6781 * Register a save state data unit.
6782 *
6783 * @returns VBox status.
6784 * @param pDevIns The device instance.
6785 * @param uVersion Data layout version number.
6786 * @param cbGuess The approximate amount of data in the unit.
6787 * Only for progress indicators.
6788 * @param pfnSaveExec Execute save callback, optional.
6789 * @param pfnLoadExec Execute load callback, optional.
6790 */
6791DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6792 PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6793{
6794 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6795 NULL /*pfnLivePrep*/, NULL /*pfnLiveExec*/, NULL /*pfnLiveDone*/,
6796 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6797 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6798}
6799
6800/**
6801 * Register a save state data unit with a live save callback as well.
6802 *
6803 * @returns VBox status.
6804 * @param pDevIns The device instance.
6805 * @param uVersion Data layout version number.
6806 * @param cbGuess The approximate amount of data in the unit.
6807 * Only for progress indicators.
6808 * @param pfnLiveExec Execute live callback, optional.
6809 * @param pfnSaveExec Execute save callback, optional.
6810 * @param pfnLoadExec Execute load callback, optional.
6811 */
6812DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6813 PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6814{
6815 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /*pszBefore*/,
6816 NULL /*pfnLivePrep*/, pfnLiveExec, NULL /*pfnLiveDone*/,
6817 NULL /*pfnSavePrep*/, pfnSaveExec, NULL /*pfnSaveDone*/,
6818 NULL /*pfnLoadPrep*/, pfnLoadExec, NULL /*pfnLoadDone*/);
6819}
6820
6821/**
6822 * @copydoc PDMDEVHLPR3::pfnSSMRegister
6823 */
6824DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6825 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6826 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6827 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6828{
6829 return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6830 pfnLivePrep, pfnLiveExec, pfnLiveVote,
6831 pfnSavePrep, pfnSaveExec, pfnSaveDone,
6832 pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6833}
6834
6835/**
6836 * @copydoc PDMDEVHLPR3::pfnTimerCreate
6837 */
6838DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6839 uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6840{
6841 return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6842}
6843
6844#endif /* IN_RING3 */
6845
6846/**
6847 * @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6848 */
6849DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6850{
6851 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6852}
6853
6854/**
6855 * @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6856 */
6857DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6858{
6859 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6860}
6861
6862/**
6863 * @copydoc PDMDEVHLPR3::pfnTimerFromNano
6864 */
6865DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6866{
6867 return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6868}
6869
6870/**
6871 * @copydoc PDMDEVHLPR3::pfnTimerGet
6872 */
6873DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6874{
6875 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6876}
6877
6878/**
6879 * @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6880 */
6881DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6882{
6883 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6884}
6885
6886/**
6887 * @copydoc PDMDEVHLPR3::pfnTimerGetNano
6888 */
6889DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6890{
6891 return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6892}
6893
6894/**
6895 * @copydoc PDMDEVHLPR3::pfnTimerIsActive
6896 */
6897DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6898{
6899 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6900}
6901
6902/**
6903 * @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6904 */
6905DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6906{
6907 return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6908}
6909
6910/**
6911 * @copydoc PDMDEVHLPR3::pfnTimerLockClock
6912 */
6913DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6914{
6915 return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6916}
6917
6918/**
6919 * @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6920 */
6921DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6922{
6923 return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6924}
6925
6926/**
6927 * @copydoc PDMDEVHLPR3::pfnTimerSet
6928 */
6929DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6930{
6931 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6932}
6933
6934/**
6935 * @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6936 */
6937DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6938{
6939 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6940}
6941
6942/**
6943 * @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6944 */
6945DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6946{
6947 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6948}
6949
6950/**
6951 * @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6952 */
6953DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6954{
6955 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6956}
6957
6958/**
6959 * @copydoc PDMDEVHLPR3::pfnTimerSetNano
6960 */
6961DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6962{
6963 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6964}
6965
6966/**
6967 * @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6968 */
6969DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6970{
6971 return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6972}
6973
6974/**
6975 * @copydoc PDMDEVHLPR3::pfnTimerStop
6976 */
6977DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6978{
6979 return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6980}
6981
6982/**
6983 * @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6984 */
6985DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6986{
6987 pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6988}
6989
6990/**
6991 * @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6992 */
6993DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6994{
6995 pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6996}
6997
6998#ifdef IN_RING3
6999
7000/**
7001 * @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
7002 */
7003DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7004{
7005 return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
7006}
7007
7008/**
7009 * @copydoc PDMDEVHLPR3::pfnTimerSave
7010 */
7011DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7012{
7013 return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
7014}
7015
7016/**
7017 * @copydoc PDMDEVHLPR3::pfnTimerLoad
7018 */
7019DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7020{
7021 return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
7022}
7023
7024/**
7025 * @copydoc PDMDEVHLPR3::pfnTimerDestroy
7026 */
7027DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7028{
7029 return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
7030}
7031
7032/**
7033 * @copydoc PDMDEVHLPR3::pfnTMUtcNow
7034 */
7035DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
7036{
7037 return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
7038}
7039
7040#endif
7041
7042/**
7043 * Read physical memory - unknown data usage.
7044 *
7045 * @returns VINF_SUCCESS (for now).
7046 * @param pDevIns The device instance.
7047 * @param GCPhys Physical address start reading from.
7048 * @param pvBuf Where to put the read bits.
7049 * @param cbRead How many bytes to read.
7050 * @thread Any thread, but the call may involve the emulation thread.
7051 */
7052DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7053{
7054 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7055}
7056
7057/**
7058 * Write to physical memory - unknown data usage.
7059 *
7060 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7061 * @param pDevIns The device instance.
7062 * @param GCPhys Physical address to write to.
7063 * @param pvBuf What to write.
7064 * @param cbWrite How many bytes to write.
7065 * @thread Any thread, but the call may involve the emulation thread.
7066 */
7067DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7068{
7069 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7070}
7071
7072/**
7073 * Read physical memory - reads meta data processed by the device.
7074 *
7075 * @returns VINF_SUCCESS (for now).
7076 * @param pDevIns The device instance.
7077 * @param GCPhys Physical address start reading from.
7078 * @param pvBuf Where to put the read bits.
7079 * @param cbRead How many bytes to read.
7080 * @thread Any thread, but the call may involve the emulation thread.
7081 */
7082DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7083{
7084 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7085}
7086
7087/**
7088 * Write to physical memory - written data was created/altered by the device.
7089 *
7090 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7091 * @param pDevIns The device instance.
7092 * @param GCPhys Physical address to write to.
7093 * @param pvBuf What to write.
7094 * @param cbWrite How many bytes to write.
7095 * @thread Any thread, but the call may involve the emulation thread.
7096 */
7097DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7098{
7099 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7100}
7101
7102/**
7103 * Read physical memory - read data will not be touched by the device.
7104 *
7105 * @returns VINF_SUCCESS (for now).
7106 * @param pDevIns The device instance.
7107 * @param GCPhys Physical address start reading from.
7108 * @param pvBuf Where to put the read bits.
7109 * @param cbRead How many bytes to read.
7110 * @thread Any thread, but the call may involve the emulation thread.
7111 */
7112DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7113{
7114 return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7115}
7116
7117/**
7118 * Write to physical memory - written data was not touched/created by the device.
7119 *
7120 * @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7121 * @param pDevIns The device instance.
7122 * @param GCPhys Physical address to write to.
7123 * @param pvBuf What to write.
7124 * @param cbWrite How many bytes to write.
7125 * @thread Any thread, but the call may involve the emulation thread.
7126 */
7127DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7128{
7129 return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7130}
7131
7132#ifdef IN_RING3
7133
7134/**
7135 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
7136 */
7137DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
7138{
7139 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
7140}
7141
7142/**
7143 * @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
7144 */
7145DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
7146 PPGMPAGEMAPLOCK pLock)
7147{
7148 return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
7149}
7150
7151/**
7152 * @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
7153 */
7154DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
7155{
7156 pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
7157}
7158
7159/**
7160 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
7161 */
7162DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7163 uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
7164{
7165 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7166}
7167
7168/**
7169 * @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
7170 */
7171DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7172 uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
7173{
7174 return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7175}
7176
7177/**
7178 * @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
7179 */
7180DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
7181{
7182 pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
7183}
7184
7185/**
7186 * @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
7187 */
7188DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
7189{
7190 return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
7191}
7192
7193/**
7194 * @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
7195 */
7196DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
7197{
7198 return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
7199}
7200
7201/**
7202 * @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
7203 */
7204DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
7205{
7206 return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
7207}
7208
7209/**
7210 * @copydoc PDMDEVHLPR3::pfnCpuGetGuestScalableBusFrequency
7211 */
7212DECLINLINE(uint64_t) PDMDevHlpCpuGetGuestScalableBusFrequency(PPDMDEVINS pDevIns)
7213{
7214 return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestScalableBusFrequency(pDevIns);
7215}
7216
7217/**
7218 * @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
7219 */
7220DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth)
7221{
7222 pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
7223}
7224
7225/**
7226 * @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
7227 */
7228DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
7229{
7230 return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
7231}
7232
7233/**
7234 * @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
7235 */
7236DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
7237{
7238 return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
7239}
7240
7241/**
7242 * @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
7243 */
7244DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
7245{
7246 return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
7247}
7248
7249/**
7250 * @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
7251 */
7252DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
7253{
7254 return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
7255}
7256
7257/**
7258 * @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
7259 */
7260DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
7261{
7262 return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
7263}
7264
7265/**
7266 * Allocating string printf.
7267 *
7268 * @returns Pointer to the string.
7269 * @param pDevIns The device instance.
7270 * @param enmTag The statistics tag.
7271 * @param pszFormat The format string.
7272 * @param ... Format arguments.
7273 */
7274DECLINLINE(char *) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char *pszFormat, ...)
7275{
7276 va_list va;
7277 va_start(va, pszFormat);
7278 char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
7279 va_end(va);
7280
7281 return psz;
7282}
7283
7284/**
7285 * @copydoc PDMDEVHLPR3::pfnMMHeapFree
7286 */
7287DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7288{
7289 pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7290}
7291
7292/**
7293 * @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7294 */
7295DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7296{
7297 return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7298}
7299
7300/**
7301 * @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7302 */
7303DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7304{
7305 return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7306}
7307
7308/**
7309 * @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7310 */
7311DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7312{
7313 return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7314}
7315#endif /* IN_RING3 */
7316
7317/**
7318 * @copydoc PDMDEVHLPR3::pfnVMState
7319 */
7320DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7321{
7322 return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7323}
7324
7325#ifdef IN_RING3
7326
7327/**
7328 * @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7329 */
7330DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7331{
7332 return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7333}
7334
7335/**
7336 * Set the VM error message
7337 *
7338 * @returns rc.
7339 * @param pDevIns The device instance.
7340 * @param rc VBox status code.
7341 * @param SRC_POS Use RT_SRC_POS.
7342 * @param pszFormat Error message format string.
7343 * @param ... Error message arguments.
7344 * @sa VMSetError
7345 */
7346DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7347 const char *pszFormat, ...)
7348{
7349 va_list va;
7350 va_start(va, pszFormat);
7351 pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7352 va_end(va);
7353 return rc;
7354}
7355
7356/**
7357 * Set the VM runtime error message
7358 *
7359 * @returns VBox status code.
7360 * @param pDevIns The device instance.
7361 * @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7362 * @param pszErrorId Error ID string.
7363 * @param pszFormat Error message format string.
7364 * @param ... Error message arguments.
7365 * @sa VMSetRuntimeError
7366 */
7367DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7368 const char *pszFormat, ...)
7369{
7370 va_list va;
7371 int rc;
7372 va_start(va, pszFormat);
7373 rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7374 va_end(va);
7375 return rc;
7376}
7377
7378/**
7379 * @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7380 */
7381DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7382{
7383 return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7384}
7385
7386/**
7387 * @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7388 */
7389DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7390{
7391 return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7392}
7393
7394/**
7395 * Convenience wrapper for VMR3ReqCallU.
7396 *
7397 * This assumes (1) you're calling a function that returns an VBox status code
7398 * and that you do not wish to wait for it to complete.
7399 *
7400 * @returns VBox status code returned by VMR3ReqCallVU.
7401 *
7402 * @param pDevIns The device instance.
7403 * @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7404 * one of the following special values:
7405 * VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7406 * @param pfnFunction Pointer to the function to call.
7407 * @param cArgs Number of arguments following in the ellipsis.
7408 * @param ... Argument list.
7409 *
7410 * @remarks See remarks on VMR3ReqCallVU.
7411 */
7412DECLINLINE(int) PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7413{
7414 va_list Args;
7415 va_start(Args, cArgs);
7416 int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7417 va_end(Args);
7418 return rc;
7419}
7420
7421/**
7422 * Convenience wrapper for VMR3ReqCallU.
7423 *
7424 * This assumes (1) you're calling a function that returns void, (2) that you
7425 * wish to wait for ever for it to return, and (3) that it's priority request
7426 * that can be safely be handled during async suspend and power off.
7427 *
7428 * @returns VBox status code of VMR3ReqCallVU.
7429 *
7430 * @param pDevIns The device instance.
7431 * @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7432 * one of the following special values:
7433 * VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7434 * @param pfnFunction Pointer to the function to call.
7435 * @param cArgs Number of arguments following in the ellipsis.
7436 * @param ... Argument list.
7437 *
7438 * @remarks See remarks on VMR3ReqCallVU.
7439 */
7440DECLINLINE(int) PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7441{
7442 va_list Args;
7443 va_start(Args, cArgs);
7444 int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7445 va_end(Args);
7446 return rc;
7447}
7448
7449#endif /* IN_RING3 */
7450
7451/**
7452 * VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7453 *
7454 * @returns VBox status code which must be passed up to the VMM. This will be
7455 * VINF_SUCCESS in non-strict builds.
7456 * @param pDevIns The device instance.
7457 * @param SRC_POS Use RT_SRC_POS.
7458 * @param pszFormat Message. (optional)
7459 * @param ... Message parameters.
7460 */
7461DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7462{
7463#ifdef VBOX_STRICT
7464# ifdef IN_RING3
7465 int rc;
7466 va_list args;
7467 va_start(args, pszFormat);
7468 rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7469 va_end(args);
7470 return rc;
7471# else
7472 NOREF(pDevIns);
7473 NOREF(pszFile);
7474 NOREF(iLine);
7475 NOREF(pszFunction);
7476 NOREF(pszFormat);
7477 return VINF_EM_DBG_STOP;
7478# endif
7479#else
7480 NOREF(pDevIns);
7481 NOREF(pszFile);
7482 NOREF(iLine);
7483 NOREF(pszFunction);
7484 NOREF(pszFormat);
7485 return VINF_SUCCESS;
7486#endif
7487}
7488
7489#ifdef IN_RING3
7490
7491/**
7492 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7493 */
7494DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7495{
7496 return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7497}
7498
7499/**
7500 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7501 */
7502DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7503{
7504 return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7505}
7506
7507/**
7508 * @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7509 */
7510DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7511{
7512 return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7513}
7514
7515/**
7516 * @copydoc PDMDEVHLPR3::pfnDBGFReportBugCheck
7517 */
7518DECLINLINE(VBOXSTRICTRC) PDMDevHlpDBGFReportBugCheck(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
7519 uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4)
7520{
7521 return pDevIns->pHlpR3->pfnDBGFReportBugCheck(pDevIns, enmEvent, uBugCheck, uP1, uP2, uP3, uP4);
7522}
7523
7524/**
7525 * @copydoc PDMDEVHLPR3::pfnDBGFCoreWrite
7526 */
7527DECLINLINE(int) PDMDevHlpDBGFCoreWrite(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile)
7528{
7529 return pDevIns->pHlpR3->pfnDBGFCoreWrite(pDevIns, pszFilename, fReplaceFile);
7530}
7531
7532/**
7533 * @copydoc PDMDEVHLPR3::pfnDBGFInfoLogHlp
7534 */
7535DECLINLINE(PCDBGFINFOHLP) PDMDevHlpDBGFInfoLogHlp(PPDMDEVINS pDevIns)
7536{
7537 return pDevIns->pHlpR3->pfnDBGFInfoLogHlp(pDevIns);
7538}
7539
7540/**
7541 * @copydoc PDMDEVHLPR3::pfnDBGFRegNmQueryU64
7542 */
7543DECLINLINE(int) PDMDevHlpDBGFRegNmQueryU64(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char *pszReg, uint64_t *pu64)
7544{
7545 return pDevIns->pHlpR3->pfnDBGFRegNmQueryU64(pDevIns, idDefCpu, pszReg, pu64);
7546}
7547
7548 /**
7549 * Format a set of registers.
7550 *
7551 * This is restricted to registers from one CPU, that specified by @a idCpu.
7552 *
7553 * @returns VBox status code.
7554 * @param pDevIns The device instance.
7555 * @param idCpu The CPU ID of any CPU registers that may be
7556 * printed, pass VMCPUID_ANY if not applicable.
7557 * @param pszBuf The output buffer.
7558 * @param cbBuf The size of the output buffer.
7559 * @param pszFormat The format string. Register names are given by
7560 * %VR{name}, they take no arguments.
7561 * @param ... Argument list.
7562 */
7563DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpDBGFRegPrintf(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
7564 const char *pszFormat, ...)
7565{
7566 va_list Args;
7567 va_start(Args, pszFormat);
7568 int rc = pDevIns->pHlpR3->pfnDBGFRegPrintfV(pDevIns, idCpu, pszBuf, cbBuf, pszFormat, Args);
7569 va_end(Args);
7570 return rc;
7571}
7572
7573/**
7574 * @copydoc PDMDEVHLPR3::pfnSTAMRegister
7575 */
7576DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc)
7577{
7578 pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7579}
7580
7581/**
7582 * Same as pfnSTAMRegister except that the name is specified in a
7583 * RTStrPrintf like fashion.
7584 *
7585 * @returns VBox status.
7586 * @param pDevIns Device instance of the DMA.
7587 * @param pvSample Pointer to the sample.
7588 * @param enmType Sample type. This indicates what pvSample is
7589 * pointing at.
7590 * @param enmVisibility Visibility type specifying whether unused
7591 * statistics should be visible or not.
7592 * @param enmUnit Sample unit.
7593 * @param pszDesc Sample description.
7594 * @param pszName Sample name format string, unix path style. If
7595 * this does not start with a '/', the default
7596 * prefix will be prepended, otherwise it will be
7597 * used as-is.
7598 * @param ... Arguments to the format string.
7599 */
7600DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7601 STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7602 const char *pszDesc, const char *pszName, ...)
7603{
7604 va_list va;
7605 va_start(va, pszName);
7606 pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7607 va_end(va);
7608}
7609
7610/**
7611 * @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7612 */
7613DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7614{
7615 return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7616}
7617
7618/**
7619 * Registers the device with the default PCI bus.
7620 *
7621 * @returns VBox status code.
7622 * @param pDevIns The device instance.
7623 * @param pPciDev The PCI device structure.
7624 * This must be kept in the instance data.
7625 * The PCI configuration must be initialized before registration.
7626 */
7627DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7628{
7629 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /*fFlags*/,
7630 PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7631}
7632
7633/**
7634 * @copydoc PDMDEVHLPR3::pfnPCIRegister
7635 */
7636DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7637 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7638{
7639 return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7640}
7641
7642/**
7643 * Initialize MSI emulation support for the first PCI device.
7644 *
7645 * @returns VBox status code.
7646 * @param pDevIns The device instance.
7647 * @param pMsiReg MSI emulation registration structure.
7648 */
7649DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7650{
7651 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7652}
7653
7654/**
7655 * @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7656 */
7657DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7658{
7659 return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7660}
7661
7662/**
7663 * Registers a I/O port region for the default PCI device.
7664 *
7665 * @returns VBox status code.
7666 * @param pDevIns The device instance.
7667 * @param iRegion The region number.
7668 * @param cbRegion Size of the region.
7669 * @param hIoPorts Handle to the I/O port region.
7670 */
7671DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7672{
7673 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7674 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7675}
7676
7677/**
7678 * Registers a I/O port region for the default PCI device, custom map/unmap.
7679 *
7680 * @returns VBox status code.
7681 * @param pDevIns The device instance.
7682 * @param iRegion The region number.
7683 * @param cbRegion Size of the region.
7684 * @param pfnMapUnmap Callback for doing the mapping, optional. The
7685 * callback will be invoked holding only the PDM lock.
7686 * The device lock will _not_ be taken (due to lock
7687 * order).
7688 */
7689DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7690 PFNPCIIOREGIONMAP pfnMapUnmap)
7691{
7692 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7693 PDMPCIDEV_IORGN_F_NO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7694 UINT64_MAX, pfnMapUnmap);
7695}
7696
7697/**
7698 * Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7699 * and registering an I/O port region for the default PCI device.
7700 *
7701 * @returns VBox status code.
7702 * @param pDevIns The device instance to register the ports with.
7703 * @param cPorts The count of I/O ports in the region (the size).
7704 * @param iPciRegion The PCI device region.
7705 * @param pfnOut Pointer to function which is gonna handle OUT
7706 * operations. Optional.
7707 * @param pfnIn Pointer to function which is gonna handle IN operations.
7708 * Optional.
7709 * @param pvUser User argument to pass to the callbacks.
7710 * @param pszDesc Pointer to description string. This must not be freed.
7711 * @param paExtDescs Extended per-port descriptions, optional. Partial range
7712 * coverage is allowed. This must not be freed.
7713 * @param phIoPorts Where to return the I/O port range handle.
7714 *
7715 */
7716DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7717 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7718 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7719
7720{
7721 int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /*fFlags*/, pDevIns->apPciDevs[0], iPciRegion << 16,
7722 pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7723 if (RT_SUCCESS(rc))
7724 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7725 PDMPCIDEV_IORGN_F_IOPORT_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7726 *phIoPorts, NULL /*pfnMapUnmap*/);
7727 return rc;
7728}
7729
7730/**
7731 * Registers an MMIO region for the default PCI device.
7732 *
7733 * @returns VBox status code.
7734 * @param pDevIns The device instance.
7735 * @param iRegion The region number.
7736 * @param cbRegion Size of the region.
7737 * @param enmType PCI_ADDRESS_SPACE_MEM or
7738 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7739 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7740 * @param hMmioRegion Handle to the MMIO region.
7741 * @param pfnMapUnmap Callback for doing the mapping, optional. The
7742 * callback will be invoked holding only the PDM lock.
7743 * The device lock will _not_ be taken (due to lock
7744 * order).
7745 */
7746DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7747 IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7748{
7749 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7750 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7751 hMmioRegion, pfnMapUnmap);
7752}
7753
7754/**
7755 * Registers an MMIO region for the default PCI device, extended version.
7756 *
7757 * @returns VBox status code.
7758 * @param pDevIns The device instance.
7759 * @param pPciDev The PCI device structure.
7760 * @param iRegion The region number.
7761 * @param cbRegion Size of the region.
7762 * @param enmType PCI_ADDRESS_SPACE_MEM or
7763 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7764 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7765 * @param hMmioRegion Handle to the MMIO region.
7766 * @param pfnMapUnmap Callback for doing the mapping, optional. The
7767 * callback will be invoked holding only the PDM lock.
7768 * The device lock will _not_ be taken (due to lock
7769 * order).
7770 */
7771DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7772 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7773 PFNPCIIOREGIONMAP pfnMapUnmap)
7774{
7775 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7776 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7777 hMmioRegion, pfnMapUnmap);
7778}
7779
7780/**
7781 * Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7782 * and registering an MMIO region for the default PCI device.
7783 *
7784 * @returns VBox status code.
7785 * @param pDevIns The device instance to register the ports with.
7786 * @param cbRegion The size of the region in bytes.
7787 * @param iPciRegion The PCI device region.
7788 * @param enmType PCI_ADDRESS_SPACE_MEM or
7789 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7790 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7791 * @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7792 * @param pfnWrite Pointer to function which is gonna handle Write
7793 * operations.
7794 * @param pfnRead Pointer to function which is gonna handle Read
7795 * operations.
7796 * @param pvUser User argument to pass to the callbacks.
7797 * @param pszDesc Pointer to description string. This must not be freed.
7798 * @param phRegion Where to return the MMIO region handle.
7799 *
7800 */
7801DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7802 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7803 uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7804
7805{
7806 int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7807 pfnWrite, pfnRead, NULL /*pfnFill*/, pvUser, pszDesc, phRegion);
7808 if (RT_SUCCESS(rc))
7809 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7810 PDMPCIDEV_IORGN_F_MMIO_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7811 *phRegion, NULL /*pfnMapUnmap*/);
7812 return rc;
7813}
7814
7815
7816/**
7817 * Registers an MMIO2 region for the default PCI device.
7818 *
7819 * @returns VBox status code.
7820 * @param pDevIns The device instance.
7821 * @param iRegion The region number.
7822 * @param cbRegion Size of the region.
7823 * @param enmType PCI_ADDRESS_SPACE_MEM or
7824 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7825 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7826 * @param hMmio2Region Handle to the MMIO2 region.
7827 */
7828DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7829 PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7830{
7831 return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7832 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7833 hMmio2Region, NULL);
7834}
7835
7836/**
7837 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7838 * and registering an MMIO2 region for the default PCI device, extended edition.
7839 *
7840 * @returns VBox status code.
7841 * @param pDevIns The device instance to register the ports with.
7842 * @param cbRegion The size of the region in bytes.
7843 * @param iPciRegion The PCI device region.
7844 * @param enmType PCI_ADDRESS_SPACE_MEM or
7845 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7846 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7847 * @param pszDesc Pointer to description string. This must not be freed.
7848 * @param ppvMapping Where to store the address of the ring-3 mapping of
7849 * the memory.
7850 * @param phRegion Where to return the MMIO2 region handle.
7851 *
7852 */
7853DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7854 PCIADDRESSSPACE enmType, const char *pszDesc,
7855 void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7856
7857{
7858 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /*fFlags*/,
7859 pszDesc, ppvMapping, phRegion);
7860 if (RT_SUCCESS(rc))
7861 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7862 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7863 *phRegion, NULL /*pfnCallback*/);
7864 return rc;
7865}
7866
7867/**
7868 * Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7869 * and registering an MMIO2 region for the default PCI device.
7870 *
7871 * @returns VBox status code.
7872 * @param pDevIns The device instance to register the ports with.
7873 * @param cbRegion The size of the region in bytes.
7874 * @param iPciRegion The PCI device region.
7875 * @param enmType PCI_ADDRESS_SPACE_MEM or
7876 * PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7877 * PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7878 * @param fMmio2Flags To be defined, must be zero.
7879 * @param pfnMapUnmap Callback for doing the mapping, optional. The
7880 * callback will be invoked holding only the PDM lock.
7881 * The device lock will _not_ be taken (due to lock
7882 * order).
7883 * @param pszDesc Pointer to description string. This must not be freed.
7884 * @param ppvMapping Where to store the address of the ring-3 mapping of
7885 * the memory.
7886 * @param phRegion Where to return the MMIO2 region handle.
7887 *
7888 */
7889DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7890 PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7891 const char *pszDesc, void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7892
7893{
7894 int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7895 pszDesc, ppvMapping, phRegion);
7896 if (RT_SUCCESS(rc))
7897 rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7898 PDMPCIDEV_IORGN_F_MMIO2_HANDLE | PDMPCIDEV_IORGN_F_NEW_STYLE,
7899 *phRegion, pfnMapUnmap);
7900 return rc;
7901}
7902
7903/**
7904 * @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7905 */
7906DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7907 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7908{
7909 return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7910}
7911
7912/**
7913 * @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7914 */
7915DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7916 unsigned cb, uint32_t *pu32Value)
7917{
7918 return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7919}
7920
7921/**
7922 * @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7923 */
7924DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7925 unsigned cb, uint32_t u32Value)
7926{
7927 return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7928}
7929
7930#endif /* IN_RING3 */
7931
7932/**
7933 * Bus master physical memory read from the default PCI device.
7934 *
7935 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7936 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7937 * @param pDevIns The device instance.
7938 * @param GCPhys Physical address start reading from.
7939 * @param pvBuf Where to put the read bits.
7940 * @param cbRead How many bytes to read.
7941 * @thread Any thread, but the call may involve the emulation thread.
7942 */
7943DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7944{
7945 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7946}
7947
7948/**
7949 * Bus master physical memory read - unknown data usage.
7950 *
7951 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7952 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7953 * @param pDevIns The device instance.
7954 * @param pPciDev The PCI device structure. If NULL the default
7955 * PCI device for this device instance is used.
7956 * @param GCPhys Physical address start reading from.
7957 * @param pvBuf Where to put the read bits.
7958 * @param cbRead How many bytes to read.
7959 * @thread Any thread, but the call may involve the emulation thread.
7960 */
7961DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7962{
7963 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7964}
7965
7966/**
7967 * Bus master physical memory read from the default PCI device.
7968 *
7969 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7970 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7971 * @param pDevIns The device instance.
7972 * @param GCPhys Physical address start reading from.
7973 * @param pvBuf Where to put the read bits.
7974 * @param cbRead How many bytes to read.
7975 * @thread Any thread, but the call may involve the emulation thread.
7976 */
7977DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7978{
7979 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7980}
7981
7982/**
7983 * Bus master physical memory read - reads meta data processed by the device.
7984 *
7985 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7986 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
7987 * @param pDevIns The device instance.
7988 * @param pPciDev The PCI device structure. If NULL the default
7989 * PCI device for this device instance is used.
7990 * @param GCPhys Physical address start reading from.
7991 * @param pvBuf Where to put the read bits.
7992 * @param cbRead How many bytes to read.
7993 * @thread Any thread, but the call may involve the emulation thread.
7994 */
7995DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7996{
7997 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7998}
7999
8000/**
8001 * Bus master physical memory read from the default PCI device - read data will not be touched by the device.
8002 *
8003 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8004 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8005 * @param pDevIns The device instance.
8006 * @param GCPhys Physical address start reading from.
8007 * @param pvBuf Where to put the read bits.
8008 * @param cbRead How many bytes to read.
8009 * @thread Any thread, but the call may involve the emulation thread.
8010 */
8011DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8012{
8013 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8014}
8015
8016/**
8017 * Bus master physical memory read - read data will not be touched by the device.
8018 *
8019 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8020 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8021 * @param pDevIns The device instance.
8022 * @param pPciDev The PCI device structure. If NULL the default
8023 * PCI device for this device instance is used.
8024 * @param GCPhys Physical address start reading from.
8025 * @param pvBuf Where to put the read bits.
8026 * @param cbRead How many bytes to read.
8027 * @thread Any thread, but the call may involve the emulation thread.
8028 */
8029DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8030{
8031 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8032}
8033
8034/**
8035 * Bus master physical memory write from the default PCI device - unknown data usage.
8036 *
8037 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8038 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8039 * @param pDevIns The device instance.
8040 * @param GCPhys Physical address to write to.
8041 * @param pvBuf What to write.
8042 * @param cbWrite How many bytes to write.
8043 * @thread Any thread, but the call may involve the emulation thread.
8044 */
8045DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8046{
8047 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8048}
8049
8050/**
8051 * Bus master physical memory write - unknown data usage.
8052 *
8053 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8054 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8055 * @param pDevIns The device instance.
8056 * @param pPciDev The PCI device structure. If NULL the default
8057 * PCI device for this device instance is used.
8058 * @param GCPhys Physical address to write to.
8059 * @param pvBuf What to write.
8060 * @param cbWrite How many bytes to write.
8061 * @thread Any thread, but the call may involve the emulation thread.
8062 */
8063DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8064{
8065 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8066}
8067
8068/**
8069 * Bus master physical memory write from the default PCI device.
8070 *
8071 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8072 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8073 * @param pDevIns The device instance.
8074 * @param GCPhys Physical address to write to.
8075 * @param pvBuf What to write.
8076 * @param cbWrite How many bytes to write.
8077 * @thread Any thread, but the call may involve the emulation thread.
8078 */
8079DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8080{
8081 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8082}
8083
8084/**
8085 * Bus master physical memory write - written data was created/altered by the device.
8086 *
8087 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8088 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8089 * @param pDevIns The device instance.
8090 * @param pPciDev The PCI device structure. If NULL the default
8091 * PCI device for this device instance is used.
8092 * @param GCPhys Physical address to write to.
8093 * @param pvBuf What to write.
8094 * @param cbWrite How many bytes to write.
8095 * @thread Any thread, but the call may involve the emulation thread.
8096 */
8097DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8098{
8099 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8100}
8101
8102/**
8103 * Bus master physical memory write from the default PCI device.
8104 *
8105 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8106 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8107 * @param pDevIns The device instance.
8108 * @param GCPhys Physical address to write to.
8109 * @param pvBuf What to write.
8110 * @param cbWrite How many bytes to write.
8111 * @thread Any thread, but the call may involve the emulation thread.
8112 */
8113DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8114{
8115 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8116}
8117
8118/**
8119 * Bus master physical memory write - written data was not touched/created by the device.
8120 *
8121 * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8122 * VERR_EM_MEMORY. The informational status shall NOT be propagated!
8123 * @param pDevIns The device instance.
8124 * @param pPciDev The PCI device structure. If NULL the default
8125 * PCI device for this device instance is used.
8126 * @param GCPhys Physical address to write to.
8127 * @param pvBuf What to write.
8128 * @param cbWrite How many bytes to write.
8129 * @thread Any thread, but the call may involve the emulation thread.
8130 */
8131DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8132{
8133 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8134}
8135
8136#ifdef IN_RING3
8137/**
8138 * @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
8139 */
8140DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8141 void **ppv, PPGMPAGEMAPLOCK pLock)
8142{
8143 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8144}
8145
8146/**
8147 * @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
8148 */
8149DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8150 void const **ppv, PPGMPAGEMAPLOCK pLock)
8151{
8152 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8153}
8154
8155/**
8156 * @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
8157 */
8158DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8159 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
8160 PPGMPAGEMAPLOCK paLocks)
8161{
8162 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
8163 paLocks);
8164}
8165
8166/**
8167 * @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
8168 */
8169DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8170 PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
8171 PPGMPAGEMAPLOCK paLocks)
8172{
8173 return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
8174 papvPages, paLocks);
8175}
8176#endif /* IN_RING3 */
8177
8178/**
8179 * Sets the IRQ for the default PCI device.
8180 *
8181 * @param pDevIns The device instance.
8182 * @param iIrq IRQ number to set.
8183 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
8184 * @thread Any thread, but will involve the emulation thread.
8185 */
8186DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8187{
8188 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8189}
8190
8191/**
8192 * @copydoc PDMDEVHLPR3::pfnPCISetIrq
8193 */
8194DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8195{
8196 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8197}
8198
8199/**
8200 * Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
8201 * the request when not called from EMT.
8202 *
8203 * @param pDevIns The device instance.
8204 * @param iIrq IRQ number to set.
8205 * @param iLevel IRQ level.
8206 * @thread Any thread, but will involve the emulation thread.
8207 */
8208DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8209{
8210 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8211}
8212
8213/**
8214 * @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
8215 */
8216DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8217{
8218 pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8219}
8220
8221/**
8222 * @copydoc PDMDEVHLPR3::pfnISASetIrq
8223 */
8224DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8225{
8226 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8227}
8228
8229/**
8230 * @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
8231 */
8232DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8233{
8234 pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8235}
8236
8237#ifdef IN_RING3
8238
8239/**
8240 * @copydoc PDMDEVHLPR3::pfnDriverAttach
8241 */
8242DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc)
8243{
8244 return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
8245}
8246
8247/**
8248 * @copydoc PDMDEVHLPR3::pfnDriverDetach
8249 */
8250DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
8251{
8252 return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
8253}
8254
8255/**
8256 * @copydoc PDMDEVHLPR3::pfnDriverReconfigure
8257 */
8258DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
8259 const char * const *papszDrivers, PCFGMNODE *papConfigs, uint32_t fFlags)
8260{
8261 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
8262}
8263
8264/**
8265 * Reconfigures with a single driver reattachement, no config, noflags.
8266 * @sa PDMDevHlpDriverReconfigure
8267 */
8268DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
8269{
8270 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
8271}
8272
8273/**
8274 * Reconfigures with a two drivers reattachement, no config, noflags.
8275 * @sa PDMDevHlpDriverReconfigure
8276 */
8277DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0, const char *pszDriver1)
8278{
8279 char const * apszDrivers[2];
8280 apszDrivers[0] = pszDriver0;
8281 apszDrivers[1] = pszDriver1;
8282 return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
8283}
8284
8285/**
8286 * @copydoc PDMDEVHLPR3::pfnQueueCreate
8287 */
8288DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
8289 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PDMQUEUEHANDLE *phQueue)
8290{
8291 return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
8292}
8293
8294#endif /* IN_RING3 */
8295
8296/**
8297 * @copydoc PDMDEVHLPR3::pfnQueueAlloc
8298 */
8299DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8300{
8301 return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
8302}
8303
8304/**
8305 * @copydoc PDMDEVHLPR3::pfnQueueInsert
8306 */
8307DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
8308{
8309 pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
8310}
8311
8312/**
8313 * @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
8314 */
8315DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8316{
8317 return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
8318}
8319
8320#ifdef IN_RING3
8321/**
8322 * @copydoc PDMDEVHLPR3::pfnTaskCreate
8323 */
8324DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
8325 PFNPDMTASKDEV pfnCallback, void *pvUser, PDMTASKHANDLE *phTask)
8326{
8327 return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
8328}
8329#endif
8330
8331/**
8332 * @copydoc PDMDEVHLPR3::pfnTaskTrigger
8333 */
8334DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
8335{
8336 return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
8337}
8338
8339#ifdef IN_RING3
8340
8341/**
8342 * @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8343 */
8344DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8345{
8346 return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8347}
8348
8349/**
8350 * @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8351 */
8352DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8353{
8354 return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8355}
8356
8357#endif /* IN_RING3 */
8358
8359/**
8360 * @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8361 */
8362DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8363{
8364 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8365}
8366
8367/**
8368 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8369 */
8370DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8371{
8372 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8373}
8374
8375/**
8376 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8377 */
8378DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8379{
8380 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8381}
8382
8383/**
8384 * @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8385 */
8386DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8387{
8388 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8389}
8390
8391/**
8392 * @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8393 */
8394DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8395{
8396 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8397}
8398
8399#ifdef IN_RING3
8400
8401/**
8402 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8403 */
8404DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8405{
8406 return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8407}
8408
8409/**
8410 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8411 */
8412DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8413{
8414 return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8415}
8416
8417#endif /* IN_RING3 */
8418
8419/**
8420 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8421 */
8422DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8423{
8424 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8425}
8426
8427/**
8428 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8429 */
8430DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8431{
8432 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8433}
8434
8435/**
8436 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8437 */
8438DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8439{
8440 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8441}
8442
8443/**
8444 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8445 */
8446DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8447{
8448 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8449}
8450
8451/**
8452 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8453 */
8454DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8455{
8456 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8457}
8458
8459/**
8460 * @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8461 */
8462DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8463{
8464 return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8465}
8466
8467#ifdef IN_RING3
8468
8469/**
8470 * Initializes a PDM critical section.
8471 *
8472 * The PDM critical sections are derived from the IPRT critical sections, but
8473 * works in RC and R0 as well.
8474 *
8475 * @returns VBox status code.
8476 * @param pDevIns The device instance.
8477 * @param pCritSect Pointer to the critical section.
8478 * @param SRC_POS Use RT_SRC_POS.
8479 * @param pszNameFmt Format string for naming the critical section.
8480 * For statistics and lock validation.
8481 * @param ... Arguments for the format string.
8482 */
8483DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8484 const char *pszNameFmt, ...)
8485{
8486 int rc;
8487 va_list va;
8488 va_start(va, pszNameFmt);
8489 rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8490 va_end(va);
8491 return rc;
8492}
8493
8494#endif /* IN_RING3 */
8495
8496/**
8497 * @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8498 */
8499DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8500{
8501 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8502}
8503
8504/**
8505 * @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8506 */
8507DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8508{
8509 return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8510}
8511
8512/**
8513 * Enters a PDM critical section.
8514 *
8515 * @returns VINF_SUCCESS if entered successfully.
8516 * @returns rcBusy when encountering a busy critical section in RC/R0.
8517 * @retval VERR_SEM_DESTROYED if the critical section is delete before or
8518 * during the operation.
8519 *
8520 * @param pDevIns The device instance.
8521 * @param pCritSect The PDM critical section to enter.
8522 * @param rcBusy The status code to return when we're in RC or R0
8523 * and the section is busy. Pass VINF_SUCCESS to
8524 * acquired the critical section thru a ring-3
8525 * call if necessary.
8526 *
8527 * @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8528 * possible failures in ring-0 or at least apply
8529 * PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8530 * function.
8531 *
8532 * @sa PDMCritSectEnter
8533 */
8534DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8535{
8536 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8537}
8538
8539/**
8540 * Enters a PDM critical section, with location information for debugging.
8541 *
8542 * @returns VINF_SUCCESS if entered successfully.
8543 * @returns rcBusy when encountering a busy critical section in RC/R0.
8544 * @retval VERR_SEM_DESTROYED if the critical section is delete before or
8545 * during the operation.
8546 *
8547 * @param pDevIns The device instance.
8548 * @param pCritSect The PDM critical section to enter.
8549 * @param rcBusy The status code to return when we're in RC or R0
8550 * and the section is busy. Pass VINF_SUCCESS to
8551 * acquired the critical section thru a ring-3
8552 * call if necessary.
8553 * @param uId Some kind of locking location ID. Typically a
8554 * return address up the stack. Optional (0).
8555 * @param SRC_POS The source position where to lock is being
8556 * acquired from. Optional.
8557 * @sa PDMCritSectEnterDebug
8558 */
8559DECLINLINE(DECL_CHECK_RETURN(int))
8560PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8561{
8562 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8563}
8564
8565/**
8566 * Try enter a critical section.
8567 *
8568 * @retval VINF_SUCCESS on success.
8569 * @retval VERR_SEM_BUSY if the critsect was owned.
8570 * @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8571 * @retval VERR_SEM_DESTROYED if the critical section is delete before or
8572 * during the operation.
8573 *
8574 * @param pDevIns The device instance.
8575 * @param pCritSect The critical section.
8576 * @sa PDMCritSectTryEnter
8577 */
8578DECLINLINE(DECL_CHECK_RETURN(int))
8579PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8580{
8581 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8582}
8583
8584/**
8585 * Try enter a critical section, with location information for debugging.
8586 *
8587 * @retval VINF_SUCCESS on success.
8588 * @retval VERR_SEM_BUSY if the critsect was owned.
8589 * @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8590 * @retval VERR_SEM_DESTROYED if the critical section is delete before or
8591 * during the operation.
8592 *
8593 * @param pDevIns The device instance.
8594 * @param pCritSect The critical section.
8595 * @param uId Some kind of locking location ID. Typically a
8596 * return address up the stack. Optional (0).
8597 * @param SRC_POS The source position where to lock is being
8598 * acquired from. Optional.
8599 * @sa PDMCritSectTryEnterDebug
8600 */
8601DECLINLINE(DECL_CHECK_RETURN(int))
8602PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8603{
8604 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8605}
8606
8607/**
8608 * Leaves a critical section entered with PDMCritSectEnter().
8609 *
8610 * @returns Indication whether we really exited the critical section.
8611 * @retval VINF_SUCCESS if we really exited.
8612 * @retval VINF_SEM_NESTED if we only reduced the nesting count.
8613 * @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8614 *
8615 * @param pDevIns The device instance.
8616 * @param pCritSect The PDM critical section to leave.
8617 * @sa PDMCritSectLeave
8618 */
8619DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8620{
8621 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8622}
8623
8624/**
8625 * @see PDMCritSectIsOwner
8626 */
8627DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8628{
8629 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8630}
8631
8632/**
8633 * @see PDMCritSectIsInitialized
8634 */
8635DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8636{
8637 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8638}
8639
8640/**
8641 * @see PDMCritSectHasWaiters
8642 */
8643DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8644{
8645 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8646}
8647
8648/**
8649 * @see PDMCritSectGetRecursion
8650 */
8651DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8652{
8653 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8654}
8655
8656#if defined(IN_RING3) || defined(IN_RING0)
8657/**
8658 * @see PDMHCCritSectScheduleExitEvent
8659 */
8660DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8661{
8662 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8663}
8664#endif
8665
8666/* Strict build: Remap the two enter calls to the debug versions. */
8667#ifdef VBOX_STRICT
8668# ifdef IPRT_INCLUDED_asm_h
8669# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8670# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8671# else
8672# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8673# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8674# endif
8675#endif
8676
8677#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
8678
8679/**
8680 * Deletes the critical section.
8681 *
8682 * @returns VBox status code.
8683 * @param pDevIns The device instance.
8684 * @param pCritSect The PDM critical section to destroy.
8685 * @sa PDMR3CritSectDelete
8686 */
8687DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8688{
8689 return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8690}
8691
8692/**
8693 * Initializes a PDM read/write critical section.
8694 *
8695 * The PDM read/write critical sections are derived from the IPRT critical
8696 * sections, but works in RC and R0 as well.
8697 *
8698 * @returns VBox status code.
8699 * @param pDevIns The device instance.
8700 * @param pCritSect Pointer to the read/write critical section.
8701 * @param SRC_POS Use RT_SRC_POS.
8702 * @param pszNameFmt Format string for naming the critical section.
8703 * For statistics and lock validation.
8704 * @param ... Arguments for the format string.
8705 */
8706DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8707 const char *pszNameFmt, ...)
8708{
8709 int rc;
8710 va_list va;
8711 va_start(va, pszNameFmt);
8712 rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8713 va_end(va);
8714 return rc;
8715}
8716
8717/**
8718 * Deletes the read/write critical section.
8719 *
8720 * @returns VBox status code.
8721 * @param pDevIns The device instance.
8722 * @param pCritSect The PDM read/write critical section to destroy.
8723 * @sa PDMR3CritSectRwDelete
8724 */
8725DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8726{
8727 return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8728}
8729
8730#endif /* IN_RING3 */
8731
8732/**
8733 * @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8734 */
8735DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8736{
8737 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8738}
8739
8740/**
8741 * @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8742 */
8743DECLINLINE(DECL_CHECK_RETURN(int))
8744PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8745{
8746 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8747}
8748
8749/**
8750 * @sa PDMCritSectRwTryEnterShared
8751 */
8752DECLINLINE(DECL_CHECK_RETURN(int))
8753PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8754{
8755 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8756}
8757
8758/**
8759 * @sa PDMCritSectRwTryEnterSharedDebug
8760 */
8761DECLINLINE(DECL_CHECK_RETURN(int))
8762PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8763{
8764 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8765}
8766
8767/**
8768 * @sa PDMCritSectRwLeaveShared
8769 */
8770DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8771{
8772 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8773}
8774
8775/**
8776 * @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8777 */
8778DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8779{
8780 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8781}
8782
8783/**
8784 * @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8785 */
8786DECLINLINE(DECL_CHECK_RETURN(int))
8787PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8788{
8789 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8790}
8791
8792/**
8793 * @sa PDMCritSectRwTryEnterExcl
8794 */
8795DECLINLINE(DECL_CHECK_RETURN(int))
8796PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8797{
8798 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8799}
8800
8801/**
8802 * @sa PDMCritSectRwTryEnterExclDebug
8803 */
8804DECLINLINE(DECL_CHECK_RETURN(int))
8805PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8806{
8807 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8808}
8809
8810/**
8811 * @sa PDMCritSectRwLeaveExcl
8812 */
8813DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8814{
8815 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8816}
8817
8818/**
8819 * @see PDMCritSectRwIsWriteOwner
8820 */
8821DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8822{
8823 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8824}
8825
8826/**
8827 * @see PDMCritSectRwIsReadOwner
8828 */
8829DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8830{
8831 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8832}
8833
8834/**
8835 * @see PDMCritSectRwGetWriteRecursion
8836 */
8837DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8838{
8839 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8840}
8841
8842/**
8843 * @see PDMCritSectRwGetWriterReadRecursion
8844 */
8845DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8846{
8847 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8848}
8849
8850/**
8851 * @see PDMCritSectRwGetReadCount
8852 */
8853DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8854{
8855 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8856}
8857
8858/**
8859 * @see PDMCritSectRwIsInitialized
8860 */
8861DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8862{
8863 return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8864}
8865
8866/* Strict build: Remap the two enter calls to the debug versions. */
8867#ifdef VBOX_STRICT
8868# ifdef IPRT_INCLUDED_asm_h
8869# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8870# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8871# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8872# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8873# else
8874# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8875# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8876# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8877# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8878# endif
8879#endif
8880
8881#if defined(IN_RING3) || defined(DOXYGEN_RUNNING)
8882
8883/**
8884 * @copydoc PDMDEVHLPR3::pfnThreadCreate
8885 */
8886DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
8887 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
8888{
8889 return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
8890}
8891
8892/**
8893 * @copydoc PDMR3ThreadDestroy
8894 * @param pDevIns The device instance.
8895 */
8896DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
8897{
8898 return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
8899}
8900
8901/**
8902 * @copydoc PDMR3ThreadIAmSuspending
8903 * @param pDevIns The device instance.
8904 */
8905DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8906{
8907 return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
8908}
8909
8910/**
8911 * @copydoc PDMR3ThreadIAmRunning
8912 * @param pDevIns The device instance.
8913 */
8914DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8915{
8916 return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
8917}
8918
8919/**
8920 * @copydoc PDMR3ThreadSleep
8921 * @param pDevIns The device instance.
8922 */
8923DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
8924{
8925 return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
8926}
8927
8928/**
8929 * @copydoc PDMR3ThreadSuspend
8930 * @param pDevIns The device instance.
8931 */
8932DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8933{
8934 return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
8935}
8936
8937/**
8938 * @copydoc PDMR3ThreadResume
8939 * @param pDevIns The device instance.
8940 */
8941DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8942{
8943 return pDevIns->pHlpR3->pfnThreadResume(pThread);
8944}
8945
8946/**
8947 * @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
8948 */
8949DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
8950{
8951 return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
8952}
8953
8954/**
8955 * @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
8956 */
8957DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
8958{
8959 pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
8960}
8961
8962/**
8963 * @copydoc PDMDEVHLPR3::pfnA20Set
8964 */
8965DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
8966{
8967 pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
8968}
8969
8970/**
8971 * @copydoc PDMDEVHLPR3::pfnRTCRegister
8972 */
8973DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
8974{
8975 return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
8976}
8977
8978/**
8979 * @copydoc PDMDEVHLPR3::pfnPCIBusRegister
8980 */
8981DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 *ppPciHlp, uint32_t *piBus)
8982{
8983 return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
8984}
8985
8986/**
8987 * @copydoc PDMDEVHLPR3::pfnIommuRegister
8988 */
8989DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp, uint32_t *pidxIommu)
8990{
8991 return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
8992}
8993
8994/**
8995 * @copydoc PDMDEVHLPR3::pfnPICRegister
8996 */
8997DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8998{
8999 return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
9000}
9001
9002/**
9003 * @copydoc PDMDEVHLPR3::pfnApicRegister
9004 */
9005DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
9006{
9007 return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
9008}
9009
9010/**
9011 * @copydoc PDMDEVHLPR3::pfnIoApicRegister
9012 */
9013DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9014{
9015 return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
9016}
9017
9018/**
9019 * @copydoc PDMDEVHLPR3::pfnHpetRegister
9020 */
9021DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
9022{
9023 return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
9024}
9025
9026/**
9027 * @copydoc PDMDEVHLPR3::pfnPciRawRegister
9028 */
9029DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
9030{
9031 return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
9032}
9033
9034/**
9035 * @copydoc PDMDEVHLPR3::pfnDMACRegister
9036 */
9037DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
9038{
9039 return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
9040}
9041
9042/**
9043 * @copydoc PDMDEVHLPR3::pfnDMARegister
9044 */
9045DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
9046{
9047 return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
9048}
9049
9050/**
9051 * @copydoc PDMDEVHLPR3::pfnDMAReadMemory
9052 */
9053DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)
9054{
9055 return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
9056}
9057
9058/**
9059 * @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
9060 */
9061DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)
9062{
9063 return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
9064}
9065
9066/**
9067 * @copydoc PDMDEVHLPR3::pfnDMASetDREQ
9068 */
9069DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
9070{
9071 return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
9072}
9073
9074/**
9075 * @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
9076 */
9077DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
9078{
9079 return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
9080}
9081
9082/**
9083 * @copydoc PDMDEVHLPR3::pfnDMASchedule
9084 */
9085DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
9086{
9087 pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
9088}
9089
9090/**
9091 * @copydoc PDMDEVHLPR3::pfnCMOSWrite
9092 */
9093DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
9094{
9095 return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
9096}
9097
9098/**
9099 * @copydoc PDMDEVHLPR3::pfnCMOSRead
9100 */
9101DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
9102{
9103 return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
9104}
9105
9106/**
9107 * @copydoc PDMDEVHLPR3::pfnCallR0
9108 */
9109DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
9110{
9111 return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
9112}
9113
9114/**
9115 * @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
9116 */
9117DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
9118{
9119 return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
9120}
9121
9122/**
9123 * @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
9124 */
9125DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
9126{
9127 return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
9128}
9129
9130/**
9131 * @copydoc PDMDEVHLPR3::pfnGetUVM
9132 */
9133DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
9134{
9135 return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
9136}
9137
9138#endif /* IN_RING3 || DOXYGEN_RUNNING */
9139
9140#if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
9141
9142/**
9143 * @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
9144 */
9145DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
9146{
9147 return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
9148}
9149
9150/**
9151 * @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
9152 */
9153DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
9154{
9155 return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
9156}
9157
9158/**
9159 * @copydoc PDMDEVHLPR0::pfnPICSetUpContext
9160 */
9161DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9162{
9163 return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
9164}
9165
9166/**
9167 * @copydoc PDMDEVHLPR0::pfnApicSetUpContext
9168 */
9169DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
9170{
9171 return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
9172}
9173
9174/**
9175 * @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
9176 */
9177DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9178{
9179 return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
9180}
9181
9182/**
9183 * @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
9184 */
9185DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
9186{
9187 return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
9188}
9189
9190#endif /* !IN_RING3 || DOXYGEN_RUNNING */
9191
9192/**
9193 * @copydoc PDMDEVHLPR3::pfnGetVM
9194 */
9195DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
9196{
9197 return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
9198}
9199
9200/**
9201 * @copydoc PDMDEVHLPR3::pfnGetVMCPU
9202 */
9203DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
9204{
9205 return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
9206}
9207
9208/**
9209 * @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
9210 */
9211DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
9212{
9213 return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
9214}
9215
9216/**
9217 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
9218 */
9219DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
9220{
9221 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
9222}
9223
9224/**
9225 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9226 */
9227DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
9228{
9229 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
9230}
9231
9232/**
9233 * @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9234 */
9235DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
9236{
9237 return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
9238}
9239
9240#ifdef IN_RING3
9241/**
9242 * @copydoc PDMDEVHLPR3::pfnTMCpuTicksPerSecond
9243 */
9244DECLINLINE(uint64_t) PDMDevHlpTMCpuTicksPerSecond(PPDMDEVINS pDevIns)
9245{
9246 return pDevIns->CTX_SUFF(pHlp)->pfnTMCpuTicksPerSecond(pDevIns);
9247}
9248
9249/**
9250 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
9251 */
9252DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
9253{
9254 return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
9255}
9256
9257/**
9258 * @copydoc PDMDEVHLPR3::pfnFirmwareRegister
9259 */
9260DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
9261{
9262 return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
9263}
9264
9265/**
9266 * @copydoc PDMDEVHLPR3::pfnVMReset
9267 */
9268DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
9269{
9270 return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
9271}
9272
9273/**
9274 * @copydoc PDMDEVHLPR3::pfnVMSuspend
9275 */
9276DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
9277{
9278 return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
9279}
9280
9281/**
9282 * @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
9283 */
9284DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
9285{
9286 return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
9287}
9288
9289/**
9290 * @copydoc PDMDEVHLPR3::pfnVMPowerOff
9291 */
9292DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
9293{
9294 return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
9295}
9296
9297#endif /* IN_RING3 */
9298
9299/**
9300 * @copydoc PDMDEVHLPR3::pfnA20IsEnabled
9301 */
9302DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
9303{
9304 return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
9305}
9306
9307#ifdef IN_RING3
9308
9309/**
9310 * @copydoc PDMDEVHLPR3::pfnGetCpuId
9311 */
9312DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
9313{
9314 pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
9315}
9316
9317/**
9318 * @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
9319 */
9320DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
9321{
9322 return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
9323}
9324
9325/**
9326 * @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
9327 */
9328DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
9329{
9330 return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
9331}
9332
9333/**
9334 * @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
9335 */
9336DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9337 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
9338 const char *pszHandlerR0, const char *pszPfHandlerR0,
9339 const char *pszHandlerRC, const char *pszPfHandlerRC,
9340 const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
9341{
9342 return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
9343 pszHandlerR0, pszPfHandlerR0,
9344 pszHandlerRC, pszPfHandlerRC,
9345 pszDesc, phType);
9346}
9347
9348/**
9349 * @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9350 */
9351DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9352 PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
9353 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc)
9354{
9355 return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType,
9356 pvUserR3, pvUserR0, pvUserRC, pszDesc);
9357}
9358
9359/**
9360 * @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9361 */
9362DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9363{
9364 return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9365}
9366#endif
9367
9368/**
9369 * @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9370 */
9371DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9372{
9373 return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9374}
9375
9376#ifdef IN_RING3
9377/**
9378 * @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9379 */
9380DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9381{
9382 return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9383}
9384
9385/**
9386 * @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9387 */
9388DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9389{
9390 return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9391}
9392
9393/**
9394 * @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9395 */
9396DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9397{
9398 return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9399}
9400
9401/**
9402 * @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9403 */
9404DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char *pszModuleName, char *pszVersion,
9405 RTGCPTR GCBaseAddr, uint32_t cbModule,
9406 uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9407{
9408 return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9409 GCBaseAddr, cbModule, cRegions, paRegions);
9410}
9411
9412/**
9413 * @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9414 */
9415DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char *pszModuleName, char *pszVersion,
9416 RTGCPTR GCBaseAddr, uint32_t cbModule)
9417{
9418 return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9419}
9420
9421/**
9422 * @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9423 */
9424DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9425 uint64_t *pfPageFlags)
9426{
9427 return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9428}
9429
9430/**
9431 * @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9432 */
9433DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9434{
9435 return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9436}
9437
9438/**
9439 * @copydoc PDMDEVHLPR3::pfnQueryLun
9440 */
9441DECLINLINE(int) PDMDevHlpQueryLun(PPDMDEVINS pDevIns, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMIBASE *ppBase)
9442{
9443 return pDevIns->pHlpR3->pfnQueryLun(pDevIns, pszDevice, iInstance, iLun, ppBase);
9444}
9445
9446/**
9447 * @copydoc PDMDEVHLPR3::pfnGIMDeviceRegister
9448 */
9449DECLINLINE(void) PDMDevHlpGIMDeviceRegister(PPDMDEVINS pDevIns, PGIMDEBUG pDbg)
9450{
9451 pDevIns->pHlpR3->pfnGIMDeviceRegister(pDevIns, pDbg);
9452}
9453
9454/**
9455 * @copydoc PDMDEVHLPR3::pfnGIMGetDebugSetup
9456 */
9457DECLINLINE(int) PDMDevHlpGIMGetDebugSetup(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup)
9458{
9459 return pDevIns->pHlpR3->pfnGIMGetDebugSetup(pDevIns, pDbgSetup);
9460}
9461#endif
9462
9463/**
9464 * @copydoc PDMDEVHLPR3::pfnGIMGetMmio2Regions
9465 */
9466DECLINLINE(PGIMMMIO2REGION) PDMDevHlpGIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
9467{
9468 return pDevIns->CTX_SUFF(pHlp)->pfnGIMGetMmio2Regions(pDevIns, pcRegions);
9469}
9470
9471#ifdef IN_RING3
9472/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9473# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9474 do { \
9475 uint32_t u32GetEnumTmp = 0; \
9476 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9477 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9478 (a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9479 AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9480 } while (0)
9481
9482/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9483# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9484 do { \
9485 uint8_t bGetEnumTmp = 0; \
9486 int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9487 AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9488 (a_enmDst) = (a_EnumType)bGetEnumTmp; \
9489 } while (0)
9490
9491#endif /* IN_RING3 */
9492
9493/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9494typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9495
9496/**
9497 * Callbacks for VBoxDeviceRegister().
9498 */
9499typedef struct PDMDEVREGCB
9500{
9501 /** Interface version.
9502 * This is set to PDM_DEVREG_CB_VERSION. */
9503 uint32_t u32Version;
9504
9505 /**
9506 * Registers a device with the current VM instance.
9507 *
9508 * @returns VBox status code.
9509 * @param pCallbacks Pointer to the callback table.
9510 * @param pReg Pointer to the device registration record.
9511 * This data must be permanent and readonly.
9512 */
9513 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9514} PDMDEVREGCB;
9515
9516/** Current version of the PDMDEVREGCB structure. */
9517#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9518
9519
9520/**
9521 * The VBoxDevicesRegister callback function.
9522 *
9523 * PDM will invoke this function after loading a device module and letting
9524 * the module decide which devices to register and how to handle conflicts.
9525 *
9526 * @returns VBox status code.
9527 * @param pCallbacks Pointer to the callback table.
9528 * @param u32Version VBox version number.
9529 */
9530typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9531
9532/** @} */
9533
9534RT_C_DECLS_END
9535
9536#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */
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