pdmdev.h@ 91014

最後變更在這個檔案從91014是 91000,由 vboxsync 提交於 4 年前
VMM,PDM,PGM: Restrict the VMSetError and VMSetRuntimeError APIs to ring-3, these never worked properly in ring-0 or raw-mode. A PAEmode runtime error was the only place any of these were used, but given that the VMSetRuntimeError codepath starts with an assertion, it can't have been used/tested. The PAEmode runtime error shouldn't necessarily be triggered by PGM anyway, but IEM. Removed VMMCALLRING3_VM_SET_ERROR and VMMCALLRING3_VM_SET_RUNTIME_ERROR. [doxygen fix] bugref:10093
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Id Revision`
檔案大小: 366.8 KB

行
1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.alldomusa.eu.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmcritsectrw.h>
34	#include <VBox/vmm/pdmqueue.h>
35	#include <VBox/vmm/pdmtask.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmthread.h>
38	#endif
39	#include <VBox/vmm/pdmifs.h>
40	#include <VBox/vmm/pdmins.h>
41	#include <VBox/vmm/pdmcommon.h>
42	#include <VBox/vmm/pdmpcidev.h>
43	#include <VBox/vmm/iom.h>
44	#include <VBox/vmm/tm.h>
45	#include <VBox/vmm/ssm.h>
46	#include <VBox/vmm/cfgm.h>
47	#include <VBox/vmm/cpum.h>
48	#include <VBox/vmm/dbgf.h>
49	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
50	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
51	#include <VBox/msi.h>
52	#include <iprt/stdarg.h>
53	#include <iprt/list.h>
54
55
56	RT_C_DECLS_BEGIN
57
58	/** @defgroup grp_pdm_device The PDM Devices API
59	* @ingroup grp_pdm
60	* @{
61	*/
62
63	/**
64	* Construct a device instance for a VM.
65	*
66	* @returns VBox status.
67	* @param pDevIns The device instance data. If the registration structure
68	* is needed, it can be accessed thru pDevIns->pReg.
69	* @param iInstance Instance number. Use this to figure out which registers
70	* and such to use. The instance number is also found in
71	* pDevIns->iInstance, but since it's likely to be
72	* frequently used PDM passes it as parameter.
73	* @param pCfg Configuration node handle for the driver. This is
74	* expected to be in high demand in the constructor and is
75	* therefore passed as an argument. When using it at other
76	* times, it can be found in pDevIns->pCfg.
77	*/
78	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
79	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
80	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
81
82	/**
83	* Destruct a device instance.
84	*
85	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
86	* resources can be freed correctly.
87	*
88	* @returns VBox status.
89	* @param pDevIns The device instance data.
90	*
91	* @remarks The device critical section is not entered. The routine may delete
92	* the critical section, so the caller cannot exit it.
93	*/
94	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
95	/** Pointer to a FNPDMDEVDESTRUCT() function. */
96	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
97
98	/**
99	* Device relocation callback.
100	*
101	* This is called when the instance data has been relocated in raw-mode context
102	* (RC). It is also called when the RC hypervisor selects changes. The device
103	* must fixup all necessary pointers and re-query all interfaces to other RC
104	* devices and drivers.
105	*
106	* Before the RC code is executed the first time, this function will be called
107	* with a 0 delta so RC pointer calculations can be one in one place.
108	*
109	* @param pDevIns Pointer to the device instance.
110	* @param offDelta The relocation delta relative to the old location.
111	*
112	* @remarks A relocation CANNOT fail.
113	*
114	* @remarks The device critical section is not entered. The relocations should
115	* not normally require any locking.
116	*/
117	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
118	/** Pointer to a FNPDMDEVRELOCATE() function. */
119	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
120
121	/**
122	* Power On notification.
123	*
124	* @returns VBox status.
125	* @param pDevIns The device instance data.
126	*
127	* @remarks Caller enters the device critical section.
128	*/
129	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
130	/** Pointer to a FNPDMDEVPOWERON() function. */
131	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
132
133	/**
134	* Reset notification.
135	*
136	* @returns VBox status.
137	* @param pDevIns The device instance data.
138	*
139	* @remarks Caller enters the device critical section.
140	*/
141	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
142	/** Pointer to a FNPDMDEVRESET() function. */
143	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
144
145	/**
146	* Soft reset notification.
147	*
148	* This is mainly for emulating the 286 style protected mode exits, in which
149	* most devices should remain in their current state.
150	*
151	* @returns VBox status.
152	* @param pDevIns The device instance data.
153	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
154	*
155	* @remarks Caller enters the device critical section.
156	*/
157	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
158	/** Pointer to a FNPDMDEVSOFTRESET() function. */
159	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
160
161	/** @name PDMVMRESET_F_XXX - VM reset flags.
162	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
163	* reset via PDMDevHlpVMReset.
164	* @{ */
165	/** Unknown reason. */
166	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
167	/** GIM triggered reset. */
168	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
169	/** The last source always causing hard resets. */
170	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
171	/** ACPI triggered reset. */
172	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
173	/** PS/2 system port A (92h) reset. */
174	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
175	/** Keyboard reset. */
176	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
177	/** Tripple fault. */
178	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
179	/** Reset source mask. */
180	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
181	/** @} */
182
183	/**
184	* Suspend notification.
185	*
186	* @returns VBox status.
187	* @param pDevIns The device instance data.
188	* @thread EMT(0)
189	*
190	* @remarks Caller enters the device critical section.
191	*/
192	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
193	/** Pointer to a FNPDMDEVSUSPEND() function. */
194	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
195
196	/**
197	* Resume notification.
198	*
199	* @returns VBox status.
200	* @param pDevIns The device instance data.
201	*
202	* @remarks Caller enters the device critical section.
203	*/
204	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
205	/** Pointer to a FNPDMDEVRESUME() function. */
206	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
207
208	/**
209	* Power Off notification.
210	*
211	* This is always called when VMR3PowerOff is called.
212	* There will be no callback when hot plugging devices.
213	*
214	* @param pDevIns The device instance data.
215	* @thread EMT(0)
216	*
217	* @remarks Caller enters the device critical section.
218	*/
219	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
220	/** Pointer to a FNPDMDEVPOWEROFF() function. */
221	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
222
223	/**
224	* Attach command.
225	*
226	* This is called to let the device attach to a driver for a specified LUN
227	* at runtime. This is not called during VM construction, the device
228	* constructor has to attach to all the available drivers.
229	*
230	* This is like plugging in the keyboard or mouse after turning on the PC.
231	*
232	* @returns VBox status code.
233	* @param pDevIns The device instance.
234	* @param iLUN The logical unit which is being attached.
235	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
236	*
237	* @remarks Caller enters the device critical section.
238	*/
239	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
240	/** Pointer to a FNPDMDEVATTACH() function. */
241	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
242
243	/**
244	* Detach notification.
245	*
246	* This is called when a driver is detaching itself from a LUN of the device.
247	* The device should adjust its state to reflect this.
248	*
249	* This is like unplugging the network cable to use it for the laptop or
250	* something while the PC is still running.
251	*
252	* @param pDevIns The device instance.
253	* @param iLUN The logical unit which is being detached.
254	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
255	*
256	* @remarks Caller enters the device critical section.
257	*/
258	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
259	/** Pointer to a FNPDMDEVDETACH() function. */
260	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
261
262	/**
263	* Query the base interface of a logical unit.
264	*
265	* @returns VBOX status code.
266	* @param pDevIns The device instance.
267	* @param iLUN The logicial unit to query.
268	* @param ppBase Where to store the pointer to the base interface of the LUN.
269	*
270	* @remarks The device critical section is not entered.
271	*/
272	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
273	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
274	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
275
276	/**
277	* Init complete notification (after ring-0 & RC init since 5.1).
278	*
279	* This can be done to do communication with other devices and other
280	* initialization which requires everything to be in place.
281	*
282	* @returns VBOX status code.
283	* @param pDevIns The device instance.
284	*
285	* @remarks Caller enters the device critical section.
286	*/
287	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
288	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
289	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
290
291
292	/**
293	* The context of a pfnMemSetup call.
294	*/
295	typedef enum PDMDEVMEMSETUPCTX
296	{
297	/** Invalid zero value. */
298	PDMDEVMEMSETUPCTX_INVALID = 0,
299	/** After construction. */
300	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
301	/** After reset. */
302	PDMDEVMEMSETUPCTX_AFTER_RESET,
303	/** Type size hack. */
304	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
305	} PDMDEVMEMSETUPCTX;
306
307
308	/**
309	* PDM Device Registration Structure.
310	*
311	* This structure is used when registering a device from VBoxInitDevices() in HC
312	* Ring-3. PDM will continue use till the VM is terminated.
313	*
314	* @note The first part is the same in every context.
315	*/
316	typedef struct PDMDEVREGR3
317	{
318	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
319	uint32_t u32Version;
320	/** Reserved, must be zero. */
321	uint32_t uReserved0;
322	/** Device name, must match the ring-3 one. */
323	char szName[32];
324	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
325	uint32_t fFlags;
326	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
327	uint32_t fClass;
328	/** Maximum number of instances (per VM). */
329	uint32_t cMaxInstances;
330	/** The shared data structure version number. */
331	uint32_t uSharedVersion;
332	/** Size of the instance data. */
333	uint32_t cbInstanceShared;
334	/** Size of the ring-0 instance data. */
335	uint32_t cbInstanceCC;
336	/** Size of the raw-mode instance data. */
337	uint32_t cbInstanceRC;
338	/** Max number of PCI devices. */
339	uint16_t cMaxPciDevices;
340	/** Max number of MSI-X vectors in any of the PCI devices. */
341	uint16_t cMaxMsixVectors;
342	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
343	* remain unchanged from registration till VM destruction. */
344	const char *pszDescription;
345
346	/** Name of the raw-mode context module (no path).
347	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
348	const char *pszRCMod;
349	/** Name of the ring-0 module (no path).
350	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
351	const char *pszR0Mod;
352
353	/** Construct instance - required. */
354	PFNPDMDEVCONSTRUCT pfnConstruct;
355	/** Destruct instance - optional.
356	* Critical section NOT entered (will be destroyed). */
357	PFNPDMDEVDESTRUCT pfnDestruct;
358	/** Relocation command - optional.
359	* Critical section NOT entered. */
360	PFNPDMDEVRELOCATE pfnRelocate;
361	/**
362	* Memory setup callback.
363	*
364	* @param pDevIns The device instance data.
365	* @param enmCtx Indicates the context of the call.
366	* @remarks The critical section is entered prior to calling this method.
367	*/
368	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
369	/** Power on notification - optional.
370	* Critical section is entered. */
371	PFNPDMDEVPOWERON pfnPowerOn;
372	/** Reset notification - optional.
373	* Critical section is entered. */
374	PFNPDMDEVRESET pfnReset;
375	/** Suspend notification - optional.
376	* Critical section is entered. */
377	PFNPDMDEVSUSPEND pfnSuspend;
378	/** Resume notification - optional.
379	* Critical section is entered. */
380	PFNPDMDEVRESUME pfnResume;
381	/** Attach command - optional.
382	* Critical section is entered. */
383	PFNPDMDEVATTACH pfnAttach;
384	/** Detach notification - optional.
385	* Critical section is entered. */
386	PFNPDMDEVDETACH pfnDetach;
387	/** Query a LUN base interface - optional.
388	* Critical section is NOT entered. */
389	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
390	/** Init complete notification - optional.
391	* Critical section is entered. */
392	PFNPDMDEVINITCOMPLETE pfnInitComplete;
393	/** Power off notification - optional.
394	* Critical section is entered. */
395	PFNPDMDEVPOWEROFF pfnPowerOff;
396	/** Software system reset notification - optional.
397	* Critical section is entered. */
398	PFNPDMDEVSOFTRESET pfnSoftReset;
399
400	/** @name Reserved for future extensions, must be zero.
401	* @{ */
402	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
403	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
409	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
410	/** @} */
411
412	/** Initialization safty marker. */
413	uint32_t u32VersionEnd;
414	} PDMDEVREGR3;
415	/** Pointer to a PDM Device Structure. */
416	typedef PDMDEVREGR3 *PPDMDEVREGR3;
417	/** Const pointer to a PDM Device Structure. */
418	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
419	/** Current DEVREGR3 version number. */
420	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
421
422
423	/** PDM Device Flags.
424	* @{ */
425	/** This flag is used to indicate that the device has a R0 component. */
426	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
427	/** Requires the ring-0 component, ignore configuration values. */
428	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
429	/** Requires the ring-0 component, ignore configuration values. */
430	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
431
432	/** This flag is used to indicate that the device has a RC component. */
433	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
434	/** Requires the raw-mode component, ignore configuration values. */
435	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
436	/** Requires the raw-mode component, ignore configuration values. */
437	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
438
439	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
440	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
441
442	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
443	* The bit count for the current host.
444	* @note Superfluous, but still around for hysterical raisins. */
445	#if HC_ARCH_BITS == 32
446	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
447	#elif HC_ARCH_BITS == 64
448	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
449	#else
450	# error Unsupported HC_ARCH_BITS value.
451	#endif
452	/** The host bit count mask. */
453	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
454
455	/** The device support only 32-bit guests. */
456	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
457	/** The device support only 64-bit guests. */
458	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
459	/** The device support both 32-bit & 64-bit guests. */
460	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
461	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
462	* The guest bit count for the current compilation. */
463	#if GC_ARCH_BITS == 32
464	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
465	#elif GC_ARCH_BITS == 64
466	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
467	#else
468	# error Unsupported GC_ARCH_BITS value.
469	#endif
470	/** The guest bit count mask. */
471	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
472
473	/** A convenience. */
474	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
475
476	/** Indicates that the device needs to be notified before the drivers when suspending. */
477	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
478	/** Indicates that the device needs to be notified before the drivers when powering off. */
479	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
480	/** Indicates that the device needs to be notified before the drivers when resetting. */
481	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
482
483	/** This flag is used to indicate that the device has been converted to the
484	* new device style. */
485	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
486
487	/** @} */
488
489
490	/** PDM Device Classes.
491	* The order is important, lower bit earlier instantiation.
492	* @{ */
493	/** Architecture device. */
494	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
495	/** Architecture BIOS device. */
496	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
497	/** PCI bus brigde. */
498	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
499	/** PCI built-in device (e.g. PCI root complex devices). */
500	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
501	/** Input device (mouse, keyboard, joystick, HID, ...). */
502	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
503	/** Interrupt controller (PIC). */
504	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
505	/** Interval controoler (PIT). */
506	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
507	/** RTC/CMOS. */
508	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
509	/** DMA controller. */
510	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
511	/** VMM Device. */
512	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
513	/** Graphics device, like VGA. */
514	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
515	/** Storage controller device. */
516	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
517	/** Network interface controller. */
518	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
519	/** Audio. */
520	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
521	/** USB HIC. */
522	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
523	/** ACPI. */
524	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
525	/** Serial controller device. */
526	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
527	/** Parallel controller device */
528	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
529	/** Host PCI pass-through device */
530	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
531	/** Misc devices (always last). */
532	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
533	/** @} */
534
535
536	/**
537	* PDM Device Registration Structure, ring-0.
538	*
539	* This structure is used when registering a device from VBoxInitDevices() in HC
540	* Ring-0. PDM will continue use till the VM is terminated.
541	*/
542	typedef struct PDMDEVREGR0
543	{
544	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
545	uint32_t u32Version;
546	/** Reserved, must be zero. */
547	uint32_t uReserved0;
548	/** Device name, must match the ring-3 one. */
549	char szName[32];
550	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
551	uint32_t fFlags;
552	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
553	uint32_t fClass;
554	/** Maximum number of instances (per VM). */
555	uint32_t cMaxInstances;
556	/** The shared data structure version number. */
557	uint32_t uSharedVersion;
558	/** Size of the instance data. */
559	uint32_t cbInstanceShared;
560	/** Size of the ring-0 instance data. */
561	uint32_t cbInstanceCC;
562	/** Size of the raw-mode instance data. */
563	uint32_t cbInstanceRC;
564	/** Max number of PCI devices. */
565	uint16_t cMaxPciDevices;
566	/** Max number of MSI-X vectors in any of the PCI devices. */
567	uint16_t cMaxMsixVectors;
568	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
569	* remain unchanged from registration till VM destruction. */
570	const char *pszDescription;
571
572	/**
573	* Early construction callback (optional).
574	*
575	* This is called right after the device instance structure has been allocated
576	* and before the ring-3 constructor gets called.
577	*
578	* @returns VBox status code.
579	* @param pDevIns The device instance data.
580	* @note The destructure is always called, regardless of the return status.
581	*/
582	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
583
584	/**
585	* Regular construction callback (optional).
586	*
587	* This is called after (or during) the ring-3 constructor.
588	*
589	* @returns VBox status code.
590	* @param pDevIns The device instance data.
591	* @note The destructure is always called, regardless of the return status.
592	*/
593	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
594
595	/**
596	* Destructor (optional).
597	*
598	* This is called after the ring-3 destruction. This is not called if ring-3
599	* fails to trigger it (e.g. process is killed or crashes).
600	*
601	* @param pDevIns The device instance data.
602	*/
603	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
604
605	/**
606	* Final destructor (optional).
607	*
608	* This is called right before the memory is freed, which happens when the
609	* VM/GVM object is destroyed. This is always called.
610	*
611	* @param pDevIns The device instance data.
612	*/
613	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
614
615	/**
616	* Generic request handler (optional).
617	*
618	* @param pDevIns The device instance data.
619	* @param uReq Device specific request.
620	* @param uArg Request argument.
621	*/
622	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
623
624	/** @name Reserved for future extensions, must be zero.
625	* @{ */
626	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
627	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
633	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
634	/** @} */
635
636	/** Initialization safty marker. */
637	uint32_t u32VersionEnd;
638	} PDMDEVREGR0;
639	/** Pointer to a ring-0 PDM device registration structure. */
640	typedef PDMDEVREGR0 *PPDMDEVREGR0;
641	/** Pointer to a const ring-0 PDM device registration structure. */
642	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
643	/** Current DEVREGR0 version number. */
644	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
645
646
647	/**
648	* PDM Device Registration Structure, raw-mode
649	*
650	* At the moment, this structure is mostly here to match the other two contexts.
651	*/
652	typedef struct PDMDEVREGRC
653	{
654	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
655	uint32_t u32Version;
656	/** Reserved, must be zero. */
657	uint32_t uReserved0;
658	/** Device name, must match the ring-3 one. */
659	char szName[32];
660	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
661	uint32_t fFlags;
662	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
663	uint32_t fClass;
664	/** Maximum number of instances (per VM). */
665	uint32_t cMaxInstances;
666	/** The shared data structure version number. */
667	uint32_t uSharedVersion;
668	/** Size of the instance data. */
669	uint32_t cbInstanceShared;
670	/** Size of the ring-0 instance data. */
671	uint32_t cbInstanceCC;
672	/** Size of the raw-mode instance data. */
673	uint32_t cbInstanceRC;
674	/** Max number of PCI devices. */
675	uint16_t cMaxPciDevices;
676	/** Max number of MSI-X vectors in any of the PCI devices. */
677	uint16_t cMaxMsixVectors;
678	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
679	* remain unchanged from registration till VM destruction. */
680	const char *pszDescription;
681
682	/**
683	* Constructor callback.
684	*
685	* This is called much later than both the ring-0 and ring-3 constructors, since
686	* raw-mode v2 require a working VMM to run actual code.
687	*
688	* @returns VBox status code.
689	* @param pDevIns The device instance data.
690	* @note The destructure is always called, regardless of the return status.
691	*/
692	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
693
694	/** @name Reserved for future extensions, must be zero.
695	* @{ */
696	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
697	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
703	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
704	/** @} */
705
706	/** Initialization safty marker. */
707	uint32_t u32VersionEnd;
708	} PDMDEVREGRC;
709	/** Pointer to a raw-mode PDM device registration structure. */
710	typedef PDMDEVREGRC *PPDMDEVREGRC;
711	/** Pointer to a const raw-mode PDM device registration structure. */
712	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
713	/** Current DEVREGRC version number. */
714	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
715
716
717
718	/** @def PDM_DEVREG_VERSION
719	* Current DEVREG version number. */
720	/** @typedef PDMDEVREGR3
721	* A current context PDM device registration structure. */
722	/** @typedef PPDMDEVREGR3
723	* Pointer to a current context PDM device registration structure. */
724	/** @typedef PCPDMDEVREGR3
725	* Pointer to a const current context PDM device registration structure. */
726	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
727	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
728	typedef PDMDEVREGR3 PDMDEVREG;
729	typedef PPDMDEVREGR3 PPDMDEVREG;
730	typedef PCPDMDEVREGR3 PCPDMDEVREG;
731	#elif defined(IN_RING0)
732	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
733	typedef PDMDEVREGR0 PDMDEVREG;
734	typedef PPDMDEVREGR0 PPDMDEVREG;
735	typedef PCPDMDEVREGR0 PCPDMDEVREG;
736	#elif defined(IN_RC)
737	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
738	typedef PDMDEVREGRC PDMDEVREG;
739	typedef PPDMDEVREGRC PPDMDEVREG;
740	typedef PCPDMDEVREGRC PCPDMDEVREG;
741	#else
742	# error "Not IN_RING3, IN_RING0 or IN_RC"
743	#endif
744
745
746	/**
747	* Device registrations for ring-0 modules.
748	*
749	* This structure is used directly and must therefore reside in persistent
750	* memory (i.e. the data section).
751	*/
752	typedef struct PDMDEVMODREGR0
753	{
754	/** The structure version (PDM_DEVMODREGR0_VERSION). */
755	uint32_t u32Version;
756	/** Number of devices in the array papDevRegs points to. */
757	uint32_t cDevRegs;
758	/** Pointer to device registration structures. */
759	PCPDMDEVREGR0 *papDevRegs;
760	/** The ring-0 module handle - PDM internal, fingers off. */
761	void *hMod;
762	/** List entry - PDM internal, fingers off. */
763	RTLISTNODE ListEntry;
764	} PDMDEVMODREGR0;
765	/** Pointer to device registriations for a ring-0 module. */
766	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
767	/** Current PDMDEVMODREGR0 version number. */
768	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
769
770
771	/** @name IRQ Level for use with the *SetIrq APIs.
772	* @{
773	*/
774	/** Assert the IRQ (can assume value 1). */
775	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
776	/** Deassert the IRQ (can assume value 0). */
777	#define PDM_IRQ_LEVEL_LOW 0
778	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
779	* automatically deasserts it after delivery to the APIC (IOAPIC).
780	* @note Only suitable for edge trigger interrupts. */
781	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
782	/** @} */
783
784	/**
785	* Registration record for MSI/MSI-X emulation.
786	*/
787	typedef struct PDMMSIREG
788	{
789	/** Number of MSI interrupt vectors, 0 if MSI not supported */
790	uint16_t cMsiVectors;
791	/** Offset of MSI capability */
792	uint8_t iMsiCapOffset;
793	/** Offset of next capability to MSI */
794	uint8_t iMsiNextOffset;
795	/** If we support 64-bit MSI addressing */
796	bool fMsi64bit;
797	/** If we do not support per-vector masking */
798	bool fMsiNoMasking;
799
800	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
801	uint16_t cMsixVectors;
802	/** Offset of MSI-X capability */
803	uint8_t iMsixCapOffset;
804	/** Offset of next capability to MSI-X */
805	uint8_t iMsixNextOffset;
806	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
807	uint8_t iMsixBar;
808	} PDMMSIREG;
809	typedef PDMMSIREG *PPDMMSIREG;
810
811	/**
812	* PCI Bus registration structure.
813	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
814	*/
815	typedef struct PDMPCIBUSREGR3
816	{
817	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
818	uint32_t u32Version;
819
820	/**
821	* Registers the device with the default PCI bus.
822	*
823	* @returns VBox status code.
824	* @param pDevIns Device instance of the PCI Bus.
825	* @param pPciDev The PCI device structure.
826	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
827	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
828	* device number (0-31).
829	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
830	* function number (0-7).
831	* @param pszName Device name (static but not unique).
832	*
833	* @remarks Caller enters the PDM critical section.
834	*/
835	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
836	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
837
838	/**
839	* Initialize MSI or MSI-X emulation support in a PCI device.
840	*
841	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
842	* vast majority of device emulation it covers everything necessary. It's
843	* fully automatic, taking care of all BAR and config space requirements,
844	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
845	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
846	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
847	*
848	* A device not using this can still offer MSI/MSI-X. In this case it's
849	* completely up to the device (in the MSI-X case) to create/register the
850	* necessary MMIO BAR, handle all config space/BAR updating and take care
851	* of delivering the interrupts appropriately.
852	*
853	* @returns VBox status code.
854	* @param pDevIns Device instance of the PCI Bus.
855	* @param pPciDev The PCI device structure.
856	* @param pMsiReg MSI emulation registration structure
857	* @remarks Caller enters the PDM critical section.
858	*/
859	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
860
861	/**
862	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
863	*
864	* @returns VBox status code.
865	* @param pDevIns Device instance of the PCI Bus.
866	* @param pPciDev The PCI device structure.
867	* @param iRegion The region number.
868	* @param cbRegion Size of the region.
869	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
870	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
871	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
872	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
873	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
874	* @a fFlags, UINT64_MAX if no handle is passed
875	* (old style).
876	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
877	* is given.
878	* @remarks Caller enters the PDM critical section.
879	*/
880	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
881	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
882	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
883
884	/**
885	* Register PCI configuration space read/write intercept callbacks.
886	*
887	* @param pDevIns Device instance of the PCI Bus.
888	* @param pPciDev The PCI device structure.
889	* @param pfnRead Pointer to the user defined PCI config read function.
890	* @param pfnWrite Pointer to the user defined PCI config write function.
891	* to call default PCI config write function. Can be NULL.
892	* @remarks Caller enters the PDM critical section.
893	* @thread EMT
894	*/
895	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
896	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
897
898	/**
899	* Perform a PCI configuration space write, bypassing interception.
900	*
901	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
902	*
903	* @returns Strict VBox status code (mainly DBGFSTOP).
904	* @param pDevIns Device instance of the PCI Bus.
905	* @param pPciDev The PCI device which config space is being read.
906	* @param uAddress The config space address.
907	* @param cb The size of the read: 1, 2 or 4 bytes.
908	* @param u32Value The value to write.
909	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
910	* that the (root) bus will have done that already.
911	*/
912	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
913	uint32_t uAddress, unsigned cb, uint32_t u32Value));
914
915	/**
916	* Perform a PCI configuration space read, bypassing interception.
917	*
918	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
919	*
920	* @returns Strict VBox status code (mainly DBGFSTOP).
921	* @param pDevIns Device instance of the PCI Bus.
922	* @param pPciDev The PCI device which config space is being read.
923	* @param uAddress The config space address.
924	* @param cb The size of the read: 1, 2 or 4 bytes.
925	* @param pu32Value Where to return the value.
926	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
927	* that the (root) bus will have done that already.
928	*/
929	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
930	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
931
932	/**
933	* Set the IRQ for a PCI device.
934	*
935	* @param pDevIns Device instance of the PCI Bus.
936	* @param pPciDev The PCI device structure.
937	* @param iIrq IRQ number to set.
938	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
939	* @param uTagSrc The IRQ tag and source (for tracing).
940	* @remarks Caller enters the PDM critical section.
941	*/
942	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
943
944	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
945	uint32_t u32EndVersion;
946	} PDMPCIBUSREGR3;
947	/** Pointer to a PCI bus registration structure. */
948	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
949	/** Current PDMPCIBUSREGR3 version number. */
950	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
951
952	/**
953	* PCI Bus registration structure for ring-0.
954	*/
955	typedef struct PDMPCIBUSREGR0
956	{
957	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
958	uint32_t u32Version;
959	/** The PCI bus number (from ring-3 registration). */
960	uint32_t iBus;
961	/**
962	* Set the IRQ for a PCI device.
963	*
964	* @param pDevIns Device instance of the PCI Bus.
965	* @param pPciDev The PCI device structure.
966	* @param iIrq IRQ number to set.
967	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
968	* @param uTagSrc The IRQ tag and source (for tracing).
969	* @remarks Caller enters the PDM critical section.
970	*/
971	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
972	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
973	uint32_t u32EndVersion;
974	} PDMPCIBUSREGR0;
975	/** Pointer to a PCI bus ring-0 registration structure. */
976	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
977	/** Current PDMPCIBUSREGR0 version number. */
978	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
979
980	/**
981	* PCI Bus registration structure for raw-mode.
982	*/
983	typedef struct PDMPCIBUSREGRC
984	{
985	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
986	uint32_t u32Version;
987	/** The PCI bus number (from ring-3 registration). */
988	uint32_t iBus;
989	/**
990	* Set the IRQ for a PCI device.
991	*
992	* @param pDevIns Device instance of the PCI Bus.
993	* @param pPciDev The PCI device structure.
994	* @param iIrq IRQ number to set.
995	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
996	* @param uTagSrc The IRQ tag and source (for tracing).
997	* @remarks Caller enters the PDM critical section.
998	*/
999	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1000	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1001	uint32_t u32EndVersion;
1002	} PDMPCIBUSREGRC;
1003	/** Pointer to a PCI bus raw-mode registration structure. */
1004	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1005	/** Current PDMPCIBUSREGRC version number. */
1006	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1007
1008	/** PCI bus registration structure for the current context. */
1009	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1010	/** Pointer to a PCI bus registration structure for the current context. */
1011	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1012	/** PCI bus registration structure version for the current context. */
1013	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1014
1015
1016	/**
1017	* PCI Bus RC helpers.
1018	*/
1019	typedef struct PDMPCIHLPRC
1020	{
1021	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1022	uint32_t u32Version;
1023
1024	/**
1025	* Set an ISA IRQ.
1026	*
1027	* @param pDevIns PCI device instance.
1028	* @param iIrq IRQ number to set.
1029	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1030	* @param uTagSrc The IRQ tag and source (for tracing).
1031	* @thread EMT only.
1032	*/
1033	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1034
1035	/**
1036	* Set an I/O-APIC IRQ.
1037	*
1038	* @param pDevIns PCI device instance.
1039	* @param uBusDevFn The bus:device:function of the device initiating the
1040	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1041	* interrupt.
1042	* @param iIrq IRQ number to set.
1043	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1044	* @param uTagSrc The IRQ tag and source (for tracing).
1045	* @thread EMT only.
1046	*/
1047	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1048
1049	/**
1050	* Send an MSI.
1051	*
1052	* @param pDevIns PCI device instance.
1053	* @param uBusDevFn The bus:device:function of the device initiating the
1054	* MSI. Cannot be NIL_PCIBDF.
1055	* @param pMsi The MSI to send.
1056	* @param uTagSrc The IRQ tag and source (for tracing).
1057	* @thread EMT only.
1058	*/
1059	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1060
1061
1062	/**
1063	* Acquires the PDM lock.
1064	*
1065	* @returns VINF_SUCCESS on success.
1066	* @returns rc if we failed to acquire the lock.
1067	* @param pDevIns The PCI device instance.
1068	* @param rc What to return if we fail to acquire the lock.
1069	*
1070	* @sa PDMCritSectEnter
1071	*/
1072	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1073
1074	/**
1075	* Releases the PDM lock.
1076	*
1077	* @param pDevIns The PCI device instance.
1078	*/
1079	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1080
1081	/**
1082	* Gets a bus by it's PDM ordinal (typically the parent bus).
1083	*
1084	* @returns Pointer to the device instance of the bus.
1085	* @param pDevIns The PCI bus device instance.
1086	* @param idxPdmBus The PDM ordinal value of the bus to get.
1087	*/
1088	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1089
1090	/** Just a safety precaution. */
1091	uint32_t u32TheEnd;
1092	} PDMPCIHLPRC;
1093	/** Pointer to PCI helpers. */
1094	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1095	/** Pointer to const PCI helpers. */
1096	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1097
1098	/** Current PDMPCIHLPRC version number. */
1099	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1100
1101
1102	/**
1103	* PCI Bus R0 helpers.
1104	*/
1105	typedef struct PDMPCIHLPR0
1106	{
1107	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1108	uint32_t u32Version;
1109
1110	/**
1111	* Set an ISA IRQ.
1112	*
1113	* @param pDevIns PCI device instance.
1114	* @param iIrq IRQ number to set.
1115	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1116	* @param uTagSrc The IRQ tag and source (for tracing).
1117	* @thread EMT only.
1118	*/
1119	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1120
1121	/**
1122	* Set an I/O-APIC IRQ.
1123	*
1124	* @param pDevIns PCI device instance.
1125	* @param uBusDevFn The bus:device:function of the device initiating the
1126	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1127	* interrupt.
1128	* @param iIrq IRQ number to set.
1129	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1130	* @param uTagSrc The IRQ tag and source (for tracing).
1131	* @thread EMT only.
1132	*/
1133	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1134
1135	/**
1136	* Send an MSI.
1137	*
1138	* @param pDevIns PCI device instance.
1139	* @param uBusDevFn The bus:device:function of the device initiating the
1140	* MSI. Cannot be NIL_PCIBDF.
1141	* @param pMsi The MSI to send.
1142	* @param uTagSrc The IRQ tag and source (for tracing).
1143	* @thread EMT only.
1144	*/
1145	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1146
1147	/**
1148	* Acquires the PDM lock.
1149	*
1150	* @returns VINF_SUCCESS on success.
1151	* @returns rc if we failed to acquire the lock.
1152	* @param pDevIns The PCI device instance.
1153	* @param rc What to return if we fail to acquire the lock.
1154	*
1155	* @sa PDMCritSectEnter
1156	*/
1157	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1158
1159	/**
1160	* Releases the PDM lock.
1161	*
1162	* @param pDevIns The PCI device instance.
1163	*/
1164	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1165
1166	/**
1167	* Gets a bus by it's PDM ordinal (typically the parent bus).
1168	*
1169	* @returns Pointer to the device instance of the bus.
1170	* @param pDevIns The PCI bus device instance.
1171	* @param idxPdmBus The PDM ordinal value of the bus to get.
1172	*/
1173	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1174
1175	/** Just a safety precaution. */
1176	uint32_t u32TheEnd;
1177	} PDMPCIHLPR0;
1178	/** Pointer to PCI helpers. */
1179	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1180	/** Pointer to const PCI helpers. */
1181	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1182
1183	/** Current PDMPCIHLPR0 version number. */
1184	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1185
1186	/**
1187	* PCI device helpers.
1188	*/
1189	typedef struct PDMPCIHLPR3
1190	{
1191	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1192	uint32_t u32Version;
1193
1194	/**
1195	* Set an ISA IRQ.
1196	*
1197	* @param pDevIns The PCI device instance.
1198	* @param iIrq IRQ number to set.
1199	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1200	* @param uTagSrc The IRQ tag and source (for tracing).
1201	*/
1202	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1203
1204	/**
1205	* Set an I/O-APIC IRQ.
1206	*
1207	* @param pDevIns The PCI device instance.
1208	* @param uBusDevFn The bus:device:function of the device initiating the
1209	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1210	* interrupt.
1211	* @param iIrq IRQ number to set.
1212	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1213	* @param uTagSrc The IRQ tag and source (for tracing).
1214	*/
1215	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1216
1217	/**
1218	* Send an MSI.
1219	*
1220	* @param pDevIns PCI device instance.
1221	* @param uBusDevFn The bus:device:function of the device initiating the
1222	* MSI. Cannot be NIL_PCIBDF.
1223	* @param pMsi The MSI to send.
1224	* @param uTagSrc The IRQ tag and source (for tracing).
1225	*/
1226	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1227
1228	/**
1229	* Acquires the PDM lock.
1230	*
1231	* @returns VINF_SUCCESS on success.
1232	* @returns Fatal error on failure.
1233	* @param pDevIns The PCI device instance.
1234	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1235	*
1236	* @sa PDMCritSectEnter
1237	*/
1238	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1239
1240	/**
1241	* Releases the PDM lock.
1242	*
1243	* @param pDevIns The PCI device instance.
1244	*/
1245	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1246
1247	/**
1248	* Gets a bus by it's PDM ordinal (typically the parent bus).
1249	*
1250	* @returns Pointer to the device instance of the bus.
1251	* @param pDevIns The PCI bus device instance.
1252	* @param idxPdmBus The PDM ordinal value of the bus to get.
1253	*/
1254	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1255
1256	/** Just a safety precaution. */
1257	uint32_t u32TheEnd;
1258	} PDMPCIHLPR3;
1259	/** Pointer to PCI helpers. */
1260	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1261	/** Pointer to const PCI helpers. */
1262	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1263
1264	/** Current PDMPCIHLPR3 version number. */
1265	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1266
1267
1268	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1269	* These flags are used for memory access transactions via the IOMMU interface.
1270	* @{ */
1271	/** Memory read. */
1272	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1273	/** Memory write. */
1274	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1275	/** Valid flag mask. */
1276	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1277	/** @} */
1278
1279	/**
1280	* IOMMU registration structure for ring-0.
1281	*/
1282	typedef struct PDMIOMMUREGR0
1283	{
1284	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1285	* version. */
1286	uint32_t u32Version;
1287	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1288	uint32_t idxIommu;
1289
1290	/**
1291	* Translates the physical address for a memory transaction through the IOMMU.
1292	*
1293	* @returns VBox status code.
1294	* @param pDevIns The IOMMU device instance.
1295	* @param idDevice The device identifier (bus, device, function).
1296	* @param uIova The I/O virtual address being accessed.
1297	* @param cbIova The size of the access.
1298	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1299	* @param pGCPhysSpa Where to store the translated system physical address.
1300	* @param pcbContiguous Where to store the number of contiguous bytes translated
1301	* and permission-checked.
1302	*
1303	* @thread Any.
1304	*/
1305	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1306	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1307
1308	/**
1309	* Translates in bulk physical page addresses for memory transactions through the
1310	* IOMMU.
1311	*
1312	* @returns VBox status code.
1313	* @param pDevIns The IOMMU device instance.
1314	* @param idDevice The device identifier (bus, device, function).
1315	* @param cIovas The number of I/O virtual addresses being accessed.
1316	* @param pauIovas The I/O virtual addresses being accessed.
1317	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1318	* @param paGCPhysSpa Where to store the translated system physical page
1319	* addresses.
1320	*
1321	* @thread Any.
1322	*/
1323	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1324	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1325
1326	/**
1327	* Performs an interrupt remap request through the IOMMU.
1328	*
1329	* @returns VBox status code.
1330	* @param pDevIns The IOMMU device instance.
1331	* @param idDevice The device identifier (bus, device, function).
1332	* @param pMsiIn The source MSI.
1333	* @param pMsiOut Where to store the remapped MSI.
1334	*
1335	* @thread Any.
1336	*/
1337	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1338
1339	/** Just a safety precaution. */
1340	uint32_t u32TheEnd;
1341	} PDMIOMMUREGR0;
1342	/** Pointer to a IOMMU registration structure. */
1343	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1344
1345	/** Current PDMIOMMUREG version number. */
1346	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1347
1348
1349	/**
1350	* IOMMU registration structure for raw-mode.
1351	*/
1352	typedef struct PDMIOMMUREGRC
1353	{
1354	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1355	* version. */
1356	uint32_t u32Version;
1357	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1358	uint32_t idxIommu;
1359
1360	/**
1361	* Translates the physical address for a memory transaction through the IOMMU.
1362	*
1363	* @returns VBox status code.
1364	* @param pDevIns The IOMMU device instance.
1365	* @param idDevice The device identifier (bus, device, function).
1366	* @param uIova The I/O virtual address being accessed.
1367	* @param cbIova The size of the access.
1368	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1369	* @param pGCPhysSpa Where to store the translated system physical address.
1370	* @param pcbContiguous Where to store the number of contiguous bytes translated
1371	* and permission-checked.
1372	*
1373	* @thread Any.
1374	*/
1375	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1376	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1377
1378	/**
1379	* Translates in bulk physical page addresses for memory transactions through the
1380	* IOMMU.
1381	*
1382	* @returns VBox status code.
1383	* @param pDevIns The IOMMU device instance.
1384	* @param idDevice The device identifier (bus, device, function).
1385	* @param cIovas The number of I/O virtual addresses being accessed.
1386	* @param pauIovas The I/O virtual addresses being accessed.
1387	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1388	* @param paGCPhysSpa Where to store the translated system physical page
1389	* addresses.
1390	*
1391	* @thread Any.
1392	*/
1393	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1394	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1395
1396	/**
1397	* Performs an interrupt remap request through the IOMMU.
1398	*
1399	* @returns VBox status code.
1400	* @param pDevIns The IOMMU device instance.
1401	* @param idDevice The device identifier (bus, device, function).
1402	* @param pMsiIn The source MSI.
1403	* @param pMsiOut Where to store the remapped MSI.
1404	*
1405	* @thread Any.
1406	*/
1407	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1408
1409	/** Just a safety precaution. */
1410	uint32_t u32TheEnd;
1411	} PDMIOMMUREGRC;
1412	/** Pointer to a IOMMU registration structure. */
1413	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1414
1415	/** Current PDMIOMMUREG version number. */
1416	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1417
1418
1419	/**
1420	* IOMMU registration structure for ring-3.
1421	*/
1422	typedef struct PDMIOMMUREGR3
1423	{
1424	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1425	* version. */
1426	uint32_t u32Version;
1427	/** Padding. */
1428	uint32_t uPadding0;
1429
1430	/**
1431	* Translates the physical address for a memory transaction through the IOMMU.
1432	*
1433	* @returns VBox status code.
1434	* @param pDevIns The IOMMU device instance.
1435	* @param idDevice The device identifier (bus, device, function).
1436	* @param uIova The I/O virtual address being accessed.
1437	* @param cbIova The size of the access.
1438	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1439	* @param pGCPhysSpa Where to store the translated system physical address.
1440	* @param pcbContiguous Where to store the number of contiguous bytes translated
1441	* and permission-checked.
1442	*
1443	* @thread Any.
1444	*/
1445	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1446	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1447
1448	/**
1449	* Translates in bulk physical page addresses for memory transactions through the
1450	* IOMMU.
1451	*
1452	* @returns VBox status code.
1453	* @param pDevIns The IOMMU device instance.
1454	* @param idDevice The device identifier (bus, device, function).
1455	* @param cIovas The number of I/O virtual addresses being accessed.
1456	* @param pauIovas The I/O virtual addresses being accessed.
1457	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1458	* @param paGCPhysSpa Where to store the translated system physical page
1459	* addresses.
1460	*
1461	* @thread Any.
1462	*/
1463	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1464	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1465
1466	/**
1467	* Performs an interrupt remap request through the IOMMU.
1468	*
1469	* @returns VBox status code.
1470	* @param pDevIns The IOMMU device instance.
1471	* @param idDevice The device identifier (bus, device, function).
1472	* @param pMsiIn The source MSI.
1473	* @param pMsiOut Where to store the remapped MSI.
1474	*
1475	* @thread Any.
1476	*/
1477	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1478
1479	/** Just a safety precaution. */
1480	uint32_t u32TheEnd;
1481	} PDMIOMMUREGR3;
1482	/** Pointer to a IOMMU registration structure. */
1483	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1484
1485	/** Current PDMIOMMUREG version number. */
1486	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1487
1488	/** IOMMU registration structure for the current context. */
1489	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1490	/** Pointer to an IOMMU registration structure for the current context. */
1491	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1492	/** IOMMU registration structure version for the current context. */
1493	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1494
1495
1496	/**
1497	* IOMMU helpers for ring-0.
1498	*/
1499	typedef struct PDMIOMMUHLPR0
1500	{
1501	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1502	uint32_t u32Version;
1503
1504	/**
1505	* Acquires the PDM lock.
1506	*
1507	* @returns VINF_SUCCESS on success.
1508	* @returns rc if we failed to acquire the lock.
1509	* @param pDevIns The PCI device instance.
1510	* @param rc What to return if we fail to acquire the lock.
1511	*
1512	* @sa PDMCritSectEnter
1513	*/
1514	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1515
1516	/**
1517	* Releases the PDM lock.
1518	*
1519	* @param pDevIns The PCI device instance.
1520	*/
1521	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1522
1523	/**
1524	* Check whether the calling thread owns the PDM lock.
1525	*
1526	* @returns @c true if the PDM lock is owned, @c false otherwise.
1527	* @param pDevIns The PCI device instance.
1528	*/
1529	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1530
1531	/**
1532	* Send an MSI (when generated by the IOMMU device itself).
1533	*
1534	* @param pDevIns PCI device instance.
1535	* @param pMsi The MSI to send.
1536	* @param uTagSrc The IRQ tag and source (for tracing).
1537	*/
1538	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1539
1540	/** Just a safety precaution. */
1541	uint32_t u32TheEnd;
1542	} PDMIOMMUHLPR0;
1543	/** Pointer to IOMMU helpers for ring-0. */
1544	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1545	/** Pointer to const IOMMU helpers for ring-0. */
1546	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1547
1548	/** Current PDMIOMMUHLPR0 version number. */
1549	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1550
1551
1552	/**
1553	* IOMMU helpers for raw-mode.
1554	*/
1555	typedef struct PDMIOMMUHLPRC
1556	{
1557	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1558	uint32_t u32Version;
1559
1560	/**
1561	* Acquires the PDM lock.
1562	*
1563	* @returns VINF_SUCCESS on success.
1564	* @returns rc if we failed to acquire the lock.
1565	* @param pDevIns The PCI device instance.
1566	* @param rc What to return if we fail to acquire the lock.
1567	*
1568	* @sa PDMCritSectEnter
1569	*/
1570	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1571
1572	/**
1573	* Releases the PDM lock.
1574	*
1575	* @param pDevIns The PCI device instance.
1576	*/
1577	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1578
1579	/**
1580	* Check whether the threads owns the PDM lock.
1581	*
1582	* @returns @c true if the PDM lock is owned, @c false otherwise.
1583	* @param pDevIns The PCI device instance.
1584	*/
1585	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1586
1587	/**
1588	* Send an MSI (when generated by the IOMMU device itself).
1589	*
1590	* @param pDevIns PCI device instance.
1591	* @param pMsi The MSI to send.
1592	* @param uTagSrc The IRQ tag and source (for tracing).
1593	*/
1594	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1595
1596	/** Just a safety precaution. */
1597	uint32_t u32TheEnd;
1598	} PDMIOMMUHLPRC;
1599	/** Pointer to IOMMU helpers for raw-mode. */
1600	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1601	/** Pointer to const IOMMU helpers for raw-mode. */
1602	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1603
1604	/** Current PDMIOMMUHLPRC version number. */
1605	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1606
1607
1608	/**
1609	* IOMMU helpers for ring-3.
1610	*/
1611	typedef struct PDMIOMMUHLPR3
1612	{
1613	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1614	uint32_t u32Version;
1615
1616	/**
1617	* Acquires the PDM lock.
1618	*
1619	* @returns VINF_SUCCESS on success.
1620	* @returns rc if we failed to acquire the lock.
1621	* @param pDevIns The PCI device instance.
1622	* @param rc What to return if we fail to acquire the lock.
1623	*
1624	* @sa PDMCritSectEnter
1625	*/
1626	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1627
1628	/**
1629	* Releases the PDM lock.
1630	*
1631	* @param pDevIns The PCI device instance.
1632	*/
1633	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1634
1635	/**
1636	* Check whether the threads owns the PDM lock.
1637	*
1638	* @returns @c true if the PDM lock is owned, @c false otherwise.
1639	* @param pDevIns The PCI device instance.
1640	*/
1641	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1642
1643	/**
1644	* Send an MSI (when generated by the IOMMU device itself).
1645	*
1646	* @param pDevIns PCI device instance.
1647	* @param pMsi The MSI to send.
1648	* @param uTagSrc The IRQ tag and source (for tracing).
1649	*/
1650	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1651
1652	/** Just a safety precaution. */
1653	uint32_t u32TheEnd;
1654	} PDMIOMMUHLPR3;
1655	/** Pointer to IOMMU helpers for raw-mode. */
1656	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1657	/** Pointer to const IOMMU helpers for raw-mode. */
1658	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1659
1660	/** Current PDMIOMMUHLPR3 version number. */
1661	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1662
1663
1664	/**
1665	* Programmable Interrupt Controller registration structure (all contexts).
1666	*/
1667	typedef struct PDMPICREG
1668	{
1669	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1670	uint32_t u32Version;
1671
1672	/**
1673	* Set the an IRQ.
1674	*
1675	* @param pDevIns Device instance of the PIC.
1676	* @param iIrq IRQ number to set.
1677	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1678	* @param uTagSrc The IRQ tag and source (for tracing).
1679	* @remarks Caller enters the PDM critical section.
1680	*/
1681	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1682
1683	/**
1684	* Get a pending interrupt.
1685	*
1686	* @returns Pending interrupt number.
1687	* @param pDevIns Device instance of the PIC.
1688	* @param puTagSrc Where to return the IRQ tag and source.
1689	* @remarks Caller enters the PDM critical section.
1690	*/
1691	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1692
1693	/** Just a safety precaution. */
1694	uint32_t u32TheEnd;
1695	} PDMPICREG;
1696	/** Pointer to a PIC registration structure. */
1697	typedef PDMPICREG *PPDMPICREG;
1698
1699	/** Current PDMPICREG version number. */
1700	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1701
1702	/**
1703	* PIC helpers, same in all contexts.
1704	*/
1705	typedef struct PDMPICHLP
1706	{
1707	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1708	uint32_t u32Version;
1709
1710	/**
1711	* Set the interrupt force action flag.
1712	*
1713	* @param pDevIns Device instance of the PIC.
1714	*/
1715	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1716
1717	/**
1718	* Clear the interrupt force action flag.
1719	*
1720	* @param pDevIns Device instance of the PIC.
1721	*/
1722	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1723
1724	/**
1725	* Acquires the PDM lock.
1726	*
1727	* @returns VINF_SUCCESS on success.
1728	* @returns rc if we failed to acquire the lock.
1729	* @param pDevIns The PIC device instance.
1730	* @param rc What to return if we fail to acquire the lock.
1731	*
1732	* @sa PDMCritSectEnter
1733	*/
1734	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1735
1736	/**
1737	* Releases the PDM lock.
1738	*
1739	* @param pDevIns The PIC device instance.
1740	*/
1741	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1742
1743	/** Just a safety precaution. */
1744	uint32_t u32TheEnd;
1745	} PDMPICHLP;
1746	/** Pointer to PIC helpers. */
1747	typedef PDMPICHLP *PPDMPICHLP;
1748	/** Pointer to const PIC helpers. */
1749	typedef const PDMPICHLP *PCPDMPICHLP;
1750
1751	/** Current PDMPICHLP version number. */
1752	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1753
1754
1755	/**
1756	* Firmware registration structure.
1757	*/
1758	typedef struct PDMFWREG
1759	{
1760	/** Struct version+magic number (PDM_FWREG_VERSION). */
1761	uint32_t u32Version;
1762
1763	/**
1764	* Checks whether this is a hard or soft reset.
1765	*
1766	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1767	* is 5, 9 or 0xA.
1768	*
1769	* @returns true if hard reset, false if soft.
1770	* @param pDevIns Device instance of the firmware.
1771	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1772	*/
1773	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1774
1775	/** Just a safety precaution. */
1776	uint32_t u32TheEnd;
1777	} PDMFWREG;
1778	/** Pointer to a FW registration structure. */
1779	typedef PDMFWREG *PPDMFWREG;
1780	/** Pointer to a const FW registration structure. */
1781	typedef PDMFWREG const *PCPDMFWREG;
1782
1783	/** Current PDMFWREG version number. */
1784	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1785
1786	/**
1787	* Firmware R3 helpers.
1788	*/
1789	typedef struct PDMFWHLPR3
1790	{
1791	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1792	uint32_t u32Version;
1793
1794	/** Just a safety precaution. */
1795	uint32_t u32TheEnd;
1796	} PDMFWHLPR3;
1797
1798	/** Pointer to FW R3 helpers. */
1799	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1800	/** Pointer to const FW R3 helpers. */
1801	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1802
1803	/** Current PDMFWHLPR3 version number. */
1804	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1805
1806
1807	/**
1808	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1809	*
1810	* Also used in saved-states, CFGM don't change existing values.
1811	*/
1812	typedef enum PDMAPICMODE
1813	{
1814	/** Invalid 0 entry. */
1815	PDMAPICMODE_INVALID = 0,
1816	/** No APIC. */
1817	PDMAPICMODE_NONE,
1818	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1819	PDMAPICMODE_APIC,
1820	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1821	PDMAPICMODE_X2APIC,
1822	/** The usual 32-bit paranoia. */
1823	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1824	} PDMAPICMODE;
1825
1826	/**
1827	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1828	*/
1829	typedef enum PDMAPICIRQ
1830	{
1831	/** Invalid 0 entry. */
1832	PDMAPICIRQ_INVALID = 0,
1833	/** Normal hardware interrupt. */
1834	PDMAPICIRQ_HARDWARE,
1835	/** NMI. */
1836	PDMAPICIRQ_NMI,
1837	/** SMI. */
1838	PDMAPICIRQ_SMI,
1839	/** ExtINT (HW interrupt via PIC). */
1840	PDMAPICIRQ_EXTINT,
1841	/** Interrupt arrived, needs to be updated to the IRR. */
1842	PDMAPICIRQ_UPDATE_PENDING,
1843	/** The usual 32-bit paranoia. */
1844	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1845	} PDMAPICIRQ;
1846
1847
1848	/**
1849	* I/O APIC registration structure (all contexts).
1850	*/
1851	typedef struct PDMIOAPICREG
1852	{
1853	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1854	uint32_t u32Version;
1855
1856	/**
1857	* Set an IRQ.
1858	*
1859	* @param pDevIns Device instance of the I/O APIC.
1860	* @param uBusDevFn The bus:device:function of the device initiating the
1861	* IRQ. Can be NIL_PCIBDF.
1862	* @param iIrq IRQ number to set.
1863	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1864	* @param uTagSrc The IRQ tag and source (for tracing).
1865	*
1866	* @remarks Caller enters the PDM critical section
1867	* Actually, as per 2018-07-21 this isn't true (bird).
1868	*/
1869	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1870
1871	/**
1872	* Send a MSI.
1873	*
1874	* @param pDevIns Device instance of the I/O APIC.
1875	* @param uBusDevFn The bus:device:function of the device initiating the
1876	* MSI. Cannot be NIL_PCIBDF.
1877	* @param pMsi The MSI to send.
1878	* @param uTagSrc The IRQ tag and source (for tracing).
1879	*
1880	* @remarks Caller enters the PDM critical section
1881	* Actually, as per 2018-07-21 this isn't true (bird).
1882	*/
1883	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1884
1885	/**
1886	* Set the EOI for an interrupt vector.
1887	*
1888	* @param pDevIns Device instance of the I/O APIC.
1889	* @param u8Vector The vector.
1890	*
1891	* @remarks Caller enters the PDM critical section
1892	* Actually, as per 2018-07-21 this isn't true (bird).
1893	*/
1894	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1895
1896	/** Just a safety precaution. */
1897	uint32_t u32TheEnd;
1898	} PDMIOAPICREG;
1899	/** Pointer to an APIC registration structure. */
1900	typedef PDMIOAPICREG *PPDMIOAPICREG;
1901
1902	/** Current PDMAPICREG version number. */
1903	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1904
1905
1906	/**
1907	* IOAPIC helpers, same in all contexts.
1908	*/
1909	typedef struct PDMIOAPICHLP
1910	{
1911	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1912	uint32_t u32Version;
1913
1914	/**
1915	* Private interface between the IOAPIC and APIC.
1916	*
1917	* @returns status code.
1918	* @param pDevIns Device instance of the IOAPIC.
1919	* @param u8Dest See APIC implementation.
1920	* @param u8DestMode See APIC implementation.
1921	* @param u8DeliveryMode See APIC implementation.
1922	* @param uVector See APIC implementation.
1923	* @param u8Polarity See APIC implementation.
1924	* @param u8TriggerMode See APIC implementation.
1925	* @param uTagSrc The IRQ tag and source (for tracing).
1926	*
1927	* @sa APICBusDeliver()
1928	*/
1929	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1930	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1931
1932	/**
1933	* Acquires the PDM lock.
1934	*
1935	* @returns VINF_SUCCESS on success.
1936	* @returns rc if we failed to acquire the lock.
1937	* @param pDevIns The IOAPIC device instance.
1938	* @param rc What to return if we fail to acquire the lock.
1939	*
1940	* @sa PDMCritSectEnter
1941	*/
1942	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1943
1944	/**
1945	* Releases the PDM lock.
1946	*
1947	* @param pDevIns The IOAPIC device instance.
1948	*/
1949	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1950
1951	/**
1952	* Checks if the calling thread owns the PDM lock.
1953	*
1954	* @param pDevIns The IOAPIC device instance.
1955	*/
1956	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1957
1958	/**
1959	* Private interface between the IOAPIC and IOMMU.
1960	*
1961	* @returns status code.
1962	* @param pDevIns Device instance of the IOAPIC.
1963	* @param idDevice The device identifier (bus, device, function).
1964	* @param pMsiIn The source MSI.
1965	* @param pMsiOut Where to store the remapped MSI (only updated when
1966	* VINF_SUCCESS is returned).
1967	*/
1968	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1969
1970	/** Just a safety precaution. */
1971	uint32_t u32TheEnd;
1972	} PDMIOAPICHLP;
1973	/** Pointer to IOAPIC helpers. */
1974	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1975	/** Pointer to const IOAPIC helpers. */
1976	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1977
1978	/** Current PDMIOAPICHLP version number. */
1979	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1980
1981
1982	/**
1983	* HPET registration structure.
1984	*/
1985	typedef struct PDMHPETREG
1986	{
1987	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1988	uint32_t u32Version;
1989	} PDMHPETREG;
1990	/** Pointer to an HPET registration structure. */
1991	typedef PDMHPETREG *PPDMHPETREG;
1992
1993	/** Current PDMHPETREG version number. */
1994	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1995
1996	/**
1997	* HPET RC helpers.
1998	*
1999	* @remarks Keep this around in case HPET will need PDM interaction in again RC
2000	* at some later point.
2001	*/
2002	typedef struct PDMHPETHLPRC
2003	{
2004	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
2005	uint32_t u32Version;
2006
2007	/** Just a safety precaution. */
2008	uint32_t u32TheEnd;
2009	} PDMHPETHLPRC;
2010
2011	/** Pointer to HPET RC helpers. */
2012	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
2013	/** Pointer to const HPET RC helpers. */
2014	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
2015
2016	/** Current PDMHPETHLPRC version number. */
2017	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
2018
2019
2020	/**
2021	* HPET R0 helpers.
2022	*
2023	* @remarks Keep this around in case HPET will need PDM interaction in again R0
2024	* at some later point.
2025	*/
2026	typedef struct PDMHPETHLPR0
2027	{
2028	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2029	uint32_t u32Version;
2030
2031	/** Just a safety precaution. */
2032	uint32_t u32TheEnd;
2033	} PDMHPETHLPR0;
2034
2035	/** Pointer to HPET R0 helpers. */
2036	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2037	/** Pointer to const HPET R0 helpers. */
2038	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2039
2040	/** Current PDMHPETHLPR0 version number. */
2041	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2042
2043	/**
2044	* HPET R3 helpers.
2045	*/
2046	typedef struct PDMHPETHLPR3
2047	{
2048	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2049	uint32_t u32Version;
2050
2051	/**
2052	* Set legacy mode on PIT and RTC.
2053	*
2054	* @returns VINF_SUCCESS on success.
2055	* @returns rc if we failed to set legacy mode.
2056	* @param pDevIns Device instance of the HPET.
2057	* @param fActivated Whether legacy mode is activated or deactivated.
2058	*/
2059	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2060
2061
2062	/**
2063	* Set IRQ, bypassing ISA bus override rules.
2064	*
2065	* @returns VINF_SUCCESS on success.
2066	* @returns rc if we failed to set legacy mode.
2067	* @param pDevIns Device instance of the HPET.
2068	* @param iIrq IRQ number to set.
2069	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2070	*/
2071	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2072
2073	/** Just a safety precaution. */
2074	uint32_t u32TheEnd;
2075	} PDMHPETHLPR3;
2076
2077	/** Pointer to HPET R3 helpers. */
2078	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2079	/** Pointer to const HPET R3 helpers. */
2080	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2081
2082	/** Current PDMHPETHLPR3 version number. */
2083	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2084
2085
2086	/**
2087	* Raw PCI device registration structure.
2088	*/
2089	typedef struct PDMPCIRAWREG
2090	{
2091	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2092	uint32_t u32Version;
2093	/** Just a safety precaution. */
2094	uint32_t u32TheEnd;
2095	} PDMPCIRAWREG;
2096	/** Pointer to a raw PCI registration structure. */
2097	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2098
2099	/** Current PDMPCIRAWREG version number. */
2100	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2101
2102	/**
2103	* Raw PCI device raw-mode context helpers.
2104	*/
2105	typedef struct PDMPCIRAWHLPRC
2106	{
2107	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2108	uint32_t u32Version;
2109	/** Just a safety precaution. */
2110	uint32_t u32TheEnd;
2111	} PDMPCIRAWHLPRC;
2112	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2113	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2114	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2115	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2116
2117	/** Current PDMPCIRAWHLPRC version number. */
2118	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2119
2120	/**
2121	* Raw PCI device ring-0 context helpers.
2122	*/
2123	typedef struct PDMPCIRAWHLPR0
2124	{
2125	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2126	uint32_t u32Version;
2127	/** Just a safety precaution. */
2128	uint32_t u32TheEnd;
2129	} PDMPCIRAWHLPR0;
2130	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2131	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2132	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2133	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2134
2135	/** Current PDMPCIRAWHLPR0 version number. */
2136	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2137
2138
2139	/**
2140	* Raw PCI device ring-3 context helpers.
2141	*/
2142	typedef struct PDMPCIRAWHLPR3
2143	{
2144	/** Undefined structure version and magic number. */
2145	uint32_t u32Version;
2146
2147	/**
2148	* Gets the address of the RC raw PCI device helpers.
2149	*
2150	* This should be called at both construction and relocation time to obtain
2151	* the correct address of the RC helpers.
2152	*
2153	* @returns RC pointer to the raw PCI device helpers.
2154	* @param pDevIns Device instance of the raw PCI device.
2155	*/
2156	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2157
2158	/**
2159	* Gets the address of the R0 raw PCI device helpers.
2160	*
2161	* This should be called at both construction and relocation time to obtain
2162	* the correct address of the R0 helpers.
2163	*
2164	* @returns R0 pointer to the raw PCI device helpers.
2165	* @param pDevIns Device instance of the raw PCI device.
2166	*/
2167	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2168
2169	/** Just a safety precaution. */
2170	uint32_t u32TheEnd;
2171	} PDMPCIRAWHLPR3;
2172	/** Pointer to raw PCI R3 helpers. */
2173	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2174	/** Pointer to const raw PCI R3 helpers. */
2175	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2176
2177	/** Current PDMPCIRAWHLPR3 version number. */
2178	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2179
2180
2181	#ifdef IN_RING3
2182
2183	/**
2184	* DMA Transfer Handler.
2185	*
2186	* @returns Number of bytes transferred.
2187	* @param pDevIns The device instance that registered the handler.
2188	* @param pvUser User pointer.
2189	* @param uChannel Channel number.
2190	* @param off DMA position.
2191	* @param cb Block size.
2192	* @remarks The device lock is take before the callback (in fact, the locks of
2193	* DMA devices and the DMA controller itself are taken).
2194	*/
2195	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2196	uint32_t off, uint32_t cb));
2197	/** Pointer to a FNDMATRANSFERHANDLER(). */
2198	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2199
2200	/**
2201	* DMA Controller registration structure.
2202	*/
2203	typedef struct PDMDMAREG
2204	{
2205	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2206	uint32_t u32Version;
2207
2208	/**
2209	* Execute pending transfers.
2210	*
2211	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2212	* @param pDevIns Device instance of the DMAC.
2213	* @remarks No locks held, called on EMT(0) as a form of serialization.
2214	*/
2215	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2216
2217	/**
2218	* Register transfer function for DMA channel.
2219	*
2220	* @param pDevIns Device instance of the DMAC.
2221	* @param uChannel Channel number.
2222	* @param pDevInsHandler The device instance of the device making the
2223	* regstration (will be passed to the callback).
2224	* @param pfnTransferHandler Device specific transfer function.
2225	* @param pvUser User pointer to be passed to the callback.
2226	* @remarks No locks held, called on an EMT.
2227	*/
2228	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2229	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2230
2231	/**
2232	* Read memory
2233	*
2234	* @returns Number of bytes read.
2235	* @param pDevIns Device instance of the DMAC.
2236	* @param uChannel Channel number.
2237	* @param pvBuffer Pointer to target buffer.
2238	* @param off DMA position.
2239	* @param cbBlock Block size.
2240	* @remarks No locks held, called on an EMT.
2241	*/
2242	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2243
2244	/**
2245	* Write memory
2246	*
2247	* @returns Number of bytes written.
2248	* @param pDevIns Device instance of the DMAC.
2249	* @param uChannel Channel number.
2250	* @param pvBuffer Memory to write.
2251	* @param off DMA position.
2252	* @param cbBlock Block size.
2253	* @remarks No locks held, called on an EMT.
2254	*/
2255	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2256
2257	/**
2258	* Set the DREQ line.
2259	*
2260	* @param pDevIns Device instance of the DMAC.
2261	* @param uChannel Channel number.
2262	* @param uLevel Level of the line.
2263	* @remarks No locks held, called on an EMT.
2264	*/
2265	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2266
2267	/**
2268	* Get channel mode
2269	*
2270	* @returns Channel mode.
2271	* @param pDevIns Device instance of the DMAC.
2272	* @param uChannel Channel number.
2273	* @remarks No locks held, called on an EMT.
2274	*/
2275	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2276
2277	} PDMDMACREG;
2278	/** Pointer to a DMAC registration structure. */
2279	typedef PDMDMACREG *PPDMDMACREG;
2280
2281	/** Current PDMDMACREG version number. */
2282	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2283
2284
2285	/**
2286	* DMA Controller device helpers.
2287	*/
2288	typedef struct PDMDMACHLP
2289	{
2290	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2291	uint32_t u32Version;
2292
2293	/* to-be-defined */
2294
2295	} PDMDMACHLP;
2296	/** Pointer to DMAC helpers. */
2297	typedef PDMDMACHLP *PPDMDMACHLP;
2298	/** Pointer to const DMAC helpers. */
2299	typedef const PDMDMACHLP *PCPDMDMACHLP;
2300
2301	/** Current PDMDMACHLP version number. */
2302	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2303
2304	#endif /* IN_RING3 */
2305
2306
2307
2308	/**
2309	* RTC registration structure.
2310	*/
2311	typedef struct PDMRTCREG
2312	{
2313	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2314	uint32_t u32Version;
2315	uint32_t u32Alignment; /*< structure size alignment. /
2316
2317	/**
2318	* Write to a CMOS register and update the checksum if necessary.
2319	*
2320	* @returns VBox status code.
2321	* @param pDevIns Device instance of the RTC.
2322	* @param iReg The CMOS register index.
2323	* @param u8Value The CMOS register value.
2324	* @remarks Caller enters the device critical section.
2325	*/
2326	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2327
2328	/**
2329	* Read a CMOS register.
2330	*
2331	* @returns VBox status code.
2332	* @param pDevIns Device instance of the RTC.
2333	* @param iReg The CMOS register index.
2334	* @param pu8Value Where to store the CMOS register value.
2335	* @remarks Caller enters the device critical section.
2336	*/
2337	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2338
2339	} PDMRTCREG;
2340	/** Pointer to a RTC registration structure. */
2341	typedef PDMRTCREG *PPDMRTCREG;
2342	/** Pointer to a const RTC registration structure. */
2343	typedef const PDMRTCREG *PCPDMRTCREG;
2344
2345	/** Current PDMRTCREG version number. */
2346	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2347
2348
2349	/**
2350	* RTC device helpers.
2351	*/
2352	typedef struct PDMRTCHLP
2353	{
2354	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2355	uint32_t u32Version;
2356
2357	/* to-be-defined */
2358
2359	} PDMRTCHLP;
2360	/** Pointer to RTC helpers. */
2361	typedef PDMRTCHLP *PPDMRTCHLP;
2362	/** Pointer to const RTC helpers. */
2363	typedef const PDMRTCHLP *PCPDMRTCHLP;
2364
2365	/** Current PDMRTCHLP version number. */
2366	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2367
2368
2369
2370	/** @name Flags for PCI I/O region registration
2371	* @{ */
2372	/** No handle is passed. */
2373	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2374	/** An I/O port handle is passed. */
2375	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2376	/** An MMIO range handle is passed. */
2377	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2378	/** An MMIO2 handle is passed. */
2379	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2380	/** Handle type mask. */
2381	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2382	/** New-style (mostly wrt callbacks). */
2383	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2384	/** Mask of valid flags. */
2385	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2386	/** @} */
2387
2388
2389	/** @name Flags for the guest physical read/write helpers
2390	* @{ */
2391	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2392	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2393	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2394	* by the device in any way. */
2395	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2396	/** The data is metadata and being processed by the device in some way. */
2397	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2398	/** @} */
2399
2400
2401	#ifdef IN_RING3
2402
2403	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2404	* @{ */
2405	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2406	* This is handy when registering multiple PCI device functions and the device
2407	* number is left up to the PCI bus. In order to facilitate one PDM device
2408	* instance for each PCI function, this searches earlier PDM device
2409	* instances as well. */
2410	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2411	/** Use the first unused device number (all functions must be unused). */
2412	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2413	/** Use the first unused device function. */
2414	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2415
2416	/** The device and function numbers are not mandatory, just suggestions. */
2417	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2418	/** Registering a PCI bridge device. */
2419	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2420	/** Valid flag mask. */
2421	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2422	/** @} */
2423
2424	/** Current PDMDEVHLPR3 version number. */
2425	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 49, 1)
2426
2427	/**
2428	* PDM Device API.
2429	*/
2430	typedef struct PDMDEVHLPR3
2431	{
2432	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2433	uint32_t u32Version;
2434
2435	/** @name I/O ports
2436	* @{ */
2437	/**
2438	* Creates a range of I/O ports for a device.
2439	*
2440	* The I/O port range must be mapped in a separately call. Any ring-0 and
2441	* raw-mode context callback handlers needs to be set up in the respective
2442	* contexts.
2443	*
2444	* @returns VBox status.
2445	* @param pDevIns The device instance to register the ports with.
2446	* @param cPorts Number of ports to register.
2447	* @param fFlags IOM_IOPORT_F_XXX.
2448	* @param pPciDev The PCI device the range is associated with, if
2449	* applicable.
2450	* @param iPciRegion The PCI device region in the high 16-bit word and
2451	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2452	* @param pfnOut Pointer to function which is gonna handle OUT
2453	* operations. Optional.
2454	* @param pfnIn Pointer to function which is gonna handle IN operations.
2455	* Optional.
2456	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2457	* operations. Optional.
2458	* @param pfnInStr Pointer to function which is gonna handle string IN
2459	* operations. Optional.
2460	* @param pvUser User argument to pass to the callbacks.
2461	* @param pszDesc Pointer to description string. This must not be freed.
2462	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2463	* coverage is allowed. This must not be freed.
2464	* @param phIoPorts Where to return the I/O port range handle.
2465	*
2466	* @remarks Caller enters the device critical section prior to invoking the
2467	* registered callback methods.
2468	*
2469	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2470	* PDMDevHlpIoPortUnmap.
2471	*/
2472	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2473	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2474	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2475	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2476
2477	/**
2478	* Maps an I/O port range.
2479	*
2480	* @returns VBox status.
2481	* @param pDevIns The device instance to register the ports with.
2482	* @param hIoPorts The I/O port range handle.
2483	* @param Port Where to map the range.
2484	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2485	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2486	*/
2487	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2488
2489	/**
2490	* Unmaps an I/O port range.
2491	*
2492	* @returns VBox status.
2493	* @param pDevIns The device instance to register the ports with.
2494	* @param hIoPorts The I/O port range handle.
2495	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2496	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2497	*/
2498	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2499
2500	/**
2501	* Gets the mapping address of the I/O port range @a hIoPorts.
2502	*
2503	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2504	* parameters).
2505	* @param pDevIns The device instance to register the ports with.
2506	* @param hIoPorts The I/O port range handle.
2507	*/
2508	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2509	/** @} */
2510
2511	/** @name MMIO
2512	* @{ */
2513	/**
2514	* Creates a memory mapped I/O (MMIO) region for a device.
2515	*
2516	* The MMIO region must be mapped in a separately call. Any ring-0 and
2517	* raw-mode context callback handlers needs to be set up in the respective
2518	* contexts.
2519	*
2520	* @returns VBox status.
2521	* @param pDevIns The device instance to register the ports with.
2522	* @param cbRegion The size of the region in bytes.
2523	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2524	* @param pPciDev The PCI device the range is associated with, if
2525	* applicable.
2526	* @param iPciRegion The PCI device region in the high 16-bit word and
2527	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2528	* @param pfnWrite Pointer to function which is gonna handle Write
2529	* operations.
2530	* @param pfnRead Pointer to function which is gonna handle Read
2531	* operations.
2532	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2533	* operations. (optional)
2534	* @param pvUser User argument to pass to the callbacks.
2535	* @param pszDesc Pointer to description string. This must not be freed.
2536	* @param phRegion Where to return the MMIO region handle.
2537	*
2538	* @remarks Caller enters the device critical section prior to invoking the
2539	* registered callback methods.
2540	*
2541	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2542	*/
2543	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2544	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2545	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2546	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2547
2548	/**
2549	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2550	*
2551	* @returns VBox status.
2552	* @param pDevIns The device instance the region is associated with.
2553	* @param hRegion The MMIO region handle.
2554	* @param GCPhys Where to map the region.
2555	* @note An MMIO range may overlap with base memory if a lot of RAM is
2556	* configured for the VM, in which case we'll drop the base memory
2557	* pages. Presently we will make no attempt to preserve anything that
2558	* happens to be present in the base memory that is replaced, this is
2559	* technically incorrect but it's just not worth the effort to do
2560	* right, at least not at this point.
2561	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2562	* PDMDevHlpMmioSetUpContext
2563	*/
2564	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2565
2566	/**
2567	* Unmaps a memory mapped I/O (MMIO) region.
2568	*
2569	* @returns VBox status.
2570	* @param pDevIns The device instance the region is associated with.
2571	* @param hRegion The MMIO region handle.
2572	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2573	* PDMDevHlpMmioSetUpContext
2574	*/
2575	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2576
2577	/**
2578	* Reduces the length of a MMIO range.
2579	*
2580	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2581	* only work during saved state restore. It will not call the PCI bus code, as
2582	* that is expected to restore the saved resource configuration.
2583	*
2584	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2585	* called it will only map @a cbRegion bytes and not the value set during
2586	* registration.
2587	*
2588	* @return VBox status code.
2589	* @param pDevIns The device owning the range.
2590	* @param hRegion The MMIO region handle.
2591	* @param cbRegion The new size, must be smaller.
2592	*/
2593	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2594
2595	/**
2596	* Gets the mapping address of the MMIO region @a hRegion.
2597	*
2598	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2599	* @param pDevIns The device instance to register the ports with.
2600	* @param hRegion The MMIO region handle.
2601	*/
2602	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2603	/** @} */
2604
2605	/** @name MMIO2
2606	* @{ */
2607	/**
2608	* Creates a MMIO2 region.
2609	*
2610	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2611	* associated with a device. It is also non-shared memory with a permanent
2612	* ring-3 mapping and page backing (presently).
2613	*
2614	* @returns VBox status.
2615	* @param pDevIns The device instance.
2616	* @param pPciDev The PCI device the region is associated with, or
2617	* NULL if no PCI device association.
2618	* @param iPciRegion The region number. Use the PCI region number as
2619	* this must be known to the PCI bus device too. If
2620	* it's not associated with the PCI device, then
2621	* any number up to UINT8_MAX is fine.
2622	* @param cbRegion The size (in bytes) of the region.
2623	* @param fFlags Reserved for future use, must be zero.
2624	* @param pszDesc Pointer to description string. This must not be
2625	* freed.
2626	* @param ppvMapping Where to store the address of the ring-3 mapping
2627	* of the memory.
2628	* @param phRegion Where to return the MMIO2 region handle.
2629	*
2630	* @thread EMT(0)
2631	*/
2632	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2633	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2634
2635	/**
2636	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2637	*
2638	* Any physical access handlers registered for the region must be deregistered
2639	* before calling this function.
2640	*
2641	* @returns VBox status code.
2642	* @param pDevIns The device instance.
2643	* @param hRegion The MMIO2 region handle.
2644	* @thread EMT.
2645	*/
2646	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2647
2648	/**
2649	* Maps a MMIO2 region (into the guest physical address space).
2650	*
2651	* @returns VBox status.
2652	* @param pDevIns The device instance the region is associated with.
2653	* @param hRegion The MMIO2 region handle.
2654	* @param GCPhys Where to map the region.
2655	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2656	* configured for the VM, in which case we'll drop the base memory
2657	* pages. Presently we will make no attempt to preserve anything that
2658	* happens to be present in the base memory that is replaced, this is
2659	* technically incorrect but it's just not worth the effort to do
2660	* right, at least not at this point.
2661	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2662	*/
2663	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2664
2665	/**
2666	* Unmaps a MMIO2 region.
2667	*
2668	* @returns VBox status.
2669	* @param pDevIns The device instance the region is associated with.
2670	* @param hRegion The MMIO2 region handle.
2671	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2672	*/
2673	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2674
2675	/**
2676	* Reduces the length of a MMIO range.
2677	*
2678	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2679	* only work during saved state restore. It will not call the PCI bus code, as
2680	* that is expected to restore the saved resource configuration.
2681	*
2682	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2683	* called it will only map @a cbRegion bytes and not the value set during
2684	* registration.
2685	*
2686	* @return VBox status code.
2687	* @param pDevIns The device owning the range.
2688	* @param hRegion The MMIO2 region handle.
2689	* @param cbRegion The new size, must be smaller.
2690	*/
2691	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2692
2693	/**
2694	* Gets the mapping address of the MMIO region @a hRegion.
2695	*
2696	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2697	* @param pDevIns The device instance to register the ports with.
2698	* @param hRegion The MMIO2 region handle.
2699	*/
2700	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2701
2702	/**
2703	* Changes the number of an MMIO2 or pre-registered MMIO region.
2704	*
2705	* This should only be used to deal with saved state problems, so there is no
2706	* convenience inline wrapper for this method.
2707	*
2708	* @returns VBox status code.
2709	* @param pDevIns The device instance.
2710	* @param hRegion The MMIO2 region handle.
2711	* @param iNewRegion The new region index.
2712	*
2713	* @sa @bugref{9359}
2714	*/
2715	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2716	/** @} */
2717
2718	/**
2719	* Register a ROM (BIOS) region.
2720	*
2721	* It goes without saying that this is read-only memory. The memory region must be
2722	* in unassigned memory. I.e. from the top of the address space or on the PC in
2723	* the 0xa0000-0xfffff range.
2724	*
2725	* @returns VBox status.
2726	* @param pDevIns The device instance owning the ROM region.
2727	* @param GCPhysStart First physical address in the range.
2728	* Must be page aligned!
2729	* @param cbRange The size of the range (in bytes).
2730	* Must be page aligned!
2731	* @param pvBinary Pointer to the binary data backing the ROM image.
2732	* @param cbBinary The size of the binary pointer. This must
2733	* be equal or smaller than @a cbRange.
2734	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2735	* @param pszDesc Pointer to description string. This must not be freed.
2736	*
2737	* @remark There is no way to remove the rom, automatically on device cleanup or
2738	* manually from the device yet. At present I doubt we need such features...
2739	*/
2740	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2741	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2742
2743	/**
2744	* Changes the protection of shadowed ROM mapping.
2745	*
2746	* This is intented for use by the system BIOS, chipset or device in question to
2747	* change the protection of shadowed ROM code after init and on reset.
2748	*
2749	* @param pDevIns The device instance.
2750	* @param GCPhysStart Where the mapping starts.
2751	* @param cbRange The size of the mapping.
2752	* @param enmProt The new protection type.
2753	*/
2754	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2755
2756	/**
2757	* Register a save state data unit.
2758	*
2759	* @returns VBox status.
2760	* @param pDevIns The device instance.
2761	* @param uVersion Data layout version number.
2762	* @param cbGuess The approximate amount of data in the unit.
2763	* Only for progress indicators.
2764	* @param pszBefore Name of data unit which we should be put in
2765	* front of. Optional (NULL).
2766	*
2767	* @param pfnLivePrep Prepare live save callback, optional.
2768	* @param pfnLiveExec Execute live save callback, optional.
2769	* @param pfnLiveVote Vote live save callback, optional.
2770	*
2771	* @param pfnSavePrep Prepare save callback, optional.
2772	* @param pfnSaveExec Execute save callback, optional.
2773	* @param pfnSaveDone Done save callback, optional.
2774	*
2775	* @param pfnLoadPrep Prepare load callback, optional.
2776	* @param pfnLoadExec Execute load callback, optional.
2777	* @param pfnLoadDone Done load callback, optional.
2778	* @remarks Caller enters the device critical section prior to invoking the
2779	* registered callback methods.
2780	*/
2781	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2782	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2783	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2784	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2785
2786	/** @name Exported SSM Functions
2787	* @{ */
2788	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2789	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2790	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2791	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2792	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2793	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2794	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2795	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2796	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2797	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2798	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2799	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2800	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2801	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2802	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2803	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2804	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2805	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2806	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2807	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2808	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2809	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2810	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2811	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2812	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2813	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2814	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2815	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2816	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2817	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2818	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2819	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2820	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2821	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2822	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2823	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2824	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2825	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2826	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2827	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2828	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2829	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2830	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2831	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2832	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2833	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2834	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2835	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2836	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2837	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2838	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2839	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2840	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2841	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2842	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2843	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2844	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2845	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2846	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2847	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2848	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2849	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2850	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2851	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2852	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2853	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2854	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2855	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2856	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2857	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2858	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2859	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2860	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2861	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2862	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2863	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2864	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2865	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2866	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2867	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2868	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2869	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2870	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2871	/** @} */
2872
2873	/**
2874	* Creates a timer w/ a cross context handle.
2875	*
2876	* @returns VBox status.
2877	* @param pDevIns The device instance.
2878	* @param enmClock The clock to use on this timer.
2879	* @param pfnCallback Callback function.
2880	* @param pvUser User argument for the callback.
2881	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2882	* @param pszDesc Pointer to description string which must stay around
2883	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2884	* @param phTimer Where to store the timer handle on success.
2885	* @remarks Caller enters the device critical section prior to invoking the
2886	* callback.
2887	*/
2888	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2889	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2890
2891	/** @name Timer handle method wrappers
2892	* @{ */
2893	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2894	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2895	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2896	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2897	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2898	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2899	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2900	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2901	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2902	/** Takes the clock lock then enters the specified critical section. */
2903	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2904	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2905	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2906	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2907	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2908	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2909	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2910	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2911	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2912	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2913	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2914	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2915	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2916	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2917	/** @sa TMR3TimerSkip */
2918	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2919	/** @} */
2920
2921	/**
2922	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2923	*
2924	* @returns pTime.
2925	* @param pDevIns The device instance.
2926	* @param pTime Where to store the time.
2927	*/
2928	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2929
2930	/** @name Exported CFGM Functions.
2931	* @{ */
2932	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2933	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2934	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2935	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2936	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2937	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2938	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2939	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2940	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2941	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2942	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2943	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2944	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2945	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2946	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2947	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2948	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2949	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2950	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2951	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2952	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2953	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2954	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2955	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2956	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2957	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2958	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2959	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2960	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
2961	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
2962	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
2963	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
2964	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
2965	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
2966	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2967	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2968	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2969	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2970	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2971	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2972	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
2973	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
2974	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2975	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2976	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2977	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2978	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2979	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2980	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2981	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2982	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2983	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2984	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2985	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2986	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2987	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2988	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2989	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2990	const char pszValidValues, const char pszValidNodes,
2991	const char *pszWho, uint32_t uInstance));
2992	/** @} */
2993
2994	/**
2995	* Read physical memory.
2996	*
2997	* @returns VINF_SUCCESS (for now).
2998	* @param pDevIns The device instance.
2999	* @param GCPhys Physical address start reading from.
3000	* @param pvBuf Where to put the read bits.
3001	* @param cbRead How many bytes to read.
3002	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3003	* @thread Any thread, but the call may involve the emulation thread.
3004	*/
3005	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3006
3007	/**
3008	* Write to physical memory.
3009	*
3010	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3011	* @param pDevIns The device instance.
3012	* @param GCPhys Physical address to write to.
3013	* @param pvBuf What to write.
3014	* @param cbWrite How many bytes to write.
3015	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3016	* @thread Any thread, but the call may involve the emulation thread.
3017	*/
3018	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3019
3020	/**
3021	* Requests the mapping of a guest page into ring-3.
3022	*
3023	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3024	* release it.
3025	*
3026	* This API will assume your intention is to write to the page, and will
3027	* therefore replace shared and zero pages. If you do not intend to modify the
3028	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3029	*
3030	* @returns VBox status code.
3031	* @retval VINF_SUCCESS on success.
3032	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3033	* backing or if the page has any active access handlers. The caller
3034	* must fall back on using PGMR3PhysWriteExternal.
3035	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3036	*
3037	* @param pDevIns The device instance.
3038	* @param GCPhys The guest physical address of the page that
3039	* should be mapped.
3040	* @param fFlags Flags reserved for future use, MBZ.
3041	* @param ppv Where to store the address corresponding to
3042	* GCPhys.
3043	* @param pLock Where to store the lock information that
3044	* pfnPhysReleasePageMappingLock needs.
3045	*
3046	* @remark Avoid calling this API from within critical sections (other than the
3047	* PGM one) because of the deadlock risk when we have to delegating the
3048	* task to an EMT.
3049	* @thread Any.
3050	*/
3051	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3052	PPGMPAGEMAPLOCK pLock));
3053
3054	/**
3055	* Requests the mapping of a guest page into ring-3, external threads.
3056	*
3057	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3058	* release it.
3059	*
3060	* @returns VBox status code.
3061	* @retval VINF_SUCCESS on success.
3062	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3063	* backing or if the page as an active ALL access handler. The caller
3064	* must fall back on using PGMPhysRead.
3065	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3066	*
3067	* @param pDevIns The device instance.
3068	* @param GCPhys The guest physical address of the page that
3069	* should be mapped.
3070	* @param fFlags Flags reserved for future use, MBZ.
3071	* @param ppv Where to store the address corresponding to
3072	* GCPhys.
3073	* @param pLock Where to store the lock information that
3074	* pfnPhysReleasePageMappingLock needs.
3075	*
3076	* @remark Avoid calling this API from within critical sections.
3077	* @thread Any.
3078	*/
3079	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3080	void const **ppv, PPGMPAGEMAPLOCK pLock));
3081
3082	/**
3083	* Release the mapping of a guest page.
3084	*
3085	* This is the counter part of pfnPhysGCPhys2CCPtr and
3086	* pfnPhysGCPhys2CCPtrReadOnly.
3087	*
3088	* @param pDevIns The device instance.
3089	* @param pLock The lock structure initialized by the mapping
3090	* function.
3091	*/
3092	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3093
3094	/**
3095	* Read guest physical memory by virtual address.
3096	*
3097	* @param pDevIns The device instance.
3098	* @param pvDst Where to put the read bits.
3099	* @param GCVirtSrc Guest virtual address to start reading from.
3100	* @param cb How many bytes to read.
3101	* @thread The emulation thread.
3102	*/
3103	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3104
3105	/**
3106	* Write to guest physical memory by virtual address.
3107	*
3108	* @param pDevIns The device instance.
3109	* @param GCVirtDst Guest virtual address to write to.
3110	* @param pvSrc What to write.
3111	* @param cb How many bytes to write.
3112	* @thread The emulation thread.
3113	*/
3114	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3115
3116	/**
3117	* Convert a guest virtual address to a guest physical address.
3118	*
3119	* @returns VBox status code.
3120	* @param pDevIns The device instance.
3121	* @param GCPtr Guest virtual address.
3122	* @param pGCPhys Where to store the GC physical address
3123	* corresponding to GCPtr.
3124	* @thread The emulation thread.
3125	* @remark Careful with page boundaries.
3126	*/
3127	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3128
3129	/**
3130	* Allocate memory which is associated with current VM instance
3131	* and automatically freed on it's destruction.
3132	*
3133	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3134	* @param pDevIns The device instance.
3135	* @param cb Number of bytes to allocate.
3136	*/
3137	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3138
3139	/**
3140	* Allocate memory which is associated with current VM instance
3141	* and automatically freed on it's destruction. The memory is ZEROed.
3142	*
3143	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3144	* @param pDevIns The device instance.
3145	* @param cb Number of bytes to allocate.
3146	*/
3147	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3148
3149	/**
3150	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3151	*
3152	* @param pDevIns The device instance.
3153	* @param pv Pointer to the memory to free.
3154	*/
3155	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3156
3157	/**
3158	* Gets the VM state.
3159	*
3160	* @returns VM state.
3161	* @param pDevIns The device instance.
3162	* @thread Any thread (just keep in mind that it's volatile info).
3163	*/
3164	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3165
3166	/**
3167	* Checks if the VM was teleported and hasn't been fully resumed yet.
3168	*
3169	* @returns true / false.
3170	* @param pDevIns The device instance.
3171	* @thread Any thread.
3172	*/
3173	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3174
3175	/**
3176	* Set the VM error message
3177	*
3178	* @returns rc.
3179	* @param pDevIns The device instance.
3180	* @param rc VBox status code.
3181	* @param SRC_POS Use RT_SRC_POS.
3182	* @param pszFormat Error message format string.
3183	* @param va Error message arguments.
3184	*/
3185	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3186	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3187
3188	/**
3189	* Set the VM runtime error message
3190	*
3191	* @returns VBox status code.
3192	* @param pDevIns The device instance.
3193	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3194	* @param pszErrorId Error ID string.
3195	* @param pszFormat Error message format string.
3196	* @param va Error message arguments.
3197	*/
3198	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3199	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3200
3201	/**
3202	* Stops the VM and enters the debugger to look at the guest state.
3203	*
3204	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3205	* invoking this function directly.
3206	*
3207	* @returns VBox status code which must be passed up to the VMM.
3208	* @param pDevIns The device instance.
3209	* @param pszFile Filename of the assertion location.
3210	* @param iLine The linenumber of the assertion location.
3211	* @param pszFunction Function of the assertion location.
3212	* @param pszFormat Message. (optional)
3213	* @param args Message parameters.
3214	*/
3215	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3216	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3217
3218	/**
3219	* Register a info handler with DBGF.
3220	*
3221	* @returns VBox status code.
3222	* @param pDevIns The device instance.
3223	* @param pszName The identifier of the info.
3224	* @param pszDesc The description of the info and any arguments
3225	* the handler may take.
3226	* @param pfnHandler The handler function to be called to display the
3227	* info.
3228	*/
3229	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3230
3231	/**
3232	* Register a info handler with DBGF, argv style.
3233	*
3234	* @returns VBox status code.
3235	* @param pDevIns The device instance.
3236	* @param pszName The identifier of the info.
3237	* @param pszDesc The description of the info and any arguments
3238	* the handler may take.
3239	* @param pfnHandler The handler function to be called to display the
3240	* info.
3241	*/
3242	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3243
3244	/**
3245	* Registers a set of registers for a device.
3246	*
3247	* The @a pvUser argument of the getter and setter callbacks will be
3248	* @a pDevIns. The register names will be prefixed by the device name followed
3249	* immediately by the instance number.
3250	*
3251	* @returns VBox status code.
3252	* @param pDevIns The device instance.
3253	* @param paRegisters The register descriptors.
3254	*
3255	* @remarks The device critical section is NOT entered prior to working the
3256	* callbacks registered via this helper!
3257	*/
3258	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3259
3260	/**
3261	* Gets the trace buffer handle.
3262	*
3263	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3264	* really inteded for direct usage, thus no inline wrapper function.
3265	*
3266	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3267	* @param pDevIns The device instance.
3268	*/
3269	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3270
3271	/**
3272	* Registers a statistics sample.
3273	*
3274	* @param pDevIns Device instance of the DMA.
3275	* @param pvSample Pointer to the sample.
3276	* @param enmType Sample type. This indicates what pvSample is
3277	* pointing at.
3278	* @param pszName Sample name, unix path style. If this does not
3279	* start with a '/', the default prefix will be
3280	* prepended, otherwise it will be used as-is.
3281	* @param enmUnit Sample unit.
3282	* @param pszDesc Sample description.
3283	*/
3284	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3285
3286	/**
3287	* Same as pfnSTAMRegister except that the name is specified in a
3288	* RTStrPrintfV like fashion.
3289	*
3290	* @returns VBox status.
3291	* @param pDevIns Device instance of the DMA.
3292	* @param pvSample Pointer to the sample.
3293	* @param enmType Sample type. This indicates what pvSample is
3294	* pointing at.
3295	* @param enmVisibility Visibility type specifying whether unused
3296	* statistics should be visible or not.
3297	* @param enmUnit Sample unit.
3298	* @param pszDesc Sample description.
3299	* @param pszName Sample name format string, unix path style. If
3300	* this does not start with a '/', the default
3301	* prefix will be prepended, otherwise it will be
3302	* used as-is.
3303	* @param args Arguments to the format string.
3304	*/
3305	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3306	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3307	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3308
3309	/**
3310	* Registers a PCI device with the default PCI bus.
3311	*
3312	* If a PDM device has more than one PCI device, they must be registered in the
3313	* order of PDMDEVINSR3::apPciDevs.
3314	*
3315	* @returns VBox status code.
3316	* @param pDevIns The device instance.
3317	* @param pPciDev The PCI device structure.
3318	* This must be kept in the instance data.
3319	* The PCI configuration must be initialized before registration.
3320	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3321	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3322	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3323	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3324	* device number (0-31). This will be ignored if
3325	* the CFGM configuration contains a PCIDeviceNo
3326	* value.
3327	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3328	* function number (0-7). This will be ignored if
3329	* the CFGM configuration contains a PCIFunctionNo
3330	* value.
3331	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3332	* The pointer is saved, so don't free or changed.
3333	* @note The PCI device configuration is now implicit from the apPciDevs
3334	* index, meaning that the zero'th entry is the primary one and
3335	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3336	*/
3337	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3338	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3339
3340	/**
3341	* Initialize MSI or MSI-X emulation support for the given PCI device.
3342	*
3343	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3344	*
3345	* @returns VBox status code.
3346	* @param pDevIns The device instance.
3347	* @param pPciDev The PCI device. NULL is an alias for the first
3348	* one registered.
3349	* @param pMsiReg MSI emulation registration structure.
3350	*/
3351	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3352
3353	/**
3354	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3355	*
3356	* @returns VBox status code.
3357	* @param pDevIns The device instance.
3358	* @param pPciDev The PCI device structure. If NULL the default
3359	* PCI device for this device instance is used.
3360	* @param iRegion The region number.
3361	* @param cbRegion Size of the region.
3362	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3363	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3364	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3365	* @a fFlags, UINT64_MAX if no handle is passed
3366	* (old style).
3367	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3368	* handle is specified. The callback will be
3369	* invoked holding only the PDM lock. The device
3370	* lock will _not_ be taken (due to lock order).
3371	*/
3372	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3373	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3374	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3375
3376	/**
3377	* Register PCI configuration space read/write callbacks.
3378	*
3379	* @returns VBox status code.
3380	* @param pDevIns The device instance.
3381	* @param pPciDev The PCI device structure. If NULL the default
3382	* PCI device for this device instance is used.
3383	* @param pfnRead Pointer to the user defined PCI config read function.
3384	* to call default PCI config read function. Can be NULL.
3385	* @param pfnWrite Pointer to the user defined PCI config write function.
3386	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3387	* is NOT take because that is very likely be a lock order violation.
3388	* @thread EMT(0)
3389	* @note Only callable during VM creation.
3390	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3391	*/
3392	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3393	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3394
3395	/**
3396	* Perform a PCI configuration space write.
3397	*
3398	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3399	*
3400	* @returns Strict VBox status code (mainly DBGFSTOP).
3401	* @param pDevIns The device instance.
3402	* @param pPciDev The PCI device which config space is being read.
3403	* @param uAddress The config space address.
3404	* @param cb The size of the read: 1, 2 or 4 bytes.
3405	* @param u32Value The value to write.
3406	*/
3407	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3408	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3409
3410	/**
3411	* Perform a PCI configuration space read.
3412	*
3413	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3414	*
3415	* @returns Strict VBox status code (mainly DBGFSTOP).
3416	* @param pDevIns The device instance.
3417	* @param pPciDev The PCI device which config space is being read.
3418	* @param uAddress The config space address.
3419	* @param cb The size of the read: 1, 2 or 4 bytes.
3420	* @param pu32Value Where to return the value.
3421	*/
3422	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3423	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3424
3425	/**
3426	* Bus master physical memory read.
3427	*
3428	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3429	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3430	* @param pDevIns The device instance.
3431	* @param pPciDev The PCI device structure. If NULL the default
3432	* PCI device for this device instance is used.
3433	* @param GCPhys Physical address start reading from.
3434	* @param pvBuf Where to put the read bits.
3435	* @param cbRead How many bytes to read.
3436	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3437	* @thread Any thread, but the call may involve the emulation thread.
3438	*/
3439	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3440
3441	/**
3442	* Bus master physical memory write.
3443	*
3444	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3445	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3446	* @param pDevIns The device instance.
3447	* @param pPciDev The PCI device structure. If NULL the default
3448	* PCI device for this device instance is used.
3449	* @param GCPhys Physical address to write to.
3450	* @param pvBuf What to write.
3451	* @param cbWrite How many bytes to write.
3452	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3453	* @thread Any thread, but the call may involve the emulation thread.
3454	*/
3455	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3456
3457	/**
3458	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3459	* physical memory write operation.
3460	*
3461	* Refer pfnPhysGCPhys2CCPtr() for further details.
3462	*
3463	* @returns VBox status code.
3464	* @param pDevIns The device instance.
3465	* @param pPciDev The PCI device structure. If NULL the default
3466	* PCI device for this device instance is used.
3467	* @param GCPhys The guest physical address of the page that should be
3468	* mapped.
3469	* @param fFlags Flags reserved for future use, MBZ.
3470	* @param ppv Where to store the address corresponding to GCPhys.
3471	* @param pLock Where to store the lock information that
3472	* pfnPhysReleasePageMappingLock needs.
3473	*
3474	* @remarks Avoid calling this API from within critical sections (other than the PGM
3475	* one) because of the deadlock risk when we have to delegating the task to
3476	* an EMT.
3477	* @thread Any.
3478	*/
3479	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3480	void **ppv, PPGMPAGEMAPLOCK pLock));
3481
3482	/**
3483	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3484	* for a bus master physical memory read operation.
3485	*
3486	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3487	*
3488	* @returns VBox status code.
3489	* @param pDevIns The device instance.
3490	* @param pPciDev The PCI device structure. If NULL the default
3491	* PCI device for this device instance is used.
3492	* @param GCPhys The guest physical address of the page that
3493	* should be mapped.
3494	* @param fFlags Flags reserved for future use, MBZ.
3495	* @param ppv Where to store the address corresponding to
3496	* GCPhys.
3497	* @param pLock Where to store the lock information that
3498	* pfnPhysReleasePageMappingLock needs.
3499	*
3500	* @remarks Avoid calling this API from within critical sections.
3501	* @thread Any.
3502	*/
3503	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3504	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3505
3506	/**
3507	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3508	* master physical memory write operation.
3509	*
3510	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3511	* ASAP to release them.
3512	*
3513	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3514	*
3515	* @returns VBox status code.
3516	* @param pDevIns The device instance.
3517	* @param pPciDev The PCI device structure. If NULL the default
3518	* PCI device for this device instance is used.
3519	* @param cPages Number of pages to lock.
3520	* @param paGCPhysPages The guest physical address of the pages that
3521	* should be mapped (@a cPages entries).
3522	* @param fFlags Flags reserved for future use, MBZ.
3523	* @param papvPages Where to store the ring-3 mapping addresses
3524	* corresponding to @a paGCPhysPages.
3525	* @param paLocks Where to store the locking information that
3526	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3527	* in length).
3528	*/
3529	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3530	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3531	PPGMPAGEMAPLOCK paLocks));
3532
3533	/**
3534	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3535	* master physical memory read operation.
3536	*
3537	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3538	* ASAP to release them.
3539	*
3540	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3541	*
3542	* @returns VBox status code.
3543	* @param pDevIns The device instance.
3544	* @param pPciDev The PCI device structure. If NULL the default
3545	* PCI device for this device instance is used.
3546	* @param cPages Number of pages to lock.
3547	* @param paGCPhysPages The guest physical address of the pages that
3548	* should be mapped (@a cPages entries).
3549	* @param fFlags Flags reserved for future use, MBZ.
3550	* @param papvPages Where to store the ring-3 mapping addresses
3551	* corresponding to @a paGCPhysPages.
3552	* @param paLocks Where to store the lock information that
3553	* pfnPhysReleasePageMappingLock needs (@a cPages
3554	* in length).
3555	*/
3556	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3557	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3558	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3559
3560	/**
3561	* Sets the IRQ for the given PCI device.
3562	*
3563	* @param pDevIns The device instance.
3564	* @param pPciDev The PCI device structure. If NULL the default
3565	* PCI device for this device instance is used.
3566	* @param iIrq IRQ number to set.
3567	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3568	* @thread Any thread, but will involve the emulation thread.
3569	*/
3570	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3571
3572	/**
3573	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3574	* the request when not called from EMT.
3575	*
3576	* @param pDevIns The device instance.
3577	* @param pPciDev The PCI device structure. If NULL the default
3578	* PCI device for this device instance is used.
3579	* @param iIrq IRQ number to set.
3580	* @param iLevel IRQ level.
3581	* @thread Any thread, but will involve the emulation thread.
3582	*/
3583	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3584
3585	/**
3586	* Set ISA IRQ for a device.
3587	*
3588	* @param pDevIns The device instance.
3589	* @param iIrq IRQ number to set.
3590	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3591	* @thread Any thread, but will involve the emulation thread.
3592	*/
3593	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3594
3595	/**
3596	* Set the ISA IRQ for a device, but don't wait for EMT to process
3597	* the request when not called from EMT.
3598	*
3599	* @param pDevIns The device instance.
3600	* @param iIrq IRQ number to set.
3601	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3602	* @thread Any thread, but will involve the emulation thread.
3603	*/
3604	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3605
3606	/**
3607	* Attaches a driver (chain) to the device.
3608	*
3609	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3610	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3611	*
3612	* @returns VBox status code.
3613	* @param pDevIns The device instance.
3614	* @param iLun The logical unit to attach.
3615	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3616	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3617	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3618	* for the live of the device instance.
3619	*/
3620	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3621	PPDMIBASE ppBaseInterface, const char pszDesc));
3622
3623	/**
3624	* Detaches an attached driver (chain) from the device again.
3625	*
3626	* @returns VBox status code.
3627	* @param pDevIns The device instance.
3628	* @param pDrvIns The driver instance to detach.
3629	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3630	*/
3631	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3632
3633	/**
3634	* Reconfigures the driver chain for a LUN, detaching any driver currently
3635	* present there.
3636	*
3637	* Caller will have attach it, of course.
3638	*
3639	* @returns VBox status code.
3640	* @param pDevIns The device instance.
3641	* @param iLun The logical unit to reconfigure.
3642	* @param cDepth The depth of the driver chain. Determins the
3643	* size of @a papszDrivers and @a papConfigs.
3644	* @param papszDrivers The names of the drivers to configure in the
3645	* chain, first entry is the one immediately
3646	* below the device/LUN
3647	* @param papConfigs The configurations for each of the drivers
3648	* in @a papszDrivers array. NULL entries
3649	* corresponds to empty 'Config' nodes. This
3650	* function will take ownership of non-NULL
3651	* CFGM sub-trees and set the array member to
3652	* NULL, so the caller can do cleanups on
3653	* failure. This parameter is optional.
3654	* @param fFlags Reserved, MBZ.
3655	*/
3656	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3657	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3658
3659	/** @name Exported PDM Queue Functions
3660	* @{ */
3661	/**
3662	* Create a queue.
3663	*
3664	* @returns VBox status code.
3665	* @param pDevIns The device instance.
3666	* @param cbItem The size of a queue item.
3667	* @param cItems The number of items in the queue.
3668	* @param cMilliesInterval The number of milliseconds between polling the queue.
3669	* If 0 then the emulation thread will be notified whenever an item arrives.
3670	* @param pfnCallback The consumer function.
3671	* @param fRZEnabled Set if the queue should work in RC and R0.
3672	* @param pszName The queue base name. The instance number will be
3673	* appended automatically.
3674	* @param ppQueue Where to store the queue pointer on success.
3675	* @thread The emulation thread.
3676	* @remarks The device critical section will NOT be entered before calling the
3677	* callback. No locks will be held, but for now it's safe to assume
3678	* that only one EMT will do queue callbacks at any one time.
3679	*/
3680	DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3681	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3682	PPDMQUEUE *ppQueue));
3683
3684	/**
3685	* Create a queue.
3686	*
3687	* @returns VBox status code.
3688	* @param pDevIns The device instance.
3689	* @param cbItem The size of a queue item.
3690	* @param cItems The number of items in the queue.
3691	* @param cMilliesInterval The number of milliseconds between polling the queue.
3692	* If 0 then the emulation thread will be notified whenever an item arrives.
3693	* @param pfnCallback The consumer function.
3694	* @param fRZEnabled Set if the queue should work in RC and R0.
3695	* @param pszName The queue base name. The instance number will be
3696	* appended automatically.
3697	* @param phQueue Where to store the queue handle on success.
3698	* @thread EMT(0)
3699	* @remarks The device critical section will NOT be entered before calling the
3700	* callback. No locks will be held, but for now it's safe to assume
3701	* that only one EMT will do queue callbacks at any one time.
3702	*/
3703	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3704	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3705	PDMQUEUEHANDLE *phQueue));
3706
3707	DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3708	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3709	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3710	DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3711	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3712	/** @} */
3713
3714	/** @name PDM Task
3715	* @{ */
3716	/**
3717	* Create an asynchronous ring-3 task.
3718	*
3719	* @returns VBox status code.
3720	* @param pDevIns The device instance.
3721	* @param fFlags PDMTASK_F_XXX
3722	* @param pszName The function name or similar. Used for statistics,
3723	* so no slashes.
3724	* @param pfnCallback The task function.
3725	* @param pvUser User argument for the task function.
3726	* @param phTask Where to return the task handle.
3727	* @thread EMT(0)
3728	*/
3729	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3730	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3731	/**
3732	* Triggers the running the given task.
3733	*
3734	* @returns VBox status code.
3735	* @retval VINF_ALREADY_POSTED is the task is already pending.
3736	* @param pDevIns The device instance.
3737	* @param hTask The task to trigger.
3738	* @thread Any thread.
3739	*/
3740	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3741	/** @} */
3742
3743	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3744	* These semaphores can be signalled from ring-0.
3745	* @{ */
3746	/** @sa SUPSemEventCreate */
3747	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3748	/** @sa SUPSemEventClose */
3749	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3750	/** @sa SUPSemEventSignal */
3751	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3752	/** @sa SUPSemEventWaitNoResume */
3753	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3754	/** @sa SUPSemEventWaitNsAbsIntr */
3755	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3756	/** @sa SUPSemEventWaitNsRelIntr */
3757	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3758	/** @sa SUPSemEventGetResolution */
3759	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3760	/** @} */
3761
3762	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3763	* These semaphores can be signalled from ring-0.
3764	* @{ */
3765	/** @sa SUPSemEventMultiCreate */
3766	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3767	/** @sa SUPSemEventMultiClose */
3768	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3769	/** @sa SUPSemEventMultiSignal */
3770	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3771	/** @sa SUPSemEventMultiReset */
3772	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3773	/** @sa SUPSemEventMultiWaitNoResume */
3774	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3775	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3776	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3777	/** @sa SUPSemEventMultiWaitNsRelIntr */
3778	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3779	/** @sa SUPSemEventMultiGetResolution */
3780	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3781	/** @} */
3782
3783	/**
3784	* Initializes a PDM critical section.
3785	*
3786	* The PDM critical sections are derived from the IPRT critical sections, but
3787	* works in RC and R0 as well.
3788	*
3789	* @returns VBox status code.
3790	* @param pDevIns The device instance.
3791	* @param pCritSect Pointer to the critical section.
3792	* @param SRC_POS Use RT_SRC_POS.
3793	* @param pszNameFmt Format string for naming the critical section.
3794	* For statistics and lock validation.
3795	* @param va Arguments for the format string.
3796	*/
3797	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3798	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3799
3800	/**
3801	* Gets the NOP critical section.
3802	*
3803	* @returns The ring-3 address of the NOP critical section.
3804	* @param pDevIns The device instance.
3805	*/
3806	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3807
3808	/**
3809	* Gets the NOP critical section.
3810	*
3811	* @returns The ring-0 address of the NOP critical section.
3812	* @param pDevIns The device instance.
3813	* @deprecated
3814	*/
3815	DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3816
3817	/**
3818	* Gets the NOP critical section.
3819	*
3820	* @returns The raw-mode context address of the NOP critical section.
3821	* @param pDevIns The device instance.
3822	* @deprecated
3823	*/
3824	DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3825
3826	/**
3827	* Changes the device level critical section from the automatically created
3828	* default to one desired by the device constructor.
3829	*
3830	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3831	* the additional contexts.
3832	*
3833	* @returns VBox status code.
3834	* @param pDevIns The device instance.
3835	* @param pCritSect The critical section to use. NULL is not
3836	* valid, instead use the NOP critical
3837	* section.
3838	*/
3839	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3840
3841	/** @name Exported PDM Critical Section Functions
3842	* @{ */
3843	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3844	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3845	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3846	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3847	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3848	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3849	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3850	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3851	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3852	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3853	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3854	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3855	/** @} */
3856
3857	/** @name Exported PDM Read/Write Critical Section Functions
3858	* @{ */
3859	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
3860	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3861	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3862
3863	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3864	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3865	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3866	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3867	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3868
3869	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
3870	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3871	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3872	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3873	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3874
3875	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3876	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
3877	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3878	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3879	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3880	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
3881	/** @} */
3882
3883	/**
3884	* Creates a PDM thread.
3885	*
3886	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3887	* resuming, and destroying the thread as the VM state changes.
3888	*
3889	* @returns VBox status code.
3890	* @param pDevIns The device instance.
3891	* @param ppThread Where to store the thread 'handle'.
3892	* @param pvUser The user argument to the thread function.
3893	* @param pfnThread The thread function.
3894	* @param pfnWakeup The wakup callback. This is called on the EMT
3895	* thread when a state change is pending.
3896	* @param cbStack See RTThreadCreate.
3897	* @param enmType See RTThreadCreate.
3898	* @param pszName See RTThreadCreate.
3899	* @remarks The device critical section will NOT be entered prior to invoking
3900	* the function pointers.
3901	*/
3902	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3903	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3904
3905	/** @name Exported PDM Thread Functions
3906	* @{ */
3907	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3908	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3909	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3910	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3911	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3912	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3913	/** @} */
3914
3915	/**
3916	* Set up asynchronous handling of a suspend, reset or power off notification.
3917	*
3918	* This shall only be called when getting the notification. It must be called
3919	* for each one.
3920	*
3921	* @returns VBox status code.
3922	* @param pDevIns The device instance.
3923	* @param pfnAsyncNotify The callback.
3924	* @thread EMT(0)
3925	* @remarks The caller will enter the device critical section prior to invoking
3926	* the callback.
3927	*/
3928	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3929
3930	/**
3931	* Notify EMT(0) that the device has completed the asynchronous notification
3932	* handling.
3933	*
3934	* This can be called at any time, spurious calls will simply be ignored.
3935	*
3936	* @param pDevIns The device instance.
3937	* @thread Any
3938	*/
3939	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3940
3941	/**
3942	* Register the RTC device.
3943	*
3944	* @returns VBox status code.
3945	* @param pDevIns The device instance.
3946	* @param pRtcReg Pointer to a RTC registration structure.
3947	* @param ppRtcHlp Where to store the pointer to the helper
3948	* functions.
3949	*/
3950	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3951
3952	/**
3953	* Register a PCI Bus.
3954	*
3955	* @returns VBox status code, but the positive values 0..31 are used to indicate
3956	* bus number rather than informational status codes.
3957	* @param pDevIns The device instance.
3958	* @param pPciBusReg Pointer to PCI bus registration structure.
3959	* @param ppPciHlp Where to store the pointer to the PCI Bus
3960	* helpers.
3961	* @param piBus Where to return the PDM bus number. Optional.
3962	*/
3963	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3964	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
3965
3966	/**
3967	* Register the IOMMU device.
3968	*
3969	* @returns VBox status code.
3970	* @param pDevIns The device instance.
3971	* @param pIommuReg Pointer to a IOMMU registration structure.
3972	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3973	* helpers.
3974	* @param pidxIommu Where to return the IOMMU index. Optional.
3975	*/
3976	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3977	uint32_t *pidxIommu));
3978
3979	/**
3980	* Register the PIC device.
3981	*
3982	* @returns VBox status code.
3983	* @param pDevIns The device instance.
3984	* @param pPicReg Pointer to a PIC registration structure.
3985	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
3986	* helpers.
3987	* @sa PDMDevHlpPICSetUpContext
3988	*/
3989	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3990
3991	/**
3992	* Register the APIC device.
3993	*
3994	* @returns VBox status code.
3995	* @param pDevIns The device instance.
3996	*/
3997	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3998
3999	/**
4000	* Register the I/O APIC device.
4001	*
4002	* @returns VBox status code.
4003	* @param pDevIns The device instance.
4004	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4005	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4006	* helpers.
4007	*/
4008	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4009
4010	/**
4011	* Register the HPET device.
4012	*
4013	* @returns VBox status code.
4014	* @param pDevIns The device instance.
4015	* @param pHpetReg Pointer to a HPET registration structure.
4016	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4017	* helpers.
4018	*/
4019	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4020
4021	/**
4022	* Register a raw PCI device.
4023	*
4024	* @returns VBox status code.
4025	* @param pDevIns The device instance.
4026	* @param pPciRawReg Pointer to a raw PCI registration structure.
4027	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4028	* device helpers.
4029	*/
4030	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4031
4032	/**
4033	* Register the DMA device.
4034	*
4035	* @returns VBox status code.
4036	* @param pDevIns The device instance.
4037	* @param pDmacReg Pointer to a DMAC registration structure.
4038	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4039	*/
4040	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4041
4042	/**
4043	* Register transfer function for DMA channel.
4044	*
4045	* @returns VBox status code.
4046	* @param pDevIns The device instance.
4047	* @param uChannel Channel number.
4048	* @param pfnTransferHandler Device specific transfer callback function.
4049	* @param pvUser User pointer to pass to the callback.
4050	* @thread EMT
4051	*/
4052	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4053
4054	/**
4055	* Read memory.
4056	*
4057	* @returns VBox status code.
4058	* @param pDevIns The device instance.
4059	* @param uChannel Channel number.
4060	* @param pvBuffer Pointer to target buffer.
4061	* @param off DMA position.
4062	* @param cbBlock Block size.
4063	* @param pcbRead Where to store the number of bytes which was
4064	* read. optional.
4065	* @thread EMT
4066	*/
4067	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4068
4069	/**
4070	* Write memory.
4071	*
4072	* @returns VBox status code.
4073	* @param pDevIns The device instance.
4074	* @param uChannel Channel number.
4075	* @param pvBuffer Memory to write.
4076	* @param off DMA position.
4077	* @param cbBlock Block size.
4078	* @param pcbWritten Where to store the number of bytes which was
4079	* written. optional.
4080	* @thread EMT
4081	*/
4082	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4083
4084	/**
4085	* Set the DREQ line.
4086	*
4087	* @returns VBox status code.
4088	* @param pDevIns Device instance.
4089	* @param uChannel Channel number.
4090	* @param uLevel Level of the line.
4091	* @thread EMT
4092	*/
4093	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4094
4095	/**
4096	* Get channel mode.
4097	*
4098	* @returns Channel mode. See specs.
4099	* @param pDevIns The device instance.
4100	* @param uChannel Channel number.
4101	* @thread EMT
4102	*/
4103	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4104
4105	/**
4106	* Schedule DMA execution.
4107	*
4108	* @param pDevIns The device instance.
4109	* @thread Any thread.
4110	*/
4111	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4112
4113	/**
4114	* Write CMOS value and update the checksum(s).
4115	*
4116	* @returns VBox status code.
4117	* @param pDevIns The device instance.
4118	* @param iReg The CMOS register index.
4119	* @param u8Value The CMOS register value.
4120	* @thread EMT
4121	*/
4122	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4123
4124	/**
4125	* Read CMOS value.
4126	*
4127	* @returns VBox status code.
4128	* @param pDevIns The device instance.
4129	* @param iReg The CMOS register index.
4130	* @param pu8Value Where to store the CMOS register value.
4131	* @thread EMT
4132	*/
4133	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4134
4135	/**
4136	* Assert that the current thread is the emulation thread.
4137	*
4138	* @returns True if correct.
4139	* @returns False if wrong.
4140	* @param pDevIns The device instance.
4141	* @param pszFile Filename of the assertion location.
4142	* @param iLine The linenumber of the assertion location.
4143	* @param pszFunction Function of the assertion location.
4144	*/
4145	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4146
4147	/**
4148	* Assert that the current thread is NOT the emulation thread.
4149	*
4150	* @returns True if correct.
4151	* @returns False if wrong.
4152	* @param pDevIns The device instance.
4153	* @param pszFile Filename of the assertion location.
4154	* @param iLine The linenumber of the assertion location.
4155	* @param pszFunction Function of the assertion location.
4156	*/
4157	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4158
4159	/**
4160	* Resolves the symbol for a raw-mode context interface.
4161	*
4162	* @returns VBox status code.
4163	* @param pDevIns The device instance.
4164	* @param pvInterface The interface structure.
4165	* @param cbInterface The size of the interface structure.
4166	* @param pszSymPrefix What to prefix the symbols in the list with
4167	* before resolving them. This must start with
4168	* 'dev' and contain the driver name.
4169	* @param pszSymList List of symbols corresponding to the interface.
4170	* There is generally a there is generally a define
4171	* holding this list associated with the interface
4172	* definition (INTERFACE_SYM_LIST). For more
4173	* details see PDMR3LdrGetInterfaceSymbols.
4174	* @thread EMT
4175	*/
4176	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4177	const char pszSymPrefix, const char pszSymList));
4178
4179	/**
4180	* Resolves the symbol for a ring-0 context interface.
4181	*
4182	* @returns VBox status code.
4183	* @param pDevIns The device instance.
4184	* @param pvInterface The interface structure.
4185	* @param cbInterface The size of the interface structure.
4186	* @param pszSymPrefix What to prefix the symbols in the list with
4187	* before resolving them. This must start with
4188	* 'dev' and contain the driver name.
4189	* @param pszSymList List of symbols corresponding to the interface.
4190	* There is generally a there is generally a define
4191	* holding this list associated with the interface
4192	* definition (INTERFACE_SYM_LIST). For more
4193	* details see PDMR3LdrGetInterfaceSymbols.
4194	* @thread EMT
4195	*/
4196	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4197	const char pszSymPrefix, const char pszSymList));
4198
4199	/**
4200	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4201	*
4202	* @returns VBox status code.
4203	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4204	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4205	*
4206	* @param pDevIns The device instance.
4207	* @param uOperation The operation to perform.
4208	* @param u64Arg 64-bit integer argument.
4209	* @thread EMT
4210	*/
4211	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4212
4213	/**
4214	* Gets the reason for the most recent VM suspend.
4215	*
4216	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4217	* suspend has been made or if the pDevIns is invalid.
4218	* @param pDevIns The device instance.
4219	*/
4220	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4221
4222	/**
4223	* Gets the reason for the most recent VM resume.
4224	*
4225	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4226	* resume has been made or if the pDevIns is invalid.
4227	* @param pDevIns The device instance.
4228	*/
4229	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4230
4231	/**
4232	* Requests the mapping of multiple guest page into ring-3.
4233	*
4234	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4235	* ASAP to release them.
4236	*
4237	* This API will assume your intention is to write to the pages, and will
4238	* therefore replace shared and zero pages. If you do not intend to modify the
4239	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4240	*
4241	* @returns VBox status code.
4242	* @retval VINF_SUCCESS on success.
4243	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4244	* backing or if any of the pages the page has any active access
4245	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4246	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4247	* an invalid physical address.
4248	*
4249	* @param pDevIns The device instance.
4250	* @param cPages Number of pages to lock.
4251	* @param paGCPhysPages The guest physical address of the pages that
4252	* should be mapped (@a cPages entries).
4253	* @param fFlags Flags reserved for future use, MBZ.
4254	* @param papvPages Where to store the ring-3 mapping addresses
4255	* corresponding to @a paGCPhysPages.
4256	* @param paLocks Where to store the locking information that
4257	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4258	* in length).
4259	*
4260	* @remark Avoid calling this API from within critical sections (other than the
4261	* PGM one) because of the deadlock risk when we have to delegating the
4262	* task to an EMT.
4263	* @thread Any.
4264	* @since 6.0.6
4265	*/
4266	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4267	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4268
4269	/**
4270	* Requests the mapping of multiple guest page into ring-3, for reading only.
4271	*
4272	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4273	* ASAP to release them.
4274	*
4275	* @returns VBox status code.
4276	* @retval VINF_SUCCESS on success.
4277	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4278	* backing or if any of the pages the page has an active ALL access
4279	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4280	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4281	* an invalid physical address.
4282	*
4283	* @param pDevIns The device instance.
4284	* @param cPages Number of pages to lock.
4285	* @param paGCPhysPages The guest physical address of the pages that
4286	* should be mapped (@a cPages entries).
4287	* @param fFlags Flags reserved for future use, MBZ.
4288	* @param papvPages Where to store the ring-3 mapping addresses
4289	* corresponding to @a paGCPhysPages.
4290	* @param paLocks Where to store the lock information that
4291	* pfnPhysReleasePageMappingLock needs (@a cPages
4292	* in length).
4293	*
4294	* @remark Avoid calling this API from within critical sections.
4295	* @thread Any.
4296	* @since 6.0.6
4297	*/
4298	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4299	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4300
4301	/**
4302	* Release the mappings of multiple guest pages.
4303	*
4304	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4305	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4306	*
4307	* @param pDevIns The device instance.
4308	* @param cPages Number of pages to unlock.
4309	* @param paLocks The lock structures initialized by the mapping
4310	* function (@a cPages in length).
4311	* @thread Any.
4312	* @since 6.0.6
4313	*/
4314	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4315
4316	/**
4317	* Returns the micro architecture used for the guest.
4318	*
4319	* @returns CPU micro architecture enum.
4320	* @param pDevIns The device instance.
4321	*/
4322	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4323
4324	/**
4325	* Get the number of physical and linear address bits supported by the guest.
4326	*
4327	* @param pDevIns The device instance.
4328	* @param pcPhysAddrWidth Where to store the number of physical address bits
4329	* supported by the guest.
4330	* @param pcLinearAddrWidth Where to store the number of linear address bits
4331	* supported by the guest.
4332	*/
4333	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4334	uint8_t *pcLinearAddrWidth));
4335
4336	/** Space reserved for future members.
4337	* @{ */
4338	/**
4339	* Deregister zero or more samples given their name prefix.
4340	*
4341	* @returns VBox status code.
4342	* @param pDevIns The device instance.
4343	* @param pszPrefix The name prefix of the samples to remove. If this does
4344	* not start with a '/', the default prefix will be
4345	* prepended, otherwise it will be used as-is.
4346	*/
4347	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4348	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4349	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4350	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4351	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4352	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4353	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4354	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4355	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4356	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4357	/** @} */
4358
4359
4360	/** API available to trusted devices only.
4361	*
4362	* These APIs are providing unrestricted access to the guest and the VM,
4363	* or they are interacting intimately with PDM.
4364	*
4365	* @{
4366	*/
4367
4368	/**
4369	* Gets the user mode VM handle. Restricted API.
4370	*
4371	* @returns User mode VM Handle.
4372	* @param pDevIns The device instance.
4373	*/
4374	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4375
4376	/**
4377	* Gets the global VM handle. Restricted API.
4378	*
4379	* @returns VM Handle.
4380	* @param pDevIns The device instance.
4381	*/
4382	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4383
4384	/**
4385	* Gets the VMCPU handle. Restricted API.
4386	*
4387	* @returns VMCPU Handle.
4388	* @param pDevIns The device instance.
4389	*/
4390	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4391
4392	/**
4393	* The the VM CPU ID of the current thread (restricted API).
4394	*
4395	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4396	* @param pDevIns The device instance.
4397	*/
4398	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4399
4400	/**
4401	* Registers the VMM device heap or notifies about mapping/unmapping.
4402	*
4403	* This interface serves three purposes:
4404	*
4405	* -# Register the VMM device heap during device construction
4406	* for the HM to use.
4407	* -# Notify PDM/HM that it's mapped into guest address
4408	* space (i.e. usable).
4409	* -# Notify PDM/HM that it is being unmapped from the guest
4410	* address space (i.e. not usable).
4411	*
4412	* @returns VBox status code.
4413	* @param pDevIns The device instance.
4414	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4415	* not mapped.
4416	* @param pvHeap Ring 3 heap pointer.
4417	* @param cbHeap Size of the heap.
4418	* @thread EMT.
4419	*/
4420	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4421
4422	/**
4423	* Registers the firmware (BIOS, EFI) device with PDM.
4424	*
4425	* The firmware provides a callback table and gets a special PDM helper table.
4426	* There can only be one firmware device for a VM.
4427	*
4428	* @returns VBox status code.
4429	* @param pDevIns The device instance.
4430	* @param pFwReg Firmware registration structure.
4431	* @param ppFwHlp Where to return the firmware helper structure.
4432	* @remarks Only valid during device construction.
4433	* @thread EMT(0)
4434	*/
4435	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4436
4437	/**
4438	* Resets the VM.
4439	*
4440	* @returns The appropriate VBox status code to pass around on reset.
4441	* @param pDevIns The device instance.
4442	* @param fFlags PDMVMRESET_F_XXX flags.
4443	* @thread The emulation thread.
4444	*/
4445	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4446
4447	/**
4448	* Suspends the VM.
4449	*
4450	* @returns The appropriate VBox status code to pass around on suspend.
4451	* @param pDevIns The device instance.
4452	* @thread The emulation thread.
4453	*/
4454	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4455
4456	/**
4457	* Suspends, saves and powers off the VM.
4458	*
4459	* @returns The appropriate VBox status code to pass around.
4460	* @param pDevIns The device instance.
4461	* @thread An emulation thread.
4462	*/
4463	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4464
4465	/**
4466	* Power off the VM.
4467	*
4468	* @returns The appropriate VBox status code to pass around on power off.
4469	* @param pDevIns The device instance.
4470	* @thread The emulation thread.
4471	*/
4472	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4473
4474	/**
4475	* Checks if the Gate A20 is enabled or not.
4476	*
4477	* @returns true if A20 is enabled.
4478	* @returns false if A20 is disabled.
4479	* @param pDevIns The device instance.
4480	* @thread The emulation thread.
4481	*/
4482	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4483
4484	/**
4485	* Enables or disables the Gate A20.
4486	*
4487	* @param pDevIns The device instance.
4488	* @param fEnable Set this flag to enable the Gate A20; clear it
4489	* to disable.
4490	* @thread The emulation thread.
4491	*/
4492	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4493
4494	/**
4495	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4496	* thread.
4497	*
4498	* @param pDevIns The device instance.
4499	* @param iLeaf The CPUID leaf to get.
4500	* @param pEax Where to store the EAX value.
4501	* @param pEbx Where to store the EBX value.
4502	* @param pEcx Where to store the ECX value.
4503	* @param pEdx Where to store the EDX value.
4504	* @thread EMT.
4505	*/
4506	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4507
4508	/**
4509	* Get the current virtual clock time in a VM. The clock frequency must be
4510	* queried separately.
4511	*
4512	* @returns Current clock time.
4513	* @param pDevIns The device instance.
4514	*/
4515	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4516
4517	/**
4518	* Get the frequency of the virtual clock.
4519	*
4520	* @returns The clock frequency (not variable at run-time).
4521	* @param pDevIns The device instance.
4522	*/
4523	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4524
4525	/**
4526	* Get the current virtual clock time in a VM, in nanoseconds.
4527	*
4528	* @returns Current clock time (in ns).
4529	* @param pDevIns The device instance.
4530	*/
4531	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4532
4533	/**
4534	* Gets the support driver session.
4535	*
4536	* This is intended for working with the semaphore API.
4537	*
4538	* @returns Support driver session handle.
4539	* @param pDevIns The device instance.
4540	*/
4541	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4542
4543	/**
4544	* Queries a generic object from the VMM user.
4545	*
4546	* @returns Pointer to the object if found, NULL if not.
4547	* @param pDevIns The device instance.
4548	* @param pUuid The UUID of what's being queried. The UUIDs and
4549	* the usage conventions are defined by the user.
4550	*
4551	* @note It is strictly forbidden to call this internally in VBox! This
4552	* interface is exclusively for hacks in externally developed devices.
4553	*/
4554	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4555
4556	/**
4557	* Register a physical page access handler type.
4558	*
4559	* @returns VBox status code.
4560	* @param pDevIns The device instance.
4561	* @param enmKind The kind of access handler.
4562	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4563	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4564	* handler should be called.
4565	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4566	* ring-3 handler should be called.
4567	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4568	* the ring-3 handler should be called.
4569	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4570	* if the ring-3 handler should be called.
4571	* @param pszDesc The type description.
4572	* @param phType Where to return the type handle (cross context
4573	* safe).
4574	*/
4575	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4576	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4577	const char pszHandlerR0, const char pszPfHandlerR0,
4578	const char pszHandlerRC, const char pszPfHandlerRC,
4579	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4580
4581	/** @} */
4582
4583	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4584	uint32_t u32TheEnd;
4585	} PDMDEVHLPR3;
4586	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4587	/** Pointer to the R3 PDM Device API. */
4588	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4589	/** Pointer to the R3 PDM Device API, const variant. */
4590	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4591
4592
4593	/**
4594	* PDM Device API - RC Variant.
4595	*/
4596	typedef struct PDMDEVHLPRC
4597	{
4598	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4599	uint32_t u32Version;
4600
4601	/**
4602	* Sets up raw-mode context callback handlers for an I/O port range.
4603	*
4604	* The range must have been registered in ring-3 first using
4605	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4606	*
4607	* @returns VBox status.
4608	* @param pDevIns The device instance to register the ports with.
4609	* @param hIoPorts The I/O port range handle.
4610	* @param pfnOut Pointer to function which is gonna handle OUT
4611	* operations. Optional.
4612	* @param pfnIn Pointer to function which is gonna handle IN operations.
4613	* Optional.
4614	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4615	* operations. Optional.
4616	* @param pfnInStr Pointer to function which is gonna handle string IN
4617	* operations. Optional.
4618	* @param pvUser User argument to pass to the callbacks.
4619	*
4620	* @remarks Caller enters the device critical section prior to invoking the
4621	* registered callback methods.
4622	*
4623	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4624	* PDMDevHlpIoPortUnmap.
4625	*/
4626	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4627	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4628	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4629	void *pvUser));
4630
4631	/**
4632	* Sets up raw-mode context callback handlers for an MMIO region.
4633	*
4634	* The region must have been registered in ring-3 first using
4635	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4636	*
4637	* @returns VBox status.
4638	* @param pDevIns The device instance to register the ports with.
4639	* @param hRegion The MMIO region handle.
4640	* @param pfnWrite Pointer to function which is gonna handle Write
4641	* operations.
4642	* @param pfnRead Pointer to function which is gonna handle Read
4643	* operations.
4644	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4645	* operations. (optional)
4646	* @param pvUser User argument to pass to the callbacks.
4647	*
4648	* @remarks Caller enters the device critical section prior to invoking the
4649	* registered callback methods.
4650	*
4651	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4652	* PDMDevHlpMmioUnmap.
4653	*/
4654	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4655	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4656
4657	/**
4658	* Sets up a raw-mode mapping for an MMIO2 region.
4659	*
4660	* The region must have been created in ring-3 first using
4661	* PDMDevHlpMmio2Create().
4662	*
4663	* @returns VBox status.
4664	* @param pDevIns The device instance to register the ports with.
4665	* @param hRegion The MMIO2 region handle.
4666	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4667	* @param cbSub Number of bytes to map into raw-mode. Must be page
4668	* aligned. Zero is an alias for everything.
4669	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4670	* @thread EMT(0)
4671	* @note Only available at VM creation time.
4672	*
4673	* @sa PDMDevHlpMmio2Create().
4674	*/
4675	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4676	size_t offSub, size_t cbSub, void **ppvMapping));
4677
4678	/**
4679	* Bus master physical memory read from the given PCI device.
4680	*
4681	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4682	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4683	* @param pDevIns The device instance.
4684	* @param pPciDev The PCI device structure. If NULL the default
4685	* PCI device for this device instance is used.
4686	* @param GCPhys Physical address start reading from.
4687	* @param pvBuf Where to put the read bits.
4688	* @param cbRead How many bytes to read.
4689	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4690	* @thread Any thread, but the call may involve the emulation thread.
4691	*/
4692	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4693	void *pvBuf, size_t cbRead, uint32_t fFlags));
4694
4695	/**
4696	* Bus master physical memory write from the given PCI device.
4697	*
4698	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4699	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4700	* @param pDevIns The device instance.
4701	* @param pPciDev The PCI device structure. If NULL the default
4702	* PCI device for this device instance is used.
4703	* @param GCPhys Physical address to write to.
4704	* @param pvBuf What to write.
4705	* @param cbWrite How many bytes to write.
4706	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4707	* @thread Any thread, but the call may involve the emulation thread.
4708	*/
4709	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4710	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4711
4712	/**
4713	* Set the IRQ for the given PCI device.
4714	*
4715	* @param pDevIns Device instance.
4716	* @param pPciDev The PCI device structure. If NULL the default
4717	* PCI device for this device instance is used.
4718	* @param iIrq IRQ number to set.
4719	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4720	* @thread Any thread, but will involve the emulation thread.
4721	*/
4722	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4723
4724	/**
4725	* Set ISA IRQ for a device.
4726	*
4727	* @param pDevIns Device instance.
4728	* @param iIrq IRQ number to set.
4729	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4730	* @thread Any thread, but will involve the emulation thread.
4731	*/
4732	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4733
4734	/**
4735	* Read physical memory.
4736	*
4737	* @returns VINF_SUCCESS (for now).
4738	* @param pDevIns Device instance.
4739	* @param GCPhys Physical address start reading from.
4740	* @param pvBuf Where to put the read bits.
4741	* @param cbRead How many bytes to read.
4742	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4743	*/
4744	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4745
4746	/**
4747	* Write to physical memory.
4748	*
4749	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4750	* @param pDevIns Device instance.
4751	* @param GCPhys Physical address to write to.
4752	* @param pvBuf What to write.
4753	* @param cbWrite How many bytes to write.
4754	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4755	*/
4756	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4757
4758	/**
4759	* Checks if the Gate A20 is enabled or not.
4760	*
4761	* @returns true if A20 is enabled.
4762	* @returns false if A20 is disabled.
4763	* @param pDevIns Device instance.
4764	* @thread The emulation thread.
4765	*/
4766	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4767
4768	/**
4769	* Gets the VM state.
4770	*
4771	* @returns VM state.
4772	* @param pDevIns The device instance.
4773	* @thread Any thread (just keep in mind that it's volatile info).
4774	*/
4775	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4776
4777	/**
4778	* Gets the VM handle. Restricted API.
4779	*
4780	* @returns VM Handle.
4781	* @param pDevIns Device instance.
4782	*/
4783	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4784
4785	/**
4786	* Gets the VMCPU handle. Restricted API.
4787	*
4788	* @returns VMCPU Handle.
4789	* @param pDevIns The device instance.
4790	*/
4791	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4792
4793	/**
4794	* The the VM CPU ID of the current thread (restricted API).
4795	*
4796	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4797	* @param pDevIns The device instance.
4798	*/
4799	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4800
4801	/**
4802	* Get the current virtual clock time in a VM. The clock frequency must be
4803	* queried separately.
4804	*
4805	* @returns Current clock time.
4806	* @param pDevIns The device instance.
4807	*/
4808	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4809
4810	/**
4811	* Get the frequency of the virtual clock.
4812	*
4813	* @returns The clock frequency (not variable at run-time).
4814	* @param pDevIns The device instance.
4815	*/
4816	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4817
4818	/**
4819	* Get the current virtual clock time in a VM, in nanoseconds.
4820	*
4821	* @returns Current clock time (in ns).
4822	* @param pDevIns The device instance.
4823	*/
4824	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4825
4826	/**
4827	* Gets the NOP critical section.
4828	*
4829	* @returns The ring-3 address of the NOP critical section.
4830	* @param pDevIns The device instance.
4831	*/
4832	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4833
4834	/**
4835	* Changes the device level critical section from the automatically created
4836	* default to one desired by the device constructor.
4837	*
4838	* Must first be done in ring-3.
4839	*
4840	* @returns VBox status code.
4841	* @param pDevIns The device instance.
4842	* @param pCritSect The critical section to use. NULL is not
4843	* valid, instead use the NOP critical
4844	* section.
4845	*/
4846	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4847
4848	/** @name Exported PDM Critical Section Functions
4849	* @{ */
4850	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4851	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4852	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4853	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4854	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4855	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4856	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4857	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4858	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4859	/** @} */
4860
4861	/** @name Exported PDM Read/Write Critical Section Functions
4862	* @{ */
4863	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4864	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4865	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4866	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4867	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4868
4869	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4870	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4871	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4872	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4873	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4874
4875	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4876	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4877	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4878	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4879	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4880	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4881	/** @} */
4882
4883	/**
4884	* Gets the trace buffer handle.
4885	*
4886	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4887	* really inteded for direct usage, thus no inline wrapper function.
4888	*
4889	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4890	* @param pDevIns The device instance.
4891	*/
4892	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4893
4894	/**
4895	* Sets up the PCI bus for the raw-mode context.
4896	*
4897	* This must be called after ring-3 has registered the PCI bus using
4898	* PDMDevHlpPCIBusRegister().
4899	*
4900	* @returns VBox status code.
4901	* @param pDevIns The device instance.
4902	* @param pPciBusReg The PCI bus registration information for raw-mode,
4903	* considered volatile.
4904	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4905	*/
4906	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4907
4908	/**
4909	* Sets up the IOMMU for the raw-mode context.
4910	*
4911	* This must be called after ring-3 has registered the IOMMU using
4912	* PDMDevHlpIommuRegister().
4913	*
4914	* @returns VBox status code.
4915	* @param pDevIns The device instance.
4916	* @param pIommuReg The IOMMU registration information for raw-mode,
4917	* considered volatile.
4918	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4919	*/
4920	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4921
4922	/**
4923	* Sets up the PIC for the ring-0 context.
4924	*
4925	* This must be called after ring-3 has registered the PIC using
4926	* PDMDevHlpPICRegister().
4927	*
4928	* @returns VBox status code.
4929	* @param pDevIns The device instance.
4930	* @param pPicReg The PIC registration information for ring-0,
4931	* considered volatile and copied.
4932	* @param ppPicHlp Where to return the ring-0 PIC helpers.
4933	*/
4934	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4935
4936	/**
4937	* Sets up the APIC for the raw-mode context.
4938	*
4939	* This must be called after ring-3 has registered the APIC using
4940	* PDMDevHlpApicRegister().
4941	*
4942	* @returns VBox status code.
4943	* @param pDevIns The device instance.
4944	*/
4945	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4946
4947	/**
4948	* Sets up the IOAPIC for the ring-0 context.
4949	*
4950	* This must be called after ring-3 has registered the PIC using
4951	* PDMDevHlpIoApicRegister().
4952	*
4953	* @returns VBox status code.
4954	* @param pDevIns The device instance.
4955	* @param pIoApicReg The PIC registration information for ring-0,
4956	* considered volatile and copied.
4957	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4958	*/
4959	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4960
4961	/**
4962	* Sets up the HPET for the raw-mode context.
4963	*
4964	* This must be called after ring-3 has registered the PIC using
4965	* PDMDevHlpHpetRegister().
4966	*
4967	* @returns VBox status code.
4968	* @param pDevIns The device instance.
4969	* @param pHpetReg The PIC registration information for raw-mode,
4970	* considered volatile and copied.
4971	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
4972	*/
4973	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4974
4975	/** Space reserved for future members.
4976	* @{ */
4977	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4978	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4979	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4980	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4981	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4982	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4983	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4984	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4985	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4986	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4987	/** @} */
4988
4989	/** Just a safety precaution. */
4990	uint32_t u32TheEnd;
4991	} PDMDEVHLPRC;
4992	/** Pointer PDM Device RC API. */
4993	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4994	/** Pointer PDM Device RC API. */
4995	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4996
4997	/** Current PDMDEVHLP version number. */
4998	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 18, 0)
4999
5000
5001	/**
5002	* PDM Device API - R0 Variant.
5003	*/
5004	typedef struct PDMDEVHLPR0
5005	{
5006	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5007	uint32_t u32Version;
5008
5009	/**
5010	* Sets up ring-0 callback handlers for an I/O port range.
5011	*
5012	* The range must have been created in ring-3 first using
5013	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5014	*
5015	* @returns VBox status.
5016	* @param pDevIns The device instance to register the ports with.
5017	* @param hIoPorts The I/O port range handle.
5018	* @param pfnOut Pointer to function which is gonna handle OUT
5019	* operations. Optional.
5020	* @param pfnIn Pointer to function which is gonna handle IN operations.
5021	* Optional.
5022	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5023	* operations. Optional.
5024	* @param pfnInStr Pointer to function which is gonna handle string IN
5025	* operations. Optional.
5026	* @param pvUser User argument to pass to the callbacks.
5027	*
5028	* @remarks Caller enters the device critical section prior to invoking the
5029	* registered callback methods.
5030	*
5031	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5032	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5033	*/
5034	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5035	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5036	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5037	void *pvUser));
5038
5039	/**
5040	* Sets up ring-0 callback handlers for an MMIO region.
5041	*
5042	* The region must have been created in ring-3 first using
5043	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5044	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5045	*
5046	* @returns VBox status.
5047	* @param pDevIns The device instance to register the ports with.
5048	* @param hRegion The MMIO region handle.
5049	* @param pfnWrite Pointer to function which is gonna handle Write
5050	* operations.
5051	* @param pfnRead Pointer to function which is gonna handle Read
5052	* operations.
5053	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5054	* operations. (optional)
5055	* @param pvUser User argument to pass to the callbacks.
5056	*
5057	* @remarks Caller enters the device critical section prior to invoking the
5058	* registered callback methods.
5059	*
5060	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5061	* PDMDevHlpMmioUnmap().
5062	*/
5063	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5064	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5065
5066	/**
5067	* Sets up a ring-0 mapping for an MMIO2 region.
5068	*
5069	* The region must have been created in ring-3 first using
5070	* PDMDevHlpMmio2Create().
5071	*
5072	* @returns VBox status.
5073	* @param pDevIns The device instance to register the ports with.
5074	* @param hRegion The MMIO2 region handle.
5075	* @param offSub Start of what to map into ring-0. Must be page aligned.
5076	* @param cbSub Number of bytes to map into ring-0. Must be page
5077	* aligned. Zero is an alias for everything.
5078	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5079	*
5080	* @thread EMT(0)
5081	* @note Only available at VM creation time.
5082	*
5083	* @sa PDMDevHlpMmio2Create().
5084	*/
5085	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5086	void **ppvMapping));
5087
5088	/**
5089	* Bus master physical memory read from the given PCI device.
5090	*
5091	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5092	* VERR_EM_MEMORY.
5093	* @param pDevIns The device instance.
5094	* @param pPciDev The PCI device structure. If NULL the default
5095	* PCI device for this device instance is used.
5096	* @param GCPhys Physical address start reading from.
5097	* @param pvBuf Where to put the read bits.
5098	* @param cbRead How many bytes to read.
5099	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5100	* @thread Any thread, but the call may involve the emulation thread.
5101	*/
5102	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5103	void *pvBuf, size_t cbRead, uint32_t fFlags));
5104
5105	/**
5106	* Bus master physical memory write from the given PCI device.
5107	*
5108	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5109	* VERR_EM_MEMORY.
5110	* @param pDevIns The device instance.
5111	* @param pPciDev The PCI device structure. If NULL the default
5112	* PCI device for this device instance is used.
5113	* @param GCPhys Physical address to write to.
5114	* @param pvBuf What to write.
5115	* @param cbWrite How many bytes to write.
5116	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5117	* @thread Any thread, but the call may involve the emulation thread.
5118	*/
5119	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5120	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5121
5122	/**
5123	* Set the IRQ for the given PCI device.
5124	*
5125	* @param pDevIns Device instance.
5126	* @param pPciDev The PCI device structure. If NULL the default
5127	* PCI device for this device instance is used.
5128	* @param iIrq IRQ number to set.
5129	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5130	* @thread Any thread, but will involve the emulation thread.
5131	*/
5132	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5133
5134	/**
5135	* Set ISA IRQ for a device.
5136	*
5137	* @param pDevIns Device instance.
5138	* @param iIrq IRQ number to set.
5139	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5140	* @thread Any thread, but will involve the emulation thread.
5141	*/
5142	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5143
5144	/**
5145	* Read physical memory.
5146	*
5147	* @returns VINF_SUCCESS (for now).
5148	* @param pDevIns Device instance.
5149	* @param GCPhys Physical address start reading from.
5150	* @param pvBuf Where to put the read bits.
5151	* @param cbRead How many bytes to read.
5152	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5153	*/
5154	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5155
5156	/**
5157	* Write to physical memory.
5158	*
5159	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5160	* @param pDevIns Device instance.
5161	* @param GCPhys Physical address to write to.
5162	* @param pvBuf What to write.
5163	* @param cbWrite How many bytes to write.
5164	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5165	*/
5166	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5167
5168	/**
5169	* Checks if the Gate A20 is enabled or not.
5170	*
5171	* @returns true if A20 is enabled.
5172	* @returns false if A20 is disabled.
5173	* @param pDevIns Device instance.
5174	* @thread The emulation thread.
5175	*/
5176	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5177
5178	/**
5179	* Gets the VM state.
5180	*
5181	* @returns VM state.
5182	* @param pDevIns The device instance.
5183	* @thread Any thread (just keep in mind that it's volatile info).
5184	*/
5185	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5186
5187	/**
5188	* Gets the VM handle. Restricted API.
5189	*
5190	* @returns VM Handle.
5191	* @param pDevIns Device instance.
5192	*/
5193	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5194
5195	/**
5196	* Gets the VMCPU handle. Restricted API.
5197	*
5198	* @returns VMCPU Handle.
5199	* @param pDevIns The device instance.
5200	*/
5201	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5202
5203	/**
5204	* The the VM CPU ID of the current thread (restricted API).
5205	*
5206	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5207	* @param pDevIns The device instance.
5208	*/
5209	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5210
5211	/** @name Timer handle method wrappers
5212	* @{ */
5213	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5214	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5215	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5216	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5217	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5218	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5219	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5220	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5221	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5222	/** Takes the clock lock then enters the specified critical section. */
5223	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5224	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5225	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5226	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5227	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5228	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5229	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5230	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5231	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5232	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5233	/** @} */
5234
5235	/**
5236	* Get the current virtual clock time in a VM. The clock frequency must be
5237	* queried separately.
5238	*
5239	* @returns Current clock time.
5240	* @param pDevIns The device instance.
5241	*/
5242	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5243
5244	/**
5245	* Get the frequency of the virtual clock.
5246	*
5247	* @returns The clock frequency (not variable at run-time).
5248	* @param pDevIns The device instance.
5249	*/
5250	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5251
5252	/**
5253	* Get the current virtual clock time in a VM, in nanoseconds.
5254	*
5255	* @returns Current clock time (in ns).
5256	* @param pDevIns The device instance.
5257	*/
5258	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5259
5260	/** @name Exported PDM Queue Functions
5261	* @{ */
5262	DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5263	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5264	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5265	DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5266	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5267	/** @} */
5268
5269	/** @name PDM Task
5270	* @{ */
5271	/**
5272	* Triggers the running the given task.
5273	*
5274	* @returns VBox status code.
5275	* @retval VINF_ALREADY_POSTED is the task is already pending.
5276	* @param pDevIns The device instance.
5277	* @param hTask The task to trigger.
5278	* @thread Any thread.
5279	*/
5280	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5281	/** @} */
5282
5283	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5284	* These semaphores can be signalled from ring-0.
5285	* @{ */
5286	/** @sa SUPSemEventSignal */
5287	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5288	/** @sa SUPSemEventWaitNoResume */
5289	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5290	/** @sa SUPSemEventWaitNsAbsIntr */
5291	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5292	/** @sa SUPSemEventWaitNsRelIntr */
5293	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5294	/** @sa SUPSemEventGetResolution */
5295	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5296	/** @} */
5297
5298	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5299	* These semaphores can be signalled from ring-0.
5300	* @{ */
5301	/** @sa SUPSemEventMultiSignal */
5302	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5303	/** @sa SUPSemEventMultiReset */
5304	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5305	/** @sa SUPSemEventMultiWaitNoResume */
5306	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5307	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5308	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5309	/** @sa SUPSemEventMultiWaitNsRelIntr */
5310	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5311	/** @sa SUPSemEventMultiGetResolution */
5312	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5313	/** @} */
5314
5315	/**
5316	* Gets the NOP critical section.
5317	*
5318	* @returns The ring-3 address of the NOP critical section.
5319	* @param pDevIns The device instance.
5320	*/
5321	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5322
5323	/**
5324	* Changes the device level critical section from the automatically created
5325	* default to one desired by the device constructor.
5326	*
5327	* Must first be done in ring-3.
5328	*
5329	* @returns VBox status code.
5330	* @param pDevIns The device instance.
5331	* @param pCritSect The critical section to use. NULL is not
5332	* valid, instead use the NOP critical
5333	* section.
5334	*/
5335	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5336
5337	/** @name Exported PDM Critical Section Functions
5338	* @{ */
5339	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5340	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5341	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5342	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5343	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5344	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5345	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5346	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5347	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5348	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5349	/** @} */
5350
5351	/** @name Exported PDM Read/Write Critical Section Functions
5352	* @{ */
5353	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5354	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5355	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5356	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5357	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5358
5359	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5360	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5361	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5362	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5363	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5364
5365	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5366	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5367	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5368	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5369	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5370	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5371	/** @} */
5372
5373	/**
5374	* Gets the trace buffer handle.
5375	*
5376	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5377	* really inteded for direct usage, thus no inline wrapper function.
5378	*
5379	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5380	* @param pDevIns The device instance.
5381	*/
5382	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5383
5384	/**
5385	* Sets up the PCI bus for the ring-0 context.
5386	*
5387	* This must be called after ring-3 has registered the PCI bus using
5388	* PDMDevHlpPCIBusRegister().
5389	*
5390	* @returns VBox status code.
5391	* @param pDevIns The device instance.
5392	* @param pPciBusReg The PCI bus registration information for ring-0,
5393	* considered volatile and copied.
5394	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5395	*/
5396	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5397
5398	/**
5399	* Sets up the IOMMU for the ring-0 context.
5400	*
5401	* This must be called after ring-3 has registered the IOMMU using
5402	* PDMDevHlpIommuRegister().
5403	*
5404	* @returns VBox status code.
5405	* @param pDevIns The device instance.
5406	* @param pIommuReg The IOMMU registration information for ring-0,
5407	* considered volatile and copied.
5408	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5409	*/
5410	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5411
5412	/**
5413	* Sets up the PIC for the ring-0 context.
5414	*
5415	* This must be called after ring-3 has registered the PIC using
5416	* PDMDevHlpPICRegister().
5417	*
5418	* @returns VBox status code.
5419	* @param pDevIns The device instance.
5420	* @param pPicReg The PIC registration information for ring-0,
5421	* considered volatile and copied.
5422	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5423	*/
5424	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5425
5426	/**
5427	* Sets up the APIC for the ring-0 context.
5428	*
5429	* This must be called after ring-3 has registered the APIC using
5430	* PDMDevHlpApicRegister().
5431	*
5432	* @returns VBox status code.
5433	* @param pDevIns The device instance.
5434	*/
5435	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5436
5437	/**
5438	* Sets up the IOAPIC for the ring-0 context.
5439	*
5440	* This must be called after ring-3 has registered the PIC using
5441	* PDMDevHlpIoApicRegister().
5442	*
5443	* @returns VBox status code.
5444	* @param pDevIns The device instance.
5445	* @param pIoApicReg The PIC registration information for ring-0,
5446	* considered volatile and copied.
5447	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5448	*/
5449	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5450
5451	/**
5452	* Sets up the HPET for the ring-0 context.
5453	*
5454	* This must be called after ring-3 has registered the PIC using
5455	* PDMDevHlpHpetRegister().
5456	*
5457	* @returns VBox status code.
5458	* @param pDevIns The device instance.
5459	* @param pHpetReg The PIC registration information for ring-0,
5460	* considered volatile and copied.
5461	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5462	*/
5463	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5464
5465	/** Space reserved for future members.
5466	* @{ */
5467	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5468	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5469	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5470	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5471	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5472	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5473	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5474	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5475	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5476	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5477	/** @} */
5478
5479	/** Just a safety precaution. */
5480	uint32_t u32TheEnd;
5481	} PDMDEVHLPR0;
5482	/** Pointer PDM Device R0 API. */
5483	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5484	/** Pointer PDM Device GC API. */
5485	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5486
5487	/** Current PDMDEVHLP version number. */
5488	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 21, 0)
5489
5490
5491	/**
5492	* PDM Device Instance.
5493	*/
5494	typedef struct PDMDEVINSR3
5495	{
5496	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5497	uint32_t u32Version;
5498	/** Device instance number. */
5499	uint32_t iInstance;
5500	/** Size of the ring-3, raw-mode and shared bits. */
5501	uint32_t cbRing3;
5502	/** Set if ring-0 context is enabled. */
5503	bool fR0Enabled;
5504	/** Set if raw-mode context is enabled. */
5505	bool fRCEnabled;
5506	/** Alignment padding. */
5507	bool afReserved[2];
5508	/** Pointer the HC PDM Device API. */
5509	PCPDMDEVHLPR3 pHlpR3;
5510	/** Pointer to the shared device instance data. */
5511	RTR3PTR pvInstanceDataR3;
5512	/** Pointer to the device instance data for ring-3. */
5513	RTR3PTR pvInstanceDataForR3;
5514	/** The critical section for the device.
5515	*
5516	* TM and IOM will enter this critical section before calling into the device
5517	* code. PDM will when doing power on, power off, reset, suspend and resume
5518	* notifications. SSM will currently not, but this will be changed later on.
5519	*
5520	* The device gets a critical section automatically assigned to it before
5521	* the constructor is called. If the constructor wishes to use a different
5522	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5523	* very early on.
5524	*/
5525	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5526	/** Pointer to device registration structure. */
5527	R3PTRTYPE(PCPDMDEVREG) pReg;
5528	/** Configuration handle. */
5529	R3PTRTYPE(PCFGMNODE) pCfg;
5530	/** The base interface of the device.
5531	*
5532	* The device constructor initializes this if it has any
5533	* device level interfaces to export. To obtain this interface
5534	* call PDMR3QueryDevice(). */
5535	PDMIBASE IBase;
5536
5537	/** Tracing indicator. */
5538	uint32_t fTracing;
5539	/** The tracing ID of this device. */
5540	uint32_t idTracing;
5541
5542	/** Ring-3 pointer to the raw-mode device instance. */
5543	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5544	/** Raw-mode address of the raw-mode device instance. */
5545	RTRGPTR pDevInsForRC;
5546	/** Ring-3 pointer to the raw-mode instance data. */
5547	RTR3PTR pvInstanceDataForRCR3;
5548
5549	/** PCI device structure size. */
5550	uint32_t cbPciDev;
5551	/** Number of PCI devices in apPciDevs. */
5552	uint32_t cPciDevs;
5553	/** Pointer to the PCI devices for this device.
5554	* (Allocated after the shared instance data.)
5555	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5556	* two devices ever needing it can use cbPciDev and do the address
5557	* calculations that for entries 8+. */
5558	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5559
5560	/** Temporarily. */
5561	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5562	/** Temporarily. */
5563	RTR0PTR pvInstanceDataR0;
5564	/** Temporarily. */
5565	RTRCPTR pvInstanceDataRC;
5566	/** Align the internal data more naturally. */
5567	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5568
5569	/** Internal data. */
5570	union
5571	{
5572	#ifdef PDMDEVINSINT_DECLARED
5573	PDMDEVINSINTR3 s;
5574	#endif
5575	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5576	} Internal;
5577
5578	/** Device instance data for ring-3. The size of this area is defined
5579	* in the PDMDEVREG::cbInstanceR3 field. */
5580	char achInstanceData[8];
5581	} PDMDEVINSR3;
5582
5583	/** Current PDMDEVINSR3 version number. */
5584	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5585
5586	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5587	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5588
5589
5590	/**
5591	* PDM ring-0 device instance.
5592	*/
5593	typedef struct PDMDEVINSR0
5594	{
5595	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5596	uint32_t u32Version;
5597	/** Device instance number. */
5598	uint32_t iInstance;
5599
5600	/** Pointer the HC PDM Device API. */
5601	PCPDMDEVHLPR0 pHlpR0;
5602	/** Pointer to the shared device instance data. */
5603	RTR0PTR pvInstanceDataR0;
5604	/** Pointer to the device instance data for ring-0. */
5605	RTR0PTR pvInstanceDataForR0;
5606	/** The critical section for the device.
5607	*
5608	* TM and IOM will enter this critical section before calling into the device
5609	* code. PDM will when doing power on, power off, reset, suspend and resume
5610	* notifications. SSM will currently not, but this will be changed later on.
5611	*
5612	* The device gets a critical section automatically assigned to it before
5613	* the constructor is called. If the constructor wishes to use a different
5614	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5615	* very early on.
5616	*/
5617	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5618	/** Pointer to the ring-0 device registration structure. */
5619	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5620	/** Ring-3 address of the ring-3 device instance. */
5621	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5622	/** Ring-0 pointer to the ring-3 device instance. */
5623	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5624	/** Ring-0 pointer to the ring-3 instance data. */
5625	RTR0PTR pvInstanceDataForR3R0;
5626	/** Raw-mode address of the raw-mode device instance. */
5627	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5628	/** Ring-0 pointer to the raw-mode device instance. */
5629	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5630	/** Ring-0 pointer to the raw-mode instance data. */
5631	RTR0PTR pvInstanceDataForRCR0;
5632
5633	/** PCI device structure size. */
5634	uint32_t cbPciDev;
5635	/** Number of PCI devices in apPciDevs. */
5636	uint32_t cPciDevs;
5637	/** Pointer to the PCI devices for this device.
5638	* (Allocated after the shared instance data.)
5639	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5640	* two devices ever needing it can use cbPciDev and do the address
5641	* calculations that for entries 8+. */
5642	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5643
5644	/** Align the internal data more naturally. */
5645	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5646
5647	/** Internal data. */
5648	union
5649	{
5650	#ifdef PDMDEVINSINT_DECLARED
5651	PDMDEVINSINTR0 s;
5652	#endif
5653	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5654	} Internal;
5655
5656	/** Device instance data for ring-0. The size of this area is defined
5657	* in the PDMDEVREG::cbInstanceR0 field. */
5658	char achInstanceData[8];
5659	} PDMDEVINSR0;
5660
5661	/** Current PDMDEVINSR0 version number. */
5662	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5663
5664
5665	/**
5666	* PDM raw-mode device instance.
5667	*/
5668	typedef struct PDMDEVINSRC
5669	{
5670	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5671	uint32_t u32Version;
5672	/** Device instance number. */
5673	uint32_t iInstance;
5674
5675	/** Pointer the HC PDM Device API. */
5676	PCPDMDEVHLPRC pHlpRC;
5677	/** Pointer to the shared device instance data. */
5678	RTRGPTR pvInstanceDataRC;
5679	/** Pointer to the device instance data for raw-mode. */
5680	RTRGPTR pvInstanceDataForRC;
5681	/** The critical section for the device.
5682	*
5683	* TM and IOM will enter this critical section before calling into the device
5684	* code. PDM will when doing power on, power off, reset, suspend and resume
5685	* notifications. SSM will currently not, but this will be changed later on.
5686	*
5687	* The device gets a critical section automatically assigned to it before
5688	* the constructor is called. If the constructor wishes to use a different
5689	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5690	* very early on.
5691	*/
5692	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5693	/** Pointer to the raw-mode device registration structure. */
5694	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5695
5696	/** PCI device structure size. */
5697	uint32_t cbPciDev;
5698	/** Number of PCI devices in apPciDevs. */
5699	uint32_t cPciDevs;
5700	/** Pointer to the PCI devices for this device.
5701	* (Allocated after the shared instance data.) */
5702	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5703
5704	/** Align the internal data more naturally. */
5705	uint32_t au32Padding[14];
5706
5707	/** Internal data. */
5708	union
5709	{
5710	#ifdef PDMDEVINSINT_DECLARED
5711	PDMDEVINSINTRC s;
5712	#endif
5713	uint8_t padding[0x10];
5714	} Internal;
5715
5716	/** Device instance data for ring-0. The size of this area is defined
5717	* in the PDMDEVREG::cbInstanceR0 field. */
5718	char achInstanceData[8];
5719	} PDMDEVINSRC;
5720
5721	/** Current PDMDEVINSR0 version number. */
5722	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5723
5724
5725	/** @def PDM_DEVINS_VERSION
5726	* Current PDMDEVINS version number. */
5727	/** @typedef PDMDEVINS
5728	* The device instance structure for the current context. */
5729	#ifdef IN_RING3
5730	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5731	typedef PDMDEVINSR3 PDMDEVINS;
5732	#elif defined(IN_RING0)
5733	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5734	typedef PDMDEVINSR0 PDMDEVINS;
5735	#elif defined(IN_RC)
5736	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5737	typedef PDMDEVINSRC PDMDEVINS;
5738	#else
5739	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5740	#endif
5741
5742	/**
5743	* Get the pointer to an PCI device.
5744	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5745	*/
5746	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5747	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5748	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5749
5750	/**
5751	* Calc the pointer to of a given PCI device.
5752	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5753	*/
5754	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5755	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5756	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5757	: (PPDMPCIDEV)NULL )
5758
5759
5760	/**
5761	* Checks the structure versions of the device instance and device helpers,
5762	* returning if they are incompatible.
5763	*
5764	* This is for use in the constructor.
5765	*
5766	* @param pDevIns The device instance pointer.
5767	*/
5768	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5769	do \
5770	{ \
5771	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5772	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5773	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5774	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5775	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5776	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5777	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5778	} while (0)
5779
5780	/**
5781	* Quietly checks the structure versions of the device instance and device
5782	* helpers, returning if they are incompatible.
5783	*
5784	* This is for use in the destructor.
5785	*
5786	* @param pDevIns The device instance pointer.
5787	*/
5788	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5789	do \
5790	{ \
5791	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5792	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5793	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5794	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5795	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5796	} while (0)
5797
5798	/**
5799	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5800	* constructor - returns on failure.
5801	*
5802	* This should be invoked after having initialized the instance data
5803	* sufficiently for the correct operation of the destructor. The destructor is
5804	* always called!
5805	*
5806	* @param pDevIns Pointer to the PDM device instance.
5807	* @param pszValidValues Patterns describing the valid value names. See
5808	* RTStrSimplePatternMultiMatch for details on the
5809	* pattern syntax.
5810	* @param pszValidNodes Patterns describing the valid node (key) names.
5811	* Pass empty string if no valid nodes.
5812	*/
5813	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5814	do \
5815	{ \
5816	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5817	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5818	if (RT_SUCCESS(rcValCfg)) \
5819	{ /* likely */ } else return rcValCfg; \
5820	} while (0)
5821
5822	/** @def PDMDEV_ASSERT_EMT
5823	* Assert that the current thread is the emulation thread.
5824	*/
5825	#ifdef VBOX_STRICT
5826	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5827	#else
5828	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5829	#endif
5830
5831	/** @def PDMDEV_ASSERT_OTHER
5832	* Assert that the current thread is NOT the emulation thread.
5833	*/
5834	#ifdef VBOX_STRICT
5835	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5836	#else
5837	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5838	#endif
5839
5840	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5841	* Assert that the current thread is owner of the VM lock.
5842	*/
5843	#ifdef VBOX_STRICT
5844	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5845	#else
5846	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5847	#endif
5848
5849	/** @def PDMDEV_SET_ERROR
5850	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5851	*/
5852	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5853	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5854
5855	/** @def PDMDEV_SET_RUNTIME_ERROR
5856	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5857	*/
5858	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5859	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5860
5861	/** @def PDMDEVINS_2_RCPTR
5862	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
5863	*/
5864	#ifdef IN_RC
5865	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5866	#else
5867	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5868	#endif
5869
5870	/** @def PDMDEVINS_2_R3PTR
5871	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
5872	*/
5873	#ifdef IN_RING3
5874	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5875	#else
5876	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5877	#endif
5878
5879	/** @def PDMDEVINS_2_R0PTR
5880	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
5881	*/
5882	#ifdef IN_RING0
5883	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5884	#else
5885	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5886	#endif
5887
5888	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5889	* Converts a PDM device instance data pointer to a ring-0 one.
5890	* @deprecated
5891	*/
5892	#ifdef IN_RING0
5893	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5894	#else
5895	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5896	#endif
5897
5898
5899	/** @def PDMDEVINS_2_DATA
5900	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5901	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5902	*
5903	* @note Do no use this macro in common code working on a core structure which
5904	* device specific code has expanded.
5905	*/
5906	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5907	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5908	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5909	{ \
5910	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5911	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5912	return pLambdaRet; \
5913	}(a_pDevIns))
5914	#else
5915	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5916	#endif
5917
5918	/** @def PDMDEVINS_2_DATA_CC
5919	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5920	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5921	*
5922	* @note Do no use this macro in common code working on a core structure which
5923	* device specific code has expanded.
5924	*/
5925	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5926	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5927	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5928	{ \
5929	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5930	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5931	return pLambdaRet; \
5932	}(a_pDevIns))
5933	#else
5934	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5935	#endif
5936
5937
5938	#ifdef IN_RING3
5939
5940	/**
5941	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5942	*/
5943	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5944	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5945	PIOMIOPORTHANDLE phIoPorts)
5946	{
5947	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5948	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5949	if (RT_SUCCESS(rc))
5950	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5951	return rc;
5952	}
5953
5954	/**
5955	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5956	*/
5957	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5958	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5959	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5960	{
5961	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5962	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5963	if (RT_SUCCESS(rc))
5964	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5965	return rc;
5966	}
5967
5968	/**
5969	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5970	*/
5971	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5972	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5973	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5974	{
5975	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5976	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5977	if (RT_SUCCESS(rc))
5978	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5979	return rc;
5980	}
5981
5982	/**
5983	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5984	*/
5985	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5986	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5987	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5988	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5989	{
5990	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5991	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5992	if (RT_SUCCESS(rc))
5993	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5994	return rc;
5995	}
5996
5997	/**
5998	* @sa PDMDevHlpIoPortCreateEx
5999	*/
6000	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6001	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6002	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6003	{
6004	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6005	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6006	}
6007
6008
6009	/**
6010	* @sa PDMDevHlpIoPortCreateEx
6011	*/
6012	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6013	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6014	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6015	{
6016	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6017	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6018	}
6019
6020	/**
6021	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6022	*/
6023	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6024	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6025	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6026	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6027	{
6028	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6029	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6030	}
6031
6032	/**
6033	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6034	*/
6035	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6036	{
6037	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6038	}
6039
6040	/**
6041	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6042	*/
6043	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6044	{
6045	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6046	}
6047
6048	/**
6049	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6050	*/
6051	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6052	{
6053	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6054	}
6055
6056
6057	#endif /* IN_RING3 */
6058	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6059
6060	/**
6061	* @sa PDMDevHlpIoPortSetUpContextEx
6062	*/
6063	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6064	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6065	{
6066	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6067	}
6068
6069	/**
6070	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6071	*/
6072	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6073	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6074	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6075	{
6076	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6077	}
6078
6079	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6080	#ifdef IN_RING3
6081
6082	/**
6083	* @sa PDMDevHlpMmioCreateEx
6084	*/
6085	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6086	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6087	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6088	{
6089	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6090	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6091	}
6092
6093	/**
6094	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6095	*/
6096	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6097	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6098	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6099	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6100	{
6101	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6102	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6103	}
6104
6105	/**
6106	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6107	*/
6108	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6109	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6110	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6111	{
6112	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6113	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6114	if (RT_SUCCESS(rc))
6115	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6116	return rc;
6117	}
6118
6119	/**
6120	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6121	*/
6122	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6123	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6124	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6125	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6126	{
6127	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6128	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6129	if (RT_SUCCESS(rc))
6130	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6131	return rc;
6132	}
6133
6134	/**
6135	* @copydoc PDMDEVHLPR3::pfnMmioMap
6136	*/
6137	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6138	{
6139	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6140	}
6141
6142	/**
6143	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6144	*/
6145	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6146	{
6147	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6148	}
6149
6150	/**
6151	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6152	*/
6153	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6154	{
6155	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6156	}
6157
6158	/**
6159	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6160	*/
6161	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6162	{
6163	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6164	}
6165
6166	#endif /* IN_RING3 */
6167	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6168
6169	/**
6170	* @sa PDMDevHlpMmioSetUpContextEx
6171	*/
6172	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6173	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6174	{
6175	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6176	}
6177
6178	/**
6179	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6180	*/
6181	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6182	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6183	{
6184	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6185	}
6186
6187	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6188	#ifdef IN_RING3
6189
6190	/**
6191	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6192	*/
6193	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6194	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6195	{
6196	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6197	}
6198
6199	/**
6200	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6201	*/
6202	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6203	{
6204	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6205	}
6206
6207	/**
6208	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6209	*/
6210	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6211	{
6212	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6213	}
6214
6215	/**
6216	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6217	*/
6218	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6219	{
6220	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6221	}
6222
6223	/**
6224	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6225	*/
6226	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6227	{
6228	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6229	}
6230
6231	#endif /* IN_RING3 */
6232	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6233
6234	/**
6235	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6236	*/
6237	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6238	size_t offSub, size_t cbSub, void **ppvMapping)
6239	{
6240	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6241	}
6242
6243	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6244	#ifdef IN_RING3
6245
6246	/**
6247	* @copydoc PDMDEVHLPR3::pfnROMRegister
6248	*/
6249	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6250	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6251	{
6252	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6253	}
6254
6255	/**
6256	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6257	*/
6258	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6259	{
6260	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6261	}
6262
6263	/**
6264	* Register a save state data unit.
6265	*
6266	* @returns VBox status.
6267	* @param pDevIns The device instance.
6268	* @param uVersion Data layout version number.
6269	* @param cbGuess The approximate amount of data in the unit.
6270	* Only for progress indicators.
6271	* @param pfnSaveExec Execute save callback, optional.
6272	* @param pfnLoadExec Execute load callback, optional.
6273	*/
6274	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6275	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6276	{
6277	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6278	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6279	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6280	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6281	}
6282
6283	/**
6284	* Register a save state data unit with a live save callback as well.
6285	*
6286	* @returns VBox status.
6287	* @param pDevIns The device instance.
6288	* @param uVersion Data layout version number.
6289	* @param cbGuess The approximate amount of data in the unit.
6290	* Only for progress indicators.
6291	* @param pfnLiveExec Execute live callback, optional.
6292	* @param pfnSaveExec Execute save callback, optional.
6293	* @param pfnLoadExec Execute load callback, optional.
6294	*/
6295	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6296	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6297	{
6298	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6299	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6300	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6301	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6302	}
6303
6304	/**
6305	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6306	*/
6307	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6308	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6309	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6310	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6311	{
6312	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6313	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6314	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6315	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6316	}
6317
6318	/**
6319	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6320	*/
6321	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6322	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6323	{
6324	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6325	}
6326
6327	#endif /* IN_RING3 */
6328
6329	/**
6330	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6331	*/
6332	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6333	{
6334	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6335	}
6336
6337	/**
6338	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6339	*/
6340	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6341	{
6342	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6343	}
6344
6345	/**
6346	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6347	*/
6348	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6349	{
6350	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6351	}
6352
6353	/**
6354	* @copydoc PDMDEVHLPR3::pfnTimerGet
6355	*/
6356	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6357	{
6358	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6359	}
6360
6361	/**
6362	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6363	*/
6364	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6365	{
6366	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6367	}
6368
6369	/**
6370	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6371	*/
6372	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6373	{
6374	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6375	}
6376
6377	/**
6378	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6379	*/
6380	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6381	{
6382	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6383	}
6384
6385	/**
6386	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6387	*/
6388	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6389	{
6390	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6391	}
6392
6393	/**
6394	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6395	*/
6396	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6397	{
6398	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6399	}
6400
6401	/**
6402	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6403	*/
6404	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6405	{
6406	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6407	}
6408
6409	/**
6410	* @copydoc PDMDEVHLPR3::pfnTimerSet
6411	*/
6412	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6413	{
6414	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6415	}
6416
6417	/**
6418	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6419	*/
6420	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6421	{
6422	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6423	}
6424
6425	/**
6426	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6427	*/
6428	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6429	{
6430	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6431	}
6432
6433	/**
6434	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6435	*/
6436	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6437	{
6438	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6439	}
6440
6441	/**
6442	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6443	*/
6444	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6445	{
6446	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6447	}
6448
6449	/**
6450	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6451	*/
6452	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6453	{
6454	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6455	}
6456
6457	/**
6458	* @copydoc PDMDEVHLPR3::pfnTimerStop
6459	*/
6460	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6461	{
6462	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6463	}
6464
6465	/**
6466	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6467	*/
6468	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6469	{
6470	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6471	}
6472
6473	/**
6474	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6475	*/
6476	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6477	{
6478	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6479	}
6480
6481	#ifdef IN_RING3
6482
6483	/**
6484	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6485	*/
6486	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6487	{
6488	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6489	}
6490
6491	/**
6492	* @copydoc PDMDEVHLPR3::pfnTimerSave
6493	*/
6494	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6495	{
6496	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6497	}
6498
6499	/**
6500	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6501	*/
6502	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6503	{
6504	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6505	}
6506
6507	/**
6508	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6509	*/
6510	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6511	{
6512	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6513	}
6514
6515	/**
6516	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6517	*/
6518	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6519	{
6520	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6521	}
6522
6523	#endif
6524
6525	/**
6526	* Read physical memory - unknown data usage.
6527	*
6528	* @returns VINF_SUCCESS (for now).
6529	* @param pDevIns The device instance.
6530	* @param GCPhys Physical address start reading from.
6531	* @param pvBuf Where to put the read bits.
6532	* @param cbRead How many bytes to read.
6533	* @thread Any thread, but the call may involve the emulation thread.
6534	*/
6535	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6536	{
6537	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6538	}
6539
6540	/**
6541	* Write to physical memory - unknown data usage.
6542	*
6543	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6544	* @param pDevIns The device instance.
6545	* @param GCPhys Physical address to write to.
6546	* @param pvBuf What to write.
6547	* @param cbWrite How many bytes to write.
6548	* @thread Any thread, but the call may involve the emulation thread.
6549	*/
6550	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6551	{
6552	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6553	}
6554
6555	/**
6556	* Read physical memory - reads meta data processed by the device.
6557	*
6558	* @returns VINF_SUCCESS (for now).
6559	* @param pDevIns The device instance.
6560	* @param GCPhys Physical address start reading from.
6561	* @param pvBuf Where to put the read bits.
6562	* @param cbRead How many bytes to read.
6563	* @thread Any thread, but the call may involve the emulation thread.
6564	*/
6565	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6566	{
6567	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6568	}
6569
6570	/**
6571	* Write to physical memory - written data was created/altered by the device.
6572	*
6573	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6574	* @param pDevIns The device instance.
6575	* @param GCPhys Physical address to write to.
6576	* @param pvBuf What to write.
6577	* @param cbWrite How many bytes to write.
6578	* @thread Any thread, but the call may involve the emulation thread.
6579	*/
6580	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6581	{
6582	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6583	}
6584
6585	/**
6586	* Read physical memory - read data will not be touched by the device.
6587	*
6588	* @returns VINF_SUCCESS (for now).
6589	* @param pDevIns The device instance.
6590	* @param GCPhys Physical address start reading from.
6591	* @param pvBuf Where to put the read bits.
6592	* @param cbRead How many bytes to read.
6593	* @thread Any thread, but the call may involve the emulation thread.
6594	*/
6595	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6596	{
6597	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6598	}
6599
6600	/**
6601	* Write to physical memory - written data was not touched/created by the device.
6602	*
6603	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6604	* @param pDevIns The device instance.
6605	* @param GCPhys Physical address to write to.
6606	* @param pvBuf What to write.
6607	* @param cbWrite How many bytes to write.
6608	* @thread Any thread, but the call may involve the emulation thread.
6609	*/
6610	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6611	{
6612	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6613	}
6614
6615	#ifdef IN_RING3
6616
6617	/**
6618	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6619	*/
6620	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6621	{
6622	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6623	}
6624
6625	/**
6626	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6627	*/
6628	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6629	PPGMPAGEMAPLOCK pLock)
6630	{
6631	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6632	}
6633
6634	/**
6635	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6636	*/
6637	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6638	{
6639	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6640	}
6641
6642	/**
6643	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6644	*/
6645	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6646	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6647	{
6648	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6649	}
6650
6651	/**
6652	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6653	*/
6654	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6655	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6656	{
6657	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6658	}
6659
6660	/**
6661	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6662	*/
6663	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6664	{
6665	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6666	}
6667
6668	/**
6669	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6670	*/
6671	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6672	{
6673	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6674	}
6675
6676	/**
6677	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
6678	*/
6679	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
6680	{
6681	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
6682	}
6683
6684	/**
6685	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6686	*/
6687	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6688	{
6689	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6690	}
6691
6692	/**
6693	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6694	*/
6695	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6696	{
6697	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6698	}
6699
6700	/**
6701	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6702	*/
6703	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6704	{
6705	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6706	}
6707
6708	/**
6709	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6710	*/
6711	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6712	{
6713	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6714	}
6715
6716	/**
6717	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6718	*/
6719	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6720	{
6721	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6722	}
6723
6724	/**
6725	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6726	*/
6727	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6728	{
6729	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6730	}
6731	#endif /* IN_RING3 */
6732
6733	/**
6734	* @copydoc PDMDEVHLPR3::pfnVMState
6735	*/
6736	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6737	{
6738	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6739	}
6740
6741	#ifdef IN_RING3
6742
6743	/**
6744	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6745	*/
6746	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6747	{
6748	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6749	}
6750
6751	/**
6752	* Set the VM error message
6753	*
6754	* @returns rc.
6755	* @param pDevIns The device instance.
6756	* @param rc VBox status code.
6757	* @param SRC_POS Use RT_SRC_POS.
6758	* @param pszFormat Error message format string.
6759	* @param ... Error message arguments.
6760	* @sa VMSetError
6761	*/
6762	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6763	const char *pszFormat, ...)
6764	{
6765	va_list va;
6766	va_start(va, pszFormat);
6767	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6768	va_end(va);
6769	return rc;
6770	}
6771
6772	/**
6773	* Set the VM runtime error message
6774	*
6775	* @returns VBox status code.
6776	* @param pDevIns The device instance.
6777	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
6778	* @param pszErrorId Error ID string.
6779	* @param pszFormat Error message format string.
6780	* @param ... Error message arguments.
6781	* @sa VMSetRuntimeError
6782	*/
6783	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6784	const char *pszFormat, ...)
6785	{
6786	va_list va;
6787	int rc;
6788	va_start(va, pszFormat);
6789	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6790	va_end(va);
6791	return rc;
6792	}
6793
6794	#endif /* IN_RING3 */
6795
6796	/**
6797	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6798	*
6799	* @returns VBox status code which must be passed up to the VMM. This will be
6800	* VINF_SUCCESS in non-strict builds.
6801	* @param pDevIns The device instance.
6802	* @param SRC_POS Use RT_SRC_POS.
6803	* @param pszFormat Message. (optional)
6804	* @param ... Message parameters.
6805	*/
6806	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6807	{
6808	#ifdef VBOX_STRICT
6809	# ifdef IN_RING3
6810	int rc;
6811	va_list args;
6812	va_start(args, pszFormat);
6813	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6814	va_end(args);
6815	return rc;
6816	# else
6817	NOREF(pDevIns);
6818	NOREF(pszFile);
6819	NOREF(iLine);
6820	NOREF(pszFunction);
6821	NOREF(pszFormat);
6822	return VINF_EM_DBG_STOP;
6823	# endif
6824	#else
6825	NOREF(pDevIns);
6826	NOREF(pszFile);
6827	NOREF(iLine);
6828	NOREF(pszFunction);
6829	NOREF(pszFormat);
6830	return VINF_SUCCESS;
6831	#endif
6832	}
6833
6834	#ifdef IN_RING3
6835
6836	/**
6837	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6838	*/
6839	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6840	{
6841	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6842	}
6843
6844	/**
6845	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6846	*/
6847	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6848	{
6849	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6850	}
6851
6852	/**
6853	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6854	*/
6855	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6856	{
6857	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6858	}
6859
6860	/**
6861	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6862	*/
6863	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6864	{
6865	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6866	}
6867
6868	/**
6869	* Same as pfnSTAMRegister except that the name is specified in a
6870	* RTStrPrintf like fashion.
6871	*
6872	* @returns VBox status.
6873	* @param pDevIns Device instance of the DMA.
6874	* @param pvSample Pointer to the sample.
6875	* @param enmType Sample type. This indicates what pvSample is
6876	* pointing at.
6877	* @param enmVisibility Visibility type specifying whether unused
6878	* statistics should be visible or not.
6879	* @param enmUnit Sample unit.
6880	* @param pszDesc Sample description.
6881	* @param pszName Sample name format string, unix path style. If
6882	* this does not start with a '/', the default
6883	* prefix will be prepended, otherwise it will be
6884	* used as-is.
6885	* @param ... Arguments to the format string.
6886	*/
6887	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6888	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6889	const char pszDesc, const char pszName, ...)
6890	{
6891	va_list va;
6892	va_start(va, pszName);
6893	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6894	va_end(va);
6895	}
6896
6897	/**
6898	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
6899	*/
6900	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
6901	{
6902	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
6903	}
6904
6905	/**
6906	* Registers the device with the default PCI bus.
6907	*
6908	* @returns VBox status code.
6909	* @param pDevIns The device instance.
6910	* @param pPciDev The PCI device structure.
6911	* This must be kept in the instance data.
6912	* The PCI configuration must be initialized before registration.
6913	*/
6914	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6915	{
6916	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6917	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6918	}
6919
6920	/**
6921	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6922	*/
6923	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6924	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6925	{
6926	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6927	}
6928
6929	/**
6930	* Initialize MSI emulation support for the first PCI device.
6931	*
6932	* @returns VBox status code.
6933	* @param pDevIns The device instance.
6934	* @param pMsiReg MSI emulation registration structure.
6935	*/
6936	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6937	{
6938	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6939	}
6940
6941	/**
6942	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6943	*/
6944	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6945	{
6946	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6947	}
6948
6949	/**
6950	* Registers a I/O port region for the default PCI device.
6951	*
6952	* @returns VBox status code.
6953	* @param pDevIns The device instance.
6954	* @param iRegion The region number.
6955	* @param cbRegion Size of the region.
6956	* @param hIoPorts Handle to the I/O port region.
6957	*/
6958	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6959	{
6960	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6961	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6962	}
6963
6964	/**
6965	* Registers a I/O port region for the default PCI device, custom map/unmap.
6966	*
6967	* @returns VBox status code.
6968	* @param pDevIns The device instance.
6969	* @param iRegion The region number.
6970	* @param cbRegion Size of the region.
6971	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6972	* callback will be invoked holding only the PDM lock.
6973	* The device lock will _not_ be taken (due to lock
6974	* order).
6975	*/
6976	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6977	PFNPCIIOREGIONMAP pfnMapUnmap)
6978	{
6979	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6980	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6981	UINT64_MAX, pfnMapUnmap);
6982	}
6983
6984	/**
6985	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6986	* and registering an I/O port region for the default PCI device.
6987	*
6988	* @returns VBox status code.
6989	* @param pDevIns The device instance to register the ports with.
6990	* @param cPorts The count of I/O ports in the region (the size).
6991	* @param iPciRegion The PCI device region.
6992	* @param pfnOut Pointer to function which is gonna handle OUT
6993	* operations. Optional.
6994	* @param pfnIn Pointer to function which is gonna handle IN operations.
6995	* Optional.
6996	* @param pvUser User argument to pass to the callbacks.
6997	* @param pszDesc Pointer to description string. This must not be freed.
6998	* @param paExtDescs Extended per-port descriptions, optional. Partial range
6999	* coverage is allowed. This must not be freed.
7000	* @param phIoPorts Where to return the I/O port range handle.
7001	*
7002	*/
7003	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7004	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7005	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7006
7007	{
7008	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7009	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7010	if (RT_SUCCESS(rc))
7011	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7012	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7013	phIoPorts, NULL /pfnMapUnmap*/);
7014	return rc;
7015	}
7016
7017	/**
7018	* Registers an MMIO region for the default PCI device.
7019	*
7020	* @returns VBox status code.
7021	* @param pDevIns The device instance.
7022	* @param iRegion The region number.
7023	* @param cbRegion Size of the region.
7024	* @param enmType PCI_ADDRESS_SPACE_MEM or
7025	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7026	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7027	* @param hMmioRegion Handle to the MMIO region.
7028	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7029	* callback will be invoked holding only the PDM lock.
7030	* The device lock will _not_ be taken (due to lock
7031	* order).
7032	*/
7033	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7034	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7035	{
7036	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7037	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7038	hMmioRegion, pfnMapUnmap);
7039	}
7040
7041	/**
7042	* Registers an MMIO region for the default PCI device, extended version.
7043	*
7044	* @returns VBox status code.
7045	* @param pDevIns The device instance.
7046	* @param pPciDev The PCI device structure.
7047	* @param iRegion The region number.
7048	* @param cbRegion Size of the region.
7049	* @param enmType PCI_ADDRESS_SPACE_MEM or
7050	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7051	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7052	* @param hMmioRegion Handle to the MMIO region.
7053	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7054	* callback will be invoked holding only the PDM lock.
7055	* The device lock will _not_ be taken (due to lock
7056	* order).
7057	*/
7058	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7059	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7060	PFNPCIIOREGIONMAP pfnMapUnmap)
7061	{
7062	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7063	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7064	hMmioRegion, pfnMapUnmap);
7065	}
7066
7067	/**
7068	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7069	* and registering an MMIO region for the default PCI device.
7070	*
7071	* @returns VBox status code.
7072	* @param pDevIns The device instance to register the ports with.
7073	* @param cbRegion The size of the region in bytes.
7074	* @param iPciRegion The PCI device region.
7075	* @param enmType PCI_ADDRESS_SPACE_MEM or
7076	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7077	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7078	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7079	* @param pfnWrite Pointer to function which is gonna handle Write
7080	* operations.
7081	* @param pfnRead Pointer to function which is gonna handle Read
7082	* operations.
7083	* @param pvUser User argument to pass to the callbacks.
7084	* @param pszDesc Pointer to description string. This must not be freed.
7085	* @param phRegion Where to return the MMIO region handle.
7086	*
7087	*/
7088	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7089	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7090	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7091
7092	{
7093	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7094	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7095	if (RT_SUCCESS(rc))
7096	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7097	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7098	phRegion, NULL /pfnMapUnmap*/);
7099	return rc;
7100	}
7101
7102
7103	/**
7104	* Registers an MMIO2 region for the default PCI device.
7105	*
7106	* @returns VBox status code.
7107	* @param pDevIns The device instance.
7108	* @param iRegion The region number.
7109	* @param cbRegion Size of the region.
7110	* @param enmType PCI_ADDRESS_SPACE_MEM or
7111	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7112	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7113	* @param hMmio2Region Handle to the MMIO2 region.
7114	*/
7115	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7116	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7117	{
7118	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7119	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7120	hMmio2Region, NULL);
7121	}
7122
7123	/**
7124	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7125	* and registering an MMIO2 region for the default PCI device, extended edition.
7126	*
7127	* @returns VBox status code.
7128	* @param pDevIns The device instance to register the ports with.
7129	* @param cbRegion The size of the region in bytes.
7130	* @param iPciRegion The PCI device region.
7131	* @param enmType PCI_ADDRESS_SPACE_MEM or
7132	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7133	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7134	* @param pszDesc Pointer to description string. This must not be freed.
7135	* @param ppvMapping Where to store the address of the ring-3 mapping of
7136	* the memory.
7137	* @param phRegion Where to return the MMIO2 region handle.
7138	*
7139	*/
7140	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7141	PCIADDRESSSPACE enmType, const char *pszDesc,
7142	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7143
7144	{
7145	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7146	pszDesc, ppvMapping, phRegion);
7147	if (RT_SUCCESS(rc))
7148	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7149	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7150	phRegion, NULL /pfnCallback*/);
7151	return rc;
7152	}
7153
7154	/**
7155	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7156	* and registering an MMIO2 region for the default PCI device.
7157	*
7158	* @returns VBox status code.
7159	* @param pDevIns The device instance to register the ports with.
7160	* @param cbRegion The size of the region in bytes.
7161	* @param iPciRegion The PCI device region.
7162	* @param enmType PCI_ADDRESS_SPACE_MEM or
7163	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7164	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7165	* @param fMmio2Flags To be defined, must be zero.
7166	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7167	* callback will be invoked holding only the PDM lock.
7168	* The device lock will _not_ be taken (due to lock
7169	* order).
7170	* @param pszDesc Pointer to description string. This must not be freed.
7171	* @param ppvMapping Where to store the address of the ring-3 mapping of
7172	* the memory.
7173	* @param phRegion Where to return the MMIO2 region handle.
7174	*
7175	*/
7176	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7177	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7178	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7179
7180	{
7181	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7182	pszDesc, ppvMapping, phRegion);
7183	if (RT_SUCCESS(rc))
7184	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7185	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7186	*phRegion, pfnMapUnmap);
7187	return rc;
7188	}
7189
7190	/**
7191	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7192	*/
7193	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7194	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7195	{
7196	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7197	}
7198
7199	/**
7200	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7201	*/
7202	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7203	unsigned cb, uint32_t *pu32Value)
7204	{
7205	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7206	}
7207
7208	/**
7209	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7210	*/
7211	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7212	unsigned cb, uint32_t u32Value)
7213	{
7214	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7215	}
7216
7217	#endif /* IN_RING3 */
7218
7219	/**
7220	* Bus master physical memory read from the default PCI device.
7221	*
7222	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7223	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7224	* @param pDevIns The device instance.
7225	* @param GCPhys Physical address start reading from.
7226	* @param pvBuf Where to put the read bits.
7227	* @param cbRead How many bytes to read.
7228	* @thread Any thread, but the call may involve the emulation thread.
7229	*/
7230	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7231	{
7232	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7233	}
7234
7235	/**
7236	* Bus master physical memory read - unknown data usage.
7237	*
7238	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7239	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7240	* @param pDevIns The device instance.
7241	* @param pPciDev The PCI device structure. If NULL the default
7242	* PCI device for this device instance is used.
7243	* @param GCPhys Physical address start reading from.
7244	* @param pvBuf Where to put the read bits.
7245	* @param cbRead How many bytes to read.
7246	* @thread Any thread, but the call may involve the emulation thread.
7247	*/
7248	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7249	{
7250	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7251	}
7252
7253	/**
7254	* Bus master physical memory read from the default PCI device.
7255	*
7256	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7257	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7258	* @param pDevIns The device instance.
7259	* @param GCPhys Physical address start reading from.
7260	* @param pvBuf Where to put the read bits.
7261	* @param cbRead How many bytes to read.
7262	* @thread Any thread, but the call may involve the emulation thread.
7263	*/
7264	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7265	{
7266	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7267	}
7268
7269	/**
7270	* Bus master physical memory read - reads meta data processed by the device.
7271	*
7272	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7273	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7274	* @param pDevIns The device instance.
7275	* @param pPciDev The PCI device structure. If NULL the default
7276	* PCI device for this device instance is used.
7277	* @param GCPhys Physical address start reading from.
7278	* @param pvBuf Where to put the read bits.
7279	* @param cbRead How many bytes to read.
7280	* @thread Any thread, but the call may involve the emulation thread.
7281	*/
7282	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7283	{
7284	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7285	}
7286
7287	/**
7288	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7289	*
7290	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7291	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7292	* @param pDevIns The device instance.
7293	* @param GCPhys Physical address start reading from.
7294	* @param pvBuf Where to put the read bits.
7295	* @param cbRead How many bytes to read.
7296	* @thread Any thread, but the call may involve the emulation thread.
7297	*/
7298	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7299	{
7300	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7301	}
7302
7303	/**
7304	* Bus master physical memory read - read data will not be touched by the device.
7305	*
7306	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7307	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7308	* @param pDevIns The device instance.
7309	* @param pPciDev The PCI device structure. If NULL the default
7310	* PCI device for this device instance is used.
7311	* @param GCPhys Physical address start reading from.
7312	* @param pvBuf Where to put the read bits.
7313	* @param cbRead How many bytes to read.
7314	* @thread Any thread, but the call may involve the emulation thread.
7315	*/
7316	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7317	{
7318	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7319	}
7320
7321	/**
7322	* Bus master physical memory write from the default PCI device - unknown data usage.
7323	*
7324	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7325	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7326	* @param pDevIns The device instance.
7327	* @param GCPhys Physical address to write to.
7328	* @param pvBuf What to write.
7329	* @param cbWrite How many bytes to write.
7330	* @thread Any thread, but the call may involve the emulation thread.
7331	*/
7332	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7333	{
7334	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7335	}
7336
7337	/**
7338	* Bus master physical memory write - unknown data usage.
7339	*
7340	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7341	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7342	* @param pDevIns The device instance.
7343	* @param pPciDev The PCI device structure. If NULL the default
7344	* PCI device for this device instance is used.
7345	* @param GCPhys Physical address to write to.
7346	* @param pvBuf What to write.
7347	* @param cbWrite How many bytes to write.
7348	* @thread Any thread, but the call may involve the emulation thread.
7349	*/
7350	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7351	{
7352	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7353	}
7354
7355	/**
7356	* Bus master physical memory write from the default PCI device.
7357	*
7358	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7359	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7360	* @param pDevIns The device instance.
7361	* @param GCPhys Physical address to write to.
7362	* @param pvBuf What to write.
7363	* @param cbWrite How many bytes to write.
7364	* @thread Any thread, but the call may involve the emulation thread.
7365	*/
7366	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7367	{
7368	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7369	}
7370
7371	/**
7372	* Bus master physical memory write - written data was created/altered by the device.
7373	*
7374	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7375	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7376	* @param pDevIns The device instance.
7377	* @param pPciDev The PCI device structure. If NULL the default
7378	* PCI device for this device instance is used.
7379	* @param GCPhys Physical address to write to.
7380	* @param pvBuf What to write.
7381	* @param cbWrite How many bytes to write.
7382	* @thread Any thread, but the call may involve the emulation thread.
7383	*/
7384	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7385	{
7386	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7387	}
7388
7389	/**
7390	* Bus master physical memory write from the default PCI device.
7391	*
7392	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7393	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7394	* @param pDevIns The device instance.
7395	* @param GCPhys Physical address to write to.
7396	* @param pvBuf What to write.
7397	* @param cbWrite How many bytes to write.
7398	* @thread Any thread, but the call may involve the emulation thread.
7399	*/
7400	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7401	{
7402	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7403	}
7404
7405	/**
7406	* Bus master physical memory write - written data was not touched/created by the device.
7407	*
7408	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7409	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7410	* @param pDevIns The device instance.
7411	* @param pPciDev The PCI device structure. If NULL the default
7412	* PCI device for this device instance is used.
7413	* @param GCPhys Physical address to write to.
7414	* @param pvBuf What to write.
7415	* @param cbWrite How many bytes to write.
7416	* @thread Any thread, but the call may involve the emulation thread.
7417	*/
7418	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7419	{
7420	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7421	}
7422
7423	#ifdef IN_RING3
7424	/**
7425	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7426	*/
7427	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7428	void **ppv, PPGMPAGEMAPLOCK pLock)
7429	{
7430	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7431	}
7432
7433	/**
7434	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7435	*/
7436	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7437	void const **ppv, PPGMPAGEMAPLOCK pLock)
7438	{
7439	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7440	}
7441
7442	/**
7443	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7444	*/
7445	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7446	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7447	PPGMPAGEMAPLOCK paLocks)
7448	{
7449	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7450	paLocks);
7451	}
7452
7453	/**
7454	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7455	*/
7456	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7457	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7458	PPGMPAGEMAPLOCK paLocks)
7459	{
7460	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7461	papvPages, paLocks);
7462	}
7463	#endif /* IN_RING3 */
7464
7465	/**
7466	* Sets the IRQ for the default PCI device.
7467	*
7468	* @param pDevIns The device instance.
7469	* @param iIrq IRQ number to set.
7470	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7471	* @thread Any thread, but will involve the emulation thread.
7472	*/
7473	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7474	{
7475	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7476	}
7477
7478	/**
7479	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7480	*/
7481	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7482	{
7483	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7484	}
7485
7486	/**
7487	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7488	* the request when not called from EMT.
7489	*
7490	* @param pDevIns The device instance.
7491	* @param iIrq IRQ number to set.
7492	* @param iLevel IRQ level.
7493	* @thread Any thread, but will involve the emulation thread.
7494	*/
7495	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7496	{
7497	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7498	}
7499
7500	/**
7501	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7502	*/
7503	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7504	{
7505	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7506	}
7507
7508	/**
7509	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7510	*/
7511	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7512	{
7513	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7514	}
7515
7516	/**
7517	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7518	*/
7519	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7520	{
7521	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7522	}
7523
7524	#ifdef IN_RING3
7525
7526	/**
7527	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7528	*/
7529	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7530	{
7531	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7532	}
7533
7534	/**
7535	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7536	*/
7537	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7538	{
7539	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7540	}
7541
7542	/**
7543	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7544	*/
7545	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7546	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
7547	{
7548	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7549	}
7550
7551	/**
7552	* Reconfigures with a single driver reattachement, no config, noflags.
7553	* @sa PDMDevHlpDriverReconfigure
7554	*/
7555	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7556	{
7557	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7558	}
7559
7560	/**
7561	* Reconfigures with a two drivers reattachement, no config, noflags.
7562	* @sa PDMDevHlpDriverReconfigure
7563	*/
7564	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
7565	{
7566	char const * apszDrivers[2];
7567	apszDrivers[0] = pszDriver0;
7568	apszDrivers[1] = pszDriver1;
7569	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7570	}
7571
7572	/**
7573	* @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7574	*/
7575	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7576	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
7577	{
7578	return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7579	}
7580
7581	/**
7582	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7583	*/
7584	DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7585	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7586	{
7587	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7588	}
7589
7590	#endif /* IN_RING3 */
7591
7592	/**
7593	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7594	*/
7595	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7596	{
7597	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7598	}
7599
7600	/**
7601	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7602	*/
7603	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7604	{
7605	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7606	}
7607
7608	/**
7609	* @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7610	*/
7611	DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7612	{
7613	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7614	}
7615
7616	/**
7617	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7618	*/
7619	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7620	{
7621	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7622	}
7623
7624	#ifdef IN_RING3
7625	/**
7626	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7627	*/
7628	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7629	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7630	{
7631	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7632	}
7633	#endif
7634
7635	/**
7636	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7637	*/
7638	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7639	{
7640	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7641	}
7642
7643	#ifdef IN_RING3
7644
7645	/**
7646	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7647	*/
7648	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7649	{
7650	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7651	}
7652
7653	/**
7654	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7655	*/
7656	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7657	{
7658	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7659	}
7660
7661	#endif /* IN_RING3 */
7662
7663	/**
7664	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7665	*/
7666	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7667	{
7668	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7669	}
7670
7671	/**
7672	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7673	*/
7674	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7675	{
7676	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7677	}
7678
7679	/**
7680	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7681	*/
7682	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7683	{
7684	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7685	}
7686
7687	/**
7688	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7689	*/
7690	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7691	{
7692	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7693	}
7694
7695	/**
7696	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7697	*/
7698	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7699	{
7700	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7701	}
7702
7703	#ifdef IN_RING3
7704
7705	/**
7706	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7707	*/
7708	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7709	{
7710	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7711	}
7712
7713	/**
7714	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7715	*/
7716	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7717	{
7718	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7719	}
7720
7721	#endif /* IN_RING3 */
7722
7723	/**
7724	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7725	*/
7726	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7727	{
7728	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7729	}
7730
7731	/**
7732	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7733	*/
7734	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7735	{
7736	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7737	}
7738
7739	/**
7740	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7741	*/
7742	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7743	{
7744	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7745	}
7746
7747	/**
7748	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7749	*/
7750	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7751	{
7752	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7753	}
7754
7755	/**
7756	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7757	*/
7758	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7759	{
7760	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7761	}
7762
7763	/**
7764	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7765	*/
7766	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7767	{
7768	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7769	}
7770
7771	#ifdef IN_RING3
7772
7773	/**
7774	* Initializes a PDM critical section.
7775	*
7776	* The PDM critical sections are derived from the IPRT critical sections, but
7777	* works in RC and R0 as well.
7778	*
7779	* @returns VBox status code.
7780	* @param pDevIns The device instance.
7781	* @param pCritSect Pointer to the critical section.
7782	* @param SRC_POS Use RT_SRC_POS.
7783	* @param pszNameFmt Format string for naming the critical section.
7784	* For statistics and lock validation.
7785	* @param ... Arguments for the format string.
7786	*/
7787	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7788	const char *pszNameFmt, ...)
7789	{
7790	int rc;
7791	va_list va;
7792	va_start(va, pszNameFmt);
7793	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7794	va_end(va);
7795	return rc;
7796	}
7797
7798	#endif /* IN_RING3 */
7799
7800	/**
7801	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7802	*/
7803	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7804	{
7805	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7806	}
7807
7808	#ifdef IN_RING3
7809
7810	/**
7811	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7812	*/
7813	DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7814	{
7815	return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7816	}
7817
7818	/**
7819	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7820	*/
7821	DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7822	{
7823	return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7824	}
7825
7826	#endif /* IN_RING3 */
7827
7828	/**
7829	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7830	*/
7831	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7832	{
7833	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7834	}
7835
7836	/**
7837	* Enters a PDM critical section.
7838	*
7839	* @returns VINF_SUCCESS if entered successfully.
7840	* @returns rcBusy when encountering a busy critical section in RC/R0.
7841	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7842	* during the operation.
7843	*
7844	* @param pDevIns The device instance.
7845	* @param pCritSect The PDM critical section to enter.
7846	* @param rcBusy The status code to return when we're in RC or R0
7847	* and the section is busy. Pass VINF_SUCCESS to
7848	* acquired the critical section thru a ring-3
7849	* call if necessary.
7850	*
7851	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
7852	* possible failures in ring-0 or at least apply
7853	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
7854	* function.
7855	*
7856	* @sa PDMCritSectEnter
7857	*/
7858	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7859	{
7860	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7861	}
7862
7863	/**
7864	* Enters a PDM critical section, with location information for debugging.
7865	*
7866	* @returns VINF_SUCCESS if entered successfully.
7867	* @returns rcBusy when encountering a busy critical section in RC/R0.
7868	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7869	* during the operation.
7870	*
7871	* @param pDevIns The device instance.
7872	* @param pCritSect The PDM critical section to enter.
7873	* @param rcBusy The status code to return when we're in RC or R0
7874	* and the section is busy. Pass VINF_SUCCESS to
7875	* acquired the critical section thru a ring-3
7876	* call if necessary.
7877	* @param uId Some kind of locking location ID. Typically a
7878	* return address up the stack. Optional (0).
7879	* @param SRC_POS The source position where to lock is being
7880	* acquired from. Optional.
7881	* @sa PDMCritSectEnterDebug
7882	*/
7883	DECLINLINE(DECL_CHECK_RETURN(int))
7884	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7885	{
7886	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7887	}
7888
7889	/**
7890	* Try enter a critical section.
7891	*
7892	* @retval VINF_SUCCESS on success.
7893	* @retval VERR_SEM_BUSY if the critsect was owned.
7894	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
7895	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7896	* during the operation.
7897	*
7898	* @param pDevIns The device instance.
7899	* @param pCritSect The critical section.
7900	* @sa PDMCritSectTryEnter
7901	*/
7902	DECLINLINE(DECL_CHECK_RETURN(int))
7903	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7904	{
7905	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7906	}
7907
7908	/**
7909	* Try enter a critical section, with location information for debugging.
7910	*
7911	* @retval VINF_SUCCESS on success.
7912	* @retval VERR_SEM_BUSY if the critsect was owned.
7913	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
7914	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
7915	* during the operation.
7916	*
7917	* @param pDevIns The device instance.
7918	* @param pCritSect The critical section.
7919	* @param uId Some kind of locking location ID. Typically a
7920	* return address up the stack. Optional (0).
7921	* @param SRC_POS The source position where to lock is being
7922	* acquired from. Optional.
7923	* @sa PDMCritSectTryEnterDebug
7924	*/
7925	DECLINLINE(DECL_CHECK_RETURN(int))
7926	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7927	{
7928	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7929	}
7930
7931	/**
7932	* Leaves a critical section entered with PDMCritSectEnter().
7933	*
7934	* @returns Indication whether we really exited the critical section.
7935	* @retval VINF_SUCCESS if we really exited.
7936	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
7937	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
7938	*
7939	* @param pDevIns The device instance.
7940	* @param pCritSect The PDM critical section to leave.
7941	* @sa PDMCritSectLeave
7942	*/
7943	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7944	{
7945	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7946	}
7947
7948	/**
7949	* @see PDMCritSectIsOwner
7950	*/
7951	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7952	{
7953	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7954	}
7955
7956	/**
7957	* @see PDMCritSectIsInitialized
7958	*/
7959	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7960	{
7961	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7962	}
7963
7964	/**
7965	* @see PDMCritSectHasWaiters
7966	*/
7967	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7968	{
7969	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7970	}
7971
7972	/**
7973	* @see PDMCritSectGetRecursion
7974	*/
7975	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7976	{
7977	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7978	}
7979
7980	#if defined(IN_RING3) \|\| defined(IN_RING0)
7981	/**
7982	* @see PDMHCCritSectScheduleExitEvent
7983	*/
7984	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7985	{
7986	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7987	}
7988	#endif
7989
7990	/* Strict build: Remap the two enter calls to the debug versions. */
7991	#ifdef VBOX_STRICT
7992	# ifdef IPRT_INCLUDED_asm_h
7993	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7994	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7995	# else
7996	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7997	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7998	# endif
7999	#endif
8000
8001	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8002
8003	/**
8004	* Deletes the critical section.
8005	*
8006	* @returns VBox status code.
8007	* @param pDevIns The device instance.
8008	* @param pCritSect The PDM critical section to destroy.
8009	* @sa PDMR3CritSectDelete
8010	*/
8011	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8012	{
8013	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8014	}
8015
8016	/**
8017	* Initializes a PDM read/write critical section.
8018	*
8019	* The PDM read/write critical sections are derived from the IPRT critical
8020	* sections, but works in RC and R0 as well.
8021	*
8022	* @returns VBox status code.
8023	* @param pDevIns The device instance.
8024	* @param pCritSect Pointer to the read/write critical section.
8025	* @param SRC_POS Use RT_SRC_POS.
8026	* @param pszNameFmt Format string for naming the critical section.
8027	* For statistics and lock validation.
8028	* @param ... Arguments for the format string.
8029	*/
8030	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8031	const char *pszNameFmt, ...)
8032	{
8033	int rc;
8034	va_list va;
8035	va_start(va, pszNameFmt);
8036	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8037	va_end(va);
8038	return rc;
8039	}
8040
8041	/**
8042	* Deletes the read/write critical section.
8043	*
8044	* @returns VBox status code.
8045	* @param pDevIns The device instance.
8046	* @param pCritSect The PDM read/write critical section to destroy.
8047	* @sa PDMR3CritSectRwDelete
8048	*/
8049	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8050	{
8051	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8052	}
8053
8054	#endif /* IN_RING3 */
8055
8056	/**
8057	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8058	*/
8059	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8060	{
8061	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8062	}
8063
8064	/**
8065	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8066	*/
8067	DECLINLINE(DECL_CHECK_RETURN(int))
8068	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8069	{
8070	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8071	}
8072
8073	/**
8074	* @sa PDMCritSectRwTryEnterShared
8075	*/
8076	DECLINLINE(DECL_CHECK_RETURN(int))
8077	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8078	{
8079	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8080	}
8081
8082	/**
8083	* @sa PDMCritSectRwTryEnterSharedDebug
8084	*/
8085	DECLINLINE(DECL_CHECK_RETURN(int))
8086	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8087	{
8088	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8089	}
8090
8091	/**
8092	* @sa PDMCritSectRwLeaveShared
8093	*/
8094	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8095	{
8096	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8097	}
8098
8099	/**
8100	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8101	*/
8102	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8103	{
8104	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8105	}
8106
8107	/**
8108	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8109	*/
8110	DECLINLINE(DECL_CHECK_RETURN(int))
8111	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8112	{
8113	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8114	}
8115
8116	/**
8117	* @sa PDMCritSectRwTryEnterExcl
8118	*/
8119	DECLINLINE(DECL_CHECK_RETURN(int))
8120	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8121	{
8122	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8123	}
8124
8125	/**
8126	* @sa PDMCritSectRwTryEnterExclDebug
8127	*/
8128	DECLINLINE(DECL_CHECK_RETURN(int))
8129	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8130	{
8131	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8132	}
8133
8134	/**
8135	* @sa PDMCritSectRwLeaveExcl
8136	*/
8137	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8138	{
8139	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8140	}
8141
8142	/**
8143	* @see PDMCritSectRwIsWriteOwner
8144	*/
8145	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8146	{
8147	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8148	}
8149
8150	/**
8151	* @see PDMCritSectRwIsReadOwner
8152	*/
8153	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8154	{
8155	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
8156	}
8157
8158	/**
8159	* @see PDMCritSectRwGetWriteRecursion
8160	*/
8161	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8162	{
8163	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
8164	}
8165
8166	/**
8167	* @see PDMCritSectRwGetWriterReadRecursion
8168	*/
8169	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8170	{
8171	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
8172	}
8173
8174	/**
8175	* @see PDMCritSectRwGetReadCount
8176	*/
8177	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8178	{
8179	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
8180	}
8181
8182	/**
8183	* @see PDMCritSectRwIsInitialized
8184	*/
8185	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8186	{
8187	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
8188	}
8189
8190	/* Strict build: Remap the two enter calls to the debug versions. */
8191	#ifdef VBOX_STRICT
8192	# ifdef IPRT_INCLUDED_asm_h
8193	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8194	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8195	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8196	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8197	# else
8198	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8199	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8200	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8201	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8202	# endif
8203	#endif
8204
8205	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8206
8207	/**
8208	* @copydoc PDMDEVHLPR3::pfnThreadCreate
8209	*/
8210	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
8211	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
8212	{
8213	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
8214	}
8215
8216	/**
8217	* @copydoc PDMR3ThreadDestroy
8218	* @param pDevIns The device instance.
8219	*/
8220	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
8221	{
8222	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
8223	}
8224
8225	/**
8226	* @copydoc PDMR3ThreadIAmSuspending
8227	* @param pDevIns The device instance.
8228	*/
8229	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8230	{
8231	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
8232	}
8233
8234	/**
8235	* @copydoc PDMR3ThreadIAmRunning
8236	* @param pDevIns The device instance.
8237	*/
8238	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8239	{
8240	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
8241	}
8242
8243	/**
8244	* @copydoc PDMR3ThreadSleep
8245	* @param pDevIns The device instance.
8246	*/
8247	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
8248	{
8249	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
8250	}
8251
8252	/**
8253	* @copydoc PDMR3ThreadSuspend
8254	* @param pDevIns The device instance.
8255	*/
8256	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8257	{
8258	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
8259	}
8260
8261	/**
8262	* @copydoc PDMR3ThreadResume
8263	* @param pDevIns The device instance.
8264	*/
8265	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
8266	{
8267	return pDevIns->pHlpR3->pfnThreadResume(pThread);
8268	}
8269
8270	/**
8271	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
8272	*/
8273	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
8274	{
8275	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
8276	}
8277
8278	/**
8279	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
8280	*/
8281	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
8282	{
8283	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
8284	}
8285
8286	/**
8287	* @copydoc PDMDEVHLPR3::pfnA20Set
8288	*/
8289	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
8290	{
8291	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
8292	}
8293
8294	/**
8295	* @copydoc PDMDEVHLPR3::pfnRTCRegister
8296	*/
8297	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
8298	{
8299	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
8300	}
8301
8302	/**
8303	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
8304	*/
8305	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
8306	{
8307	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
8308	}
8309
8310	/**
8311	* @copydoc PDMDEVHLPR3::pfnIommuRegister
8312	*/
8313	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
8314	{
8315	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
8316	}
8317
8318	/**
8319	* @copydoc PDMDEVHLPR3::pfnPICRegister
8320	*/
8321	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8322	{
8323	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
8324	}
8325
8326	/**
8327	* @copydoc PDMDEVHLPR3::pfnApicRegister
8328	*/
8329	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
8330	{
8331	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8332	}
8333
8334	/**
8335	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8336	*/
8337	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8338	{
8339	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8340	}
8341
8342	/**
8343	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8344	*/
8345	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8346	{
8347	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8348	}
8349
8350	/**
8351	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8352	*/
8353	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8354	{
8355	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8356	}
8357
8358	/**
8359	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8360	*/
8361	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8362	{
8363	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8364	}
8365
8366	/**
8367	* @copydoc PDMDEVHLPR3::pfnDMARegister
8368	*/
8369	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8370	{
8371	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8372	}
8373
8374	/**
8375	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8376	*/
8377	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8378	{
8379	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8380	}
8381
8382	/**
8383	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8384	*/
8385	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8386	{
8387	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8388	}
8389
8390	/**
8391	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8392	*/
8393	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8394	{
8395	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8396	}
8397
8398	/**
8399	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8400	*/
8401	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8402	{
8403	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8404	}
8405
8406	/**
8407	* @copydoc PDMDEVHLPR3::pfnDMASchedule
8408	*/
8409	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8410	{
8411	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8412	}
8413
8414	/**
8415	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
8416	*/
8417	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8418	{
8419	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8420	}
8421
8422	/**
8423	* @copydoc PDMDEVHLPR3::pfnCMOSRead
8424	*/
8425	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8426	{
8427	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8428	}
8429
8430	/**
8431	* @copydoc PDMDEVHLPR3::pfnCallR0
8432	*/
8433	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8434	{
8435	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8436	}
8437
8438	/**
8439	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8440	*/
8441	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8442	{
8443	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8444	}
8445
8446	/**
8447	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8448	*/
8449	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8450	{
8451	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8452	}
8453
8454	/**
8455	* @copydoc PDMDEVHLPR3::pfnGetUVM
8456	*/
8457	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8458	{
8459	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8460	}
8461
8462	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
8463
8464	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8465
8466	/**
8467	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8468	*/
8469	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8470	{
8471	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8472	}
8473
8474	/**
8475	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8476	*/
8477	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8478	{
8479	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8480	}
8481
8482	/**
8483	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8484	*/
8485	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8486	{
8487	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8488	}
8489
8490	/**
8491	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8492	*/
8493	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8494	{
8495	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8496	}
8497
8498	/**
8499	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8500	*/
8501	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8502	{
8503	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8504	}
8505
8506	/**
8507	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8508	*/
8509	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8510	{
8511	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8512	}
8513
8514	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8515
8516	/**
8517	* @copydoc PDMDEVHLPR3::pfnGetVM
8518	*/
8519	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8520	{
8521	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8522	}
8523
8524	/**
8525	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8526	*/
8527	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8528	{
8529	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8530	}
8531
8532	/**
8533	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8534	*/
8535	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8536	{
8537	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8538	}
8539
8540	/**
8541	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8542	*/
8543	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8544	{
8545	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8546	}
8547
8548	/**
8549	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8550	*/
8551	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8552	{
8553	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8554	}
8555
8556	/**
8557	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8558	*/
8559	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8560	{
8561	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8562	}
8563
8564	#ifdef IN_RING3
8565
8566	/**
8567	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8568	*/
8569	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8570	{
8571	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8572	}
8573
8574	/**
8575	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8576	*/
8577	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8578	{
8579	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8580	}
8581
8582	/**
8583	* @copydoc PDMDEVHLPR3::pfnVMReset
8584	*/
8585	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8586	{
8587	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8588	}
8589
8590	/**
8591	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8592	*/
8593	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8594	{
8595	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8596	}
8597
8598	/**
8599	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8600	*/
8601	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8602	{
8603	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8604	}
8605
8606	/**
8607	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8608	*/
8609	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8610	{
8611	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8612	}
8613
8614	#endif /* IN_RING3 */
8615
8616	/**
8617	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8618	*/
8619	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8620	{
8621	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8622	}
8623
8624	#ifdef IN_RING3
8625
8626	/**
8627	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8628	*/
8629	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8630	{
8631	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8632	}
8633
8634	/**
8635	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8636	*/
8637	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8638	{
8639	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8640	}
8641
8642	/**
8643	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8644	*/
8645	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8646	{
8647	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8648	}
8649
8650	/**
8651	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8652	*/
8653	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8654	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8655	const char pszHandlerR0, const char pszPfHandlerR0,
8656	const char pszHandlerRC, const char pszPfHandlerRC,
8657	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8658	{
8659	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8660	pszHandlerR0, pszPfHandlerR0,
8661	pszHandlerRC, pszPfHandlerRC,
8662	pszDesc, phType);
8663	}
8664
8665	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8666	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8667	do { \
8668	uint32_t u32GetEnumTmp = 0; \
8669	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8670	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8671	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8672	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8673	} while (0)
8674
8675	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8676	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8677	do { \
8678	uint8_t bGetEnumTmp = 0; \
8679	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8680	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8681	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
8682	} while (0)
8683
8684	#endif /* IN_RING3 */
8685
8686	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8687	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8688
8689	/**
8690	* Callbacks for VBoxDeviceRegister().
8691	*/
8692	typedef struct PDMDEVREGCB
8693	{
8694	/** Interface version.
8695	* This is set to PDM_DEVREG_CB_VERSION. */
8696	uint32_t u32Version;
8697
8698	/**
8699	* Registers a device with the current VM instance.
8700	*
8701	* @returns VBox status code.
8702	* @param pCallbacks Pointer to the callback table.
8703	* @param pReg Pointer to the device registration record.
8704	* This data must be permanent and readonly.
8705	*/
8706	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8707	} PDMDEVREGCB;
8708
8709	/** Current version of the PDMDEVREGCB structure. */
8710	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8711
8712
8713	/**
8714	* The VBoxDevicesRegister callback function.
8715	*
8716	* PDM will invoke this function after loading a device module and letting
8717	* the module decide which devices to register and how to handle conflicts.
8718	*
8719	* @returns VBox status code.
8720	* @param pCallbacks Pointer to the callback table.
8721	* @param u32Version VBox version number.
8722	*/
8723	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
8724
8725	/** @} */
8726
8727	RT_C_DECLS_END
8728
8729	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 91014

以其他格式下載: