pdmdev.h@ 81667

最後變更在這個檔案從81667是 81624,由 vboxsync 提交於 5 年前
PDM,PGM: Added handled based MMIO2 interface. Made some adjustments to the PCI I/O region registrations. (Preps for VMMDev.) bugref:9218
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Id Revision`
檔案大小: 335.7 KB

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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.alldomusa.eu.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmqueue.h>
34	#include <VBox/vmm/pdmtask.h>
35	#ifdef IN_RING3
36	# include <VBox/vmm/pdmthread.h>
37	#endif
38	#include <VBox/vmm/pdmifs.h>
39	#include <VBox/vmm/pdmins.h>
40	#include <VBox/vmm/pdmcommon.h>
41	#include <VBox/vmm/pdmpcidev.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/tm.h>
44	#include <VBox/vmm/ssm.h>
45	#include <VBox/vmm/cfgm.h>
46	#include <VBox/vmm/dbgf.h>
47	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
48	#include <iprt/stdarg.h>
49	#include <iprt/list.h>
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_pdm_device The PDM Devices API
55	* @ingroup grp_pdm
56	* @{
57	*/
58
59	/**
60	* Construct a device instance for a VM.
61	*
62	* @returns VBox status.
63	* @param pDevIns The device instance data. If the registration structure
64	* is needed, it can be accessed thru pDevIns->pReg.
65	* @param iInstance Instance number. Use this to figure out which registers
66	* and such to use. The instance number is also found in
67	* pDevIns->iInstance, but since it's likely to be
68	* frequently used PDM passes it as parameter.
69	* @param pCfg Configuration node handle for the driver. This is
70	* expected to be in high demand in the constructor and is
71	* therefore passed as an argument. When using it at other
72	* times, it can be found in pDevIns->pCfg.
73	*/
74	typedef DECLCALLBACK(int) FNPDMDEVCONSTRUCT(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
75	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
76	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
77
78	/**
79	* Destruct a device instance.
80	*
81	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
82	* resources can be freed correctly.
83	*
84	* @returns VBox status.
85	* @param pDevIns The device instance data.
86	*
87	* @remarks The device critical section is not entered. The routine may delete
88	* the critical section, so the caller cannot exit it.
89	*/
90	typedef DECLCALLBACK(int) FNPDMDEVDESTRUCT(PPDMDEVINS pDevIns);
91	/** Pointer to a FNPDMDEVDESTRUCT() function. */
92	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
93
94	/**
95	* Device relocation callback.
96	*
97	* This is called when the instance data has been relocated in raw-mode context
98	* (RC). It is also called when the RC hypervisor selects changes. The device
99	* must fixup all necessary pointers and re-query all interfaces to other RC
100	* devices and drivers.
101	*
102	* Before the RC code is executed the first time, this function will be called
103	* with a 0 delta so RC pointer calculations can be one in one place.
104	*
105	* @param pDevIns Pointer to the device instance.
106	* @param offDelta The relocation delta relative to the old location.
107	*
108	* @remarks A relocation CANNOT fail.
109	*
110	* @remarks The device critical section is not entered. The relocations should
111	* not normally require any locking.
112	*/
113	typedef DECLCALLBACK(void) FNPDMDEVRELOCATE(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
114	/** Pointer to a FNPDMDEVRELOCATE() function. */
115	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
116
117	/**
118	* Power On notification.
119	*
120	* @returns VBox status.
121	* @param pDevIns The device instance data.
122	*
123	* @remarks Caller enters the device critical section.
124	*/
125	typedef DECLCALLBACK(void) FNPDMDEVPOWERON(PPDMDEVINS pDevIns);
126	/** Pointer to a FNPDMDEVPOWERON() function. */
127	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
128
129	/**
130	* Reset notification.
131	*
132	* @returns VBox status.
133	* @param pDevIns The device instance data.
134	*
135	* @remarks Caller enters the device critical section.
136	*/
137	typedef DECLCALLBACK(void) FNPDMDEVRESET(PPDMDEVINS pDevIns);
138	/** Pointer to a FNPDMDEVRESET() function. */
139	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
140
141	/**
142	* Soft reset notification.
143	*
144	* This is mainly for emulating the 286 style protected mode exits, in which
145	* most devices should remain in their current state.
146	*
147	* @returns VBox status.
148	* @param pDevIns The device instance data.
149	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
150	*
151	* @remarks Caller enters the device critical section.
152	*/
153	typedef DECLCALLBACK(void) FNPDMDEVSOFTRESET(PPDMDEVINS pDevIns, uint32_t fFlags);
154	/** Pointer to a FNPDMDEVSOFTRESET() function. */
155	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
156
157	/** @name PDMVMRESET_F_XXX - VM reset flags.
158	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
159	* reset via PDMDevHlpVMReset.
160	* @{ */
161	/** Unknown reason. */
162	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
163	/** GIM triggered reset. */
164	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
165	/** The last source always causing hard resets. */
166	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
167	/** ACPI triggered reset. */
168	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
169	/** PS/2 system port A (92h) reset. */
170	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
171	/** Keyboard reset. */
172	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
173	/** Tripple fault. */
174	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
175	/** Reset source mask. */
176	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
177	/** @} */
178
179	/**
180	* Suspend notification.
181	*
182	* @returns VBox status.
183	* @param pDevIns The device instance data.
184	* @thread EMT(0)
185	*
186	* @remarks Caller enters the device critical section.
187	*/
188	typedef DECLCALLBACK(void) FNPDMDEVSUSPEND(PPDMDEVINS pDevIns);
189	/** Pointer to a FNPDMDEVSUSPEND() function. */
190	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
191
192	/**
193	* Resume notification.
194	*
195	* @returns VBox status.
196	* @param pDevIns The device instance data.
197	*
198	* @remarks Caller enters the device critical section.
199	*/
200	typedef DECLCALLBACK(void) FNPDMDEVRESUME(PPDMDEVINS pDevIns);
201	/** Pointer to a FNPDMDEVRESUME() function. */
202	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
203
204	/**
205	* Power Off notification.
206	*
207	* This is always called when VMR3PowerOff is called.
208	* There will be no callback when hot plugging devices.
209	*
210	* @param pDevIns The device instance data.
211	* @thread EMT(0)
212	*
213	* @remarks Caller enters the device critical section.
214	*/
215	typedef DECLCALLBACK(void) FNPDMDEVPOWEROFF(PPDMDEVINS pDevIns);
216	/** Pointer to a FNPDMDEVPOWEROFF() function. */
217	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
218
219	/**
220	* Attach command.
221	*
222	* This is called to let the device attach to a driver for a specified LUN
223	* at runtime. This is not called during VM construction, the device
224	* constructor has to attach to all the available drivers.
225	*
226	* This is like plugging in the keyboard or mouse after turning on the PC.
227	*
228	* @returns VBox status code.
229	* @param pDevIns The device instance.
230	* @param iLUN The logical unit which is being attached.
231	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
232	*
233	* @remarks Caller enters the device critical section.
234	*/
235	typedef DECLCALLBACK(int) FNPDMDEVATTACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
236	/** Pointer to a FNPDMDEVATTACH() function. */
237	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
238
239	/**
240	* Detach notification.
241	*
242	* This is called when a driver is detaching itself from a LUN of the device.
243	* The device should adjust its state to reflect this.
244	*
245	* This is like unplugging the network cable to use it for the laptop or
246	* something while the PC is still running.
247	*
248	* @param pDevIns The device instance.
249	* @param iLUN The logical unit which is being detached.
250	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
251	*
252	* @remarks Caller enters the device critical section.
253	*/
254	typedef DECLCALLBACK(void) FNPDMDEVDETACH(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags);
255	/** Pointer to a FNPDMDEVDETACH() function. */
256	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
257
258	/**
259	* Query the base interface of a logical unit.
260	*
261	* @returns VBOX status code.
262	* @param pDevIns The device instance.
263	* @param iLUN The logicial unit to query.
264	* @param ppBase Where to store the pointer to the base interface of the LUN.
265	*
266	* @remarks The device critical section is not entered.
267	*/
268	typedef DECLCALLBACK(int) FNPDMDEVQUERYINTERFACE(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase);
269	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
270	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
271
272	/**
273	* Init complete notification (after ring-0 & RC init since 5.1).
274	*
275	* This can be done to do communication with other devices and other
276	* initialization which requires everything to be in place.
277	*
278	* @returns VBOX status code.
279	* @param pDevIns The device instance.
280	*
281	* @remarks Caller enters the device critical section.
282	*/
283	typedef DECLCALLBACK(int) FNPDMDEVINITCOMPLETE(PPDMDEVINS pDevIns);
284	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
285	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
286
287
288	/**
289	* The context of a pfnMemSetup call.
290	*/
291	typedef enum PDMDEVMEMSETUPCTX
292	{
293	/** Invalid zero value. */
294	PDMDEVMEMSETUPCTX_INVALID = 0,
295	/** After construction. */
296	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
297	/** After reset. */
298	PDMDEVMEMSETUPCTX_AFTER_RESET,
299	/** Type size hack. */
300	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
301	} PDMDEVMEMSETUPCTX;
302
303
304	/**
305	* PDM Device Registration Structure.
306	*
307	* This structure is used when registering a device from VBoxInitDevices() in HC
308	* Ring-3. PDM will continue use till the VM is terminated.
309	*
310	* @note The first part is the same in every context.
311	*/
312	typedef struct PDMDEVREGR3
313	{
314	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
315	uint32_t u32Version;
316	/** Reserved, must be zero. */
317	uint32_t uReserved0;
318	/** Device name, must match the ring-3 one. */
319	char szName[32];
320	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
321	uint32_t fFlags;
322	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
323	uint32_t fClass;
324	/** Maximum number of instances (per VM). */
325	uint32_t cMaxInstances;
326	/** The shared data structure version number. */
327	uint32_t uSharedVersion;
328	/** Size of the instance data. */
329	uint32_t cbInstanceShared;
330	/** Size of the ring-0 instance data. */
331	uint32_t cbInstanceCC;
332	/** Size of the raw-mode instance data. */
333	uint32_t cbInstanceRC;
334	/** Max number of PCI devices. */
335	uint16_t cMaxPciDevices;
336	/** Max number of MSI-X vectors in any of the PCI devices. */
337	uint16_t cMaxMsixVectors;
338	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
339	* remain unchanged from registration till VM destruction. */
340	const char *pszDescription;
341
342	/** Name of the raw-mode context module (no path).
343	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
344	const char *pszRCMod;
345	/** Name of the ring-0 module (no path).
346	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
347	const char *pszR0Mod;
348
349	/** Construct instance - required. */
350	PFNPDMDEVCONSTRUCT pfnConstruct;
351	/** Destruct instance - optional.
352	* Critical section NOT entered (will be destroyed). */
353	PFNPDMDEVDESTRUCT pfnDestruct;
354	/** Relocation command - optional.
355	* Critical section NOT entered. */
356	PFNPDMDEVRELOCATE pfnRelocate;
357	/**
358	* Memory setup callback.
359	*
360	* @param pDevIns The device instance data.
361	* @param enmCtx Indicates the context of the call.
362	* @remarks The critical section is entered prior to calling this method.
363	*/
364	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
365	/** Power on notification - optional.
366	* Critical section is entered. */
367	PFNPDMDEVPOWERON pfnPowerOn;
368	/** Reset notification - optional.
369	* Critical section is entered. */
370	PFNPDMDEVRESET pfnReset;
371	/** Suspend notification - optional.
372	* Critical section is entered. */
373	PFNPDMDEVSUSPEND pfnSuspend;
374	/** Resume notification - optional.
375	* Critical section is entered. */
376	PFNPDMDEVRESUME pfnResume;
377	/** Attach command - optional.
378	* Critical section is entered. */
379	PFNPDMDEVATTACH pfnAttach;
380	/** Detach notification - optional.
381	* Critical section is entered. */
382	PFNPDMDEVDETACH pfnDetach;
383	/** Query a LUN base interface - optional.
384	* Critical section is NOT entered. */
385	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
386	/** Init complete notification - optional.
387	* Critical section is entered. */
388	PFNPDMDEVINITCOMPLETE pfnInitComplete;
389	/** Power off notification - optional.
390	* Critical section is entered. */
391	PFNPDMDEVPOWEROFF pfnPowerOff;
392	/** Software system reset notification - optional.
393	* Critical section is entered. */
394	PFNPDMDEVSOFTRESET pfnSoftReset;
395
396	/** @name Reserved for future extensions, must be zero.
397	* @{ */
398	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
399	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
400	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
401	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
402	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
403	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
406	/** @} */
407
408	/** Initialization safty marker. */
409	uint32_t u32VersionEnd;
410	} PDMDEVREGR3;
411	/** Pointer to a PDM Device Structure. */
412	typedef PDMDEVREGR3 *PPDMDEVREGR3;
413	/** Const pointer to a PDM Device Structure. */
414	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
415	/** Current DEVREGR3 version number. */
416	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
417
418
419	/** PDM Device Flags.
420	* @{ */
421	/** This flag is used to indicate that the device has a R0 component. */
422	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
423	/** Requires the ring-0 component, ignore configuration values. */
424	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
425	/** Requires the ring-0 component, ignore configuration values. */
426	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
427
428	/** This flag is used to indicate that the device has a RC component. */
429	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
430	/** Requires the raw-mode component, ignore configuration values. */
431	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
432	/** Requires the raw-mode component, ignore configuration values. */
433	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
434
435	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
436	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
437
438	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
439	* The bit count for the current host.
440	* @note Superfluous, but still around for hysterical raisins. */
441	#if HC_ARCH_BITS == 32
442	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
443	#elif HC_ARCH_BITS == 64
444	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
445	#else
446	# error Unsupported HC_ARCH_BITS value.
447	#endif
448	/** The host bit count mask. */
449	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
450
451	/** The device support only 32-bit guests. */
452	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
453	/** The device support only 64-bit guests. */
454	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
455	/** The device support both 32-bit & 64-bit guests. */
456	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
457	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
458	* The guest bit count for the current compilation. */
459	#if GC_ARCH_BITS == 32
460	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
461	#elif GC_ARCH_BITS == 64
462	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
463	#else
464	# error Unsupported GC_ARCH_BITS value.
465	#endif
466	/** The guest bit count mask. */
467	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
468
469	/** A convenience. */
470	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
471
472	/** Indicates that the device needs to be notified before the drivers when suspending. */
473	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
474	/** Indicates that the device needs to be notified before the drivers when powering off. */
475	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
476	/** Indicates that the device needs to be notified before the drivers when resetting. */
477	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
478
479	/** This flag is used to indicate that the device has been converted to the
480	* new device style. */
481	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
482
483	/** @} */
484
485
486	/** PDM Device Classes.
487	* The order is important, lower bit earlier instantiation.
488	* @{ */
489	/** Architecture device. */
490	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
491	/** Architecture BIOS device. */
492	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
493	/** PCI bus brigde. */
494	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
495	/** ISA bus brigde. */
496	#define PDM_DEVREG_CLASS_BUS_ISA RT_BIT(3)
497	/** Input device (mouse, keyboard, joystick, HID, ...). */
498	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
499	/** Interrupt controller (PIC). */
500	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
501	/** Interval controoler (PIT). */
502	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
503	/** RTC/CMOS. */
504	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
505	/** DMA controller. */
506	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
507	/** VMM Device. */
508	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
509	/** Graphics device, like VGA. */
510	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
511	/** Storage controller device. */
512	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
513	/** Network interface controller. */
514	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
515	/** Audio. */
516	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
517	/** USB HIC. */
518	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
519	/** ACPI. */
520	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
521	/** Serial controller device. */
522	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
523	/** Parallel controller device */
524	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
525	/** Host PCI pass-through device */
526	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
527	/** Misc devices (always last). */
528	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
529	/** @} */
530
531
532	/**
533	* PDM Device Registration Structure, ring-0.
534	*
535	* This structure is used when registering a device from VBoxInitDevices() in HC
536	* Ring-0. PDM will continue use till the VM is terminated.
537	*/
538	typedef struct PDMDEVREGR0
539	{
540	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
541	uint32_t u32Version;
542	/** Reserved, must be zero. */
543	uint32_t uReserved0;
544	/** Device name, must match the ring-3 one. */
545	char szName[32];
546	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
547	uint32_t fFlags;
548	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
549	uint32_t fClass;
550	/** Maximum number of instances (per VM). */
551	uint32_t cMaxInstances;
552	/** The shared data structure version number. */
553	uint32_t uSharedVersion;
554	/** Size of the instance data. */
555	uint32_t cbInstanceShared;
556	/** Size of the ring-0 instance data. */
557	uint32_t cbInstanceCC;
558	/** Size of the raw-mode instance data. */
559	uint32_t cbInstanceRC;
560	/** Max number of PCI devices. */
561	uint16_t cMaxPciDevices;
562	/** Max number of MSI-X vectors in any of the PCI devices. */
563	uint16_t cMaxMsixVectors;
564	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
565	* remain unchanged from registration till VM destruction. */
566	const char *pszDescription;
567
568	/**
569	* Early construction callback (optional).
570	*
571	* This is called right after the device instance structure has been allocated
572	* and before the ring-3 constructor gets called.
573	*
574	* @returns VBox status code.
575	* @param pDevIns The device instance data.
576	* @note The destructure is always called, regardless of the return status.
577	*/
578	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
579
580	/**
581	* Regular construction callback (optional).
582	*
583	* This is called after (or during) the ring-3 constructor.
584	*
585	* @returns VBox status code.
586	* @param pDevIns The device instance data.
587	* @note The destructure is always called, regardless of the return status.
588	*/
589	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
590
591	/**
592	* Destructor (optional).
593	*
594	* This is called after the ring-3 destruction. This is not called if ring-3
595	* fails to trigger it (e.g. process is killed or crashes).
596	*
597	* @param pDevIns The device instance data.
598	*/
599	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
600
601	/**
602	* Final destructor (optional).
603	*
604	* This is called right before the memory is freed, which happens when the
605	* VM/GVM object is destroyed. This is always called.
606	*
607	* @param pDevIns The device instance data.
608	*/
609	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
610
611	/**
612	* Generic request handler (optional).
613	*
614	* @param pDevIns The device instance data.
615	* @param uReq Device specific request.
616	* @param uArg Request argument.
617	*/
618	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
619
620	/** @name Reserved for future extensions, must be zero.
621	* @{ */
622	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
623	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
624	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
625	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
626	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
627	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
630	/** @} */
631
632	/** Initialization safty marker. */
633	uint32_t u32VersionEnd;
634	} PDMDEVREGR0;
635	/** Pointer to a ring-0 PDM device registration structure. */
636	typedef PDMDEVREGR0 *PPDMDEVREGR0;
637	/** Pointer to a const ring-0 PDM device registration structure. */
638	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
639	/** Current DEVREGR0 version number. */
640	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
641
642
643	/**
644	* PDM Device Registration Structure, raw-mode
645	*
646	* At the moment, this structure is mostly here to match the other two contexts.
647	*/
648	typedef struct PDMDEVREGRC
649	{
650	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
651	uint32_t u32Version;
652	/** Reserved, must be zero. */
653	uint32_t uReserved0;
654	/** Device name, must match the ring-3 one. */
655	char szName[32];
656	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
657	uint32_t fFlags;
658	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
659	uint32_t fClass;
660	/** Maximum number of instances (per VM). */
661	uint32_t cMaxInstances;
662	/** The shared data structure version number. */
663	uint32_t uSharedVersion;
664	/** Size of the instance data. */
665	uint32_t cbInstanceShared;
666	/** Size of the ring-0 instance data. */
667	uint32_t cbInstanceCC;
668	/** Size of the raw-mode instance data. */
669	uint32_t cbInstanceRC;
670	/** Max number of PCI devices. */
671	uint16_t cMaxPciDevices;
672	/** Max number of MSI-X vectors in any of the PCI devices. */
673	uint16_t cMaxMsixVectors;
674	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
675	* remain unchanged from registration till VM destruction. */
676	const char *pszDescription;
677
678	/**
679	* Constructor callback.
680	*
681	* This is called much later than both the ring-0 and ring-3 constructors, since
682	* raw-mode v2 require a working VMM to run actual code.
683	*
684	* @returns VBox status code.
685	* @param pDevIns The device instance data.
686	* @note The destructure is always called, regardless of the return status.
687	*/
688	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
689
690	/** @name Reserved for future extensions, must be zero.
691	* @{ */
692	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
693	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
694	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
695	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
696	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
697	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
700	/** @} */
701
702	/** Initialization safty marker. */
703	uint32_t u32VersionEnd;
704	} PDMDEVREGRC;
705	/** Pointer to a raw-mode PDM device registration structure. */
706	typedef PDMDEVREGRC *PPDMDEVREGRC;
707	/** Pointer to a const raw-mode PDM device registration structure. */
708	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
709	/** Current DEVREGRC version number. */
710	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
711
712
713
714	/** @def PDM_DEVREG_VERSION
715	* Current DEVREG version number. */
716	/** @typedef PDMDEVREGR3
717	* A current context PDM device registration structure. */
718	/** @typedef PPDMDEVREGR3
719	* Pointer to a current context PDM device registration structure. */
720	/** @typedef PCPDMDEVREGR3
721	* Pointer to a const current context PDM device registration structure. */
722	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
723	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
724	typedef PDMDEVREGR3 PDMDEVREG;
725	typedef PPDMDEVREGR3 PPDMDEVREG;
726	typedef PCPDMDEVREGR3 PCPDMDEVREG;
727	#elif defined(IN_RING0)
728	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
729	typedef PDMDEVREGR0 PDMDEVREG;
730	typedef PPDMDEVREGR0 PPDMDEVREG;
731	typedef PCPDMDEVREGR0 PCPDMDEVREG;
732	#elif defined(IN_RC)
733	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
734	typedef PDMDEVREGRC PDMDEVREG;
735	typedef PPDMDEVREGRC PPDMDEVREG;
736	typedef PCPDMDEVREGRC PCPDMDEVREG;
737	#else
738	# error "Not IN_RING3, IN_RING0 or IN_RC"
739	#endif
740
741
742	/**
743	* Device registrations for ring-0 modules.
744	*
745	* This structure is used directly and must therefore reside in persistent
746	* memory (i.e. the data section).
747	*/
748	typedef struct PDMDEVMODREGR0
749	{
750	/** The structure version (PDM_DEVMODREGR0_VERSION). */
751	uint32_t u32Version;
752	/** Number of devices in the array papDevRegs points to. */
753	uint32_t cDevRegs;
754	/** Pointer to device registration structures. */
755	PCPDMDEVREGR0 *papDevRegs;
756	/** The ring-0 module handle - PDM internal, fingers off. */
757	void *hMod;
758	/** List entry - PDM internal, fingers off. */
759	RTLISTNODE ListEntry;
760	} PDMDEVMODREGR0;
761	/** Pointer to device registriations for a ring-0 module. */
762	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
763	/** Current PDMDEVMODREGR0 version number. */
764	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
765
766
767	/** @name IRQ Level for use with the *SetIrq APIs.
768	* @{
769	*/
770	/** Assert the IRQ (can assume value 1). */
771	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
772	/** Deassert the IRQ (can assume value 0). */
773	#define PDM_IRQ_LEVEL_LOW 0
774	/** flip-flop - deassert and then assert the IRQ again immediately. */
775	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
776	/** @} */
777
778	/**
779	* Registration record for MSI/MSI-X emulation.
780	*/
781	typedef struct PDMMSIREG
782	{
783	/** Number of MSI interrupt vectors, 0 if MSI not supported */
784	uint16_t cMsiVectors;
785	/** Offset of MSI capability */
786	uint8_t iMsiCapOffset;
787	/** Offset of next capability to MSI */
788	uint8_t iMsiNextOffset;
789	/** If we support 64-bit MSI addressing */
790	bool fMsi64bit;
791	/** If we do not support per-vector masking */
792	bool fMsiNoMasking;
793
794	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
795	uint16_t cMsixVectors;
796	/** Offset of MSI-X capability */
797	uint8_t iMsixCapOffset;
798	/** Offset of next capability to MSI-X */
799	uint8_t iMsixNextOffset;
800	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
801	uint8_t iMsixBar;
802	} PDMMSIREG;
803	typedef PDMMSIREG *PPDMMSIREG;
804
805	/**
806	* PCI Bus registration structure.
807	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
808	*/
809	typedef struct PDMPCIBUSREGR3
810	{
811	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
812	uint32_t u32Version;
813
814	/**
815	* Registers the device with the default PCI bus.
816	*
817	* @returns VBox status code.
818	* @param pDevIns Device instance of the PCI Bus.
819	* @param pPciDev The PCI device structure.
820	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
821	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
822	* device number (0-31).
823	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
824	* function number (0-7).
825	* @param pszName Device name (static but not unique).
826	*
827	* @remarks Caller enters the PDM critical section.
828	*/
829	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
830	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
831
832	/**
833	* Initialize MSI or MSI-X emulation support in a PCI device.
834	*
835	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
836	* vast majority of device emulation it covers everything necessary. It's
837	* fully automatic, taking care of all BAR and config space requirements,
838	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
839	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
840	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
841	*
842	* A device not using this can still offer MSI/MSI-X. In this case it's
843	* completely up to the device (in the MSI-X case) to create/register the
844	* necessary MMIO BAR, handle all config space/BAR updating and take care
845	* of delivering the interrupts appropriately.
846	*
847	* @returns VBox status code.
848	* @param pDevIns Device instance of the PCI Bus.
849	* @param pPciDev The PCI device structure.
850	* @param pMsiReg MSI emulation registration structure
851	* @remarks Caller enters the PDM critical section.
852	*/
853	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
854
855	/**
856	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
857	*
858	* @returns VBox status code.
859	* @param pDevIns Device instance of the PCI Bus.
860	* @param pPciDev The PCI device structure.
861	* @param iRegion The region number.
862	* @param cbRegion Size of the region.
863	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
864	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
865	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
866	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
867	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
868	* @a fFlags, UINT64_MAX if no handle is passed
869	* (old style).
870	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
871	* is given.
872	* @remarks Caller enters the PDM critical section.
873	*/
874	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
875	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
876	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
877
878	/**
879	* Register PCI configuration space read/write intercept callbacks.
880	*
881	* @param pDevIns Device instance of the PCI Bus.
882	* @param pPciDev The PCI device structure.
883	* @param pfnRead Pointer to the user defined PCI config read function.
884	* @param pfnWrite Pointer to the user defined PCI config write function.
885	* to call default PCI config write function. Can be NULL.
886	* @remarks Caller enters the PDM critical section.
887	* @thread EMT
888	*/
889	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
890	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
891
892	/**
893	* Perform a PCI configuration space write, bypassing interception.
894	*
895	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
896	*
897	* @returns Strict VBox status code (mainly DBGFSTOP).
898	* @param pDevIns Device instance of the PCI Bus.
899	* @param pPciDev The PCI device which config space is being read.
900	* @param uAddress The config space address.
901	* @param cb The size of the read: 1, 2 or 4 bytes.
902	* @param u32Value The value to write.
903	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
904	* that the (root) bus will have done that already.
905	*/
906	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
907	uint32_t uAddress, unsigned cb, uint32_t u32Value));
908
909	/**
910	* Perform a PCI configuration space read, bypassing interception.
911	*
912	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
913	*
914	* @returns Strict VBox status code (mainly DBGFSTOP).
915	* @param pDevIns Device instance of the PCI Bus.
916	* @param pPciDev The PCI device which config space is being read.
917	* @param uAddress The config space address.
918	* @param cb The size of the read: 1, 2 or 4 bytes.
919	* @param pu32Value Where to return the value.
920	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
921	* that the (root) bus will have done that already.
922	*/
923	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
924	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
925
926	/**
927	* Set the IRQ for a PCI device.
928	*
929	* @param pDevIns Device instance of the PCI Bus.
930	* @param pPciDev The PCI device structure.
931	* @param iIrq IRQ number to set.
932	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
933	* @param uTagSrc The IRQ tag and source (for tracing).
934	* @remarks Caller enters the PDM critical section.
935	*/
936	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
937
938	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
939	uint32_t u32EndVersion;
940	} PDMPCIBUSREGR3;
941	/** Pointer to a PCI bus registration structure. */
942	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
943	/** Current PDMPCIBUSREGR3 version number. */
944	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
945
946	/**
947	* PCI Bus registration structure for ring-0.
948	*/
949	typedef struct PDMPCIBUSREGR0
950	{
951	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
952	uint32_t u32Version;
953	/** The PCI bus number (from ring-3 registration). */
954	uint32_t iBus;
955	/**
956	* Set the IRQ for a PCI device.
957	*
958	* @param pDevIns Device instance of the PCI Bus.
959	* @param pPciDev The PCI device structure.
960	* @param iIrq IRQ number to set.
961	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
962	* @param uTagSrc The IRQ tag and source (for tracing).
963	* @remarks Caller enters the PDM critical section.
964	*/
965	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
966	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
967	uint32_t u32EndVersion;
968	} PDMPCIBUSREGR0;
969	/** Pointer to a PCI bus ring-0 registration structure. */
970	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
971	/** Current PDMPCIBUSREGR0 version number. */
972	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
973
974	/**
975	* PCI Bus registration structure for raw-mode.
976	*/
977	typedef struct PDMPCIBUSREGRC
978	{
979	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
980	uint32_t u32Version;
981	/** The PCI bus number (from ring-3 registration). */
982	uint32_t iBus;
983	/**
984	* Set the IRQ for a PCI device.
985	*
986	* @param pDevIns Device instance of the PCI Bus.
987	* @param pPciDev The PCI device structure.
988	* @param iIrq IRQ number to set.
989	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
990	* @param uTagSrc The IRQ tag and source (for tracing).
991	* @remarks Caller enters the PDM critical section.
992	*/
993	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
994	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
995	uint32_t u32EndVersion;
996	} PDMPCIBUSREGRC;
997	/** Pointer to a PCI bus raw-mode registration structure. */
998	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
999	/** Current PDMPCIBUSREGRC version number. */
1000	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1001
1002	/** PCI bus registration structure for the current context. */
1003	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1004	/** Pointer to a PCI bus registration structure for the current context. */
1005	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1006	/** PCI bus registration structure version for the current context. */
1007	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1008
1009
1010	/**
1011	* PCI Bus RC helpers.
1012	*/
1013	typedef struct PDMPCIHLPRC
1014	{
1015	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1016	uint32_t u32Version;
1017
1018	/**
1019	* Set an ISA IRQ.
1020	*
1021	* @param pDevIns PCI device instance.
1022	* @param iIrq IRQ number to set.
1023	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1024	* @param uTagSrc The IRQ tag and source (for tracing).
1025	* @thread EMT only.
1026	*/
1027	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1028
1029	/**
1030	* Set an I/O-APIC IRQ.
1031	*
1032	* @param pDevIns PCI device instance.
1033	* @param iIrq IRQ number to set.
1034	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1035	* @param uTagSrc The IRQ tag and source (for tracing).
1036	* @thread EMT only.
1037	*/
1038	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1039
1040	/**
1041	* Send an MSI.
1042	*
1043	* @param pDevIns PCI device instance.
1044	* @param GCPhys Physical address MSI request was written.
1045	* @param uValue Value written.
1046	* @param uTagSrc The IRQ tag and source (for tracing).
1047	* @thread EMT only.
1048	*/
1049	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1050
1051
1052	/**
1053	* Acquires the PDM lock.
1054	*
1055	* @returns VINF_SUCCESS on success.
1056	* @returns rc if we failed to acquire the lock.
1057	* @param pDevIns The PCI device instance.
1058	* @param rc What to return if we fail to acquire the lock.
1059	*/
1060	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1061
1062	/**
1063	* Releases the PDM lock.
1064	*
1065	* @param pDevIns The PCI device instance.
1066	*/
1067	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1068
1069	/**
1070	* Gets a bus by it's PDM ordinal (typically the parent bus).
1071	*
1072	* @returns Pointer to the device instance of the bus.
1073	* @param pDevIns The PCI bus device instance.
1074	* @param idxPdmBus The PDM ordinal value of the bus to get.
1075	*/
1076	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1077
1078	/** Just a safety precaution. */
1079	uint32_t u32TheEnd;
1080	} PDMPCIHLPRC;
1081	/** Pointer to PCI helpers. */
1082	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1083	/** Pointer to const PCI helpers. */
1084	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1085
1086	/** Current PDMPCIHLPRC version number. */
1087	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 3, 0)
1088
1089
1090	/**
1091	* PCI Bus R0 helpers.
1092	*/
1093	typedef struct PDMPCIHLPR0
1094	{
1095	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1096	uint32_t u32Version;
1097
1098	/**
1099	* Set an ISA IRQ.
1100	*
1101	* @param pDevIns PCI device instance.
1102	* @param iIrq IRQ number to set.
1103	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1104	* @param uTagSrc The IRQ tag and source (for tracing).
1105	* @thread EMT only.
1106	*/
1107	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1108
1109	/**
1110	* Set an I/O-APIC IRQ.
1111	*
1112	* @param pDevIns PCI device instance.
1113	* @param iIrq IRQ number to set.
1114	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1115	* @param uTagSrc The IRQ tag and source (for tracing).
1116	* @thread EMT only.
1117	*/
1118	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1119
1120	/**
1121	* Send an MSI.
1122	*
1123	* @param pDevIns PCI device instance.
1124	* @param GCPhys Physical address MSI request was written.
1125	* @param uValue Value written.
1126	* @param uTagSrc The IRQ tag and source (for tracing).
1127	* @thread EMT only.
1128	*/
1129	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1130
1131	/**
1132	* Acquires the PDM lock.
1133	*
1134	* @returns VINF_SUCCESS on success.
1135	* @returns rc if we failed to acquire the lock.
1136	* @param pDevIns The PCI device instance.
1137	* @param rc What to return if we fail to acquire the lock.
1138	*/
1139	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1140
1141	/**
1142	* Releases the PDM lock.
1143	*
1144	* @param pDevIns The PCI device instance.
1145	*/
1146	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1147
1148	/**
1149	* Gets a bus by it's PDM ordinal (typically the parent bus).
1150	*
1151	* @returns Pointer to the device instance of the bus.
1152	* @param pDevIns The PCI bus device instance.
1153	* @param idxPdmBus The PDM ordinal value of the bus to get.
1154	*/
1155	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1156
1157	/** Just a safety precaution. */
1158	uint32_t u32TheEnd;
1159	} PDMPCIHLPR0;
1160	/** Pointer to PCI helpers. */
1161	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1162	/** Pointer to const PCI helpers. */
1163	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1164
1165	/** Current PDMPCIHLPR0 version number. */
1166	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 4, 0)
1167
1168	/**
1169	* PCI device helpers.
1170	*/
1171	typedef struct PDMPCIHLPR3
1172	{
1173	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1174	uint32_t u32Version;
1175
1176	/**
1177	* Set an ISA IRQ.
1178	*
1179	* @param pDevIns The PCI device instance.
1180	* @param iIrq IRQ number to set.
1181	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1182	* @param uTagSrc The IRQ tag and source (for tracing).
1183	*/
1184	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1185
1186	/**
1187	* Set an I/O-APIC IRQ.
1188	*
1189	* @param pDevIns The PCI device instance.
1190	* @param iIrq IRQ number to set.
1191	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1192	* @param uTagSrc The IRQ tag and source (for tracing).
1193	*/
1194	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1195
1196	/**
1197	* Send an MSI.
1198	*
1199	* @param pDevIns PCI device instance.
1200	* @param GCPhys Physical address MSI request was written.
1201	* @param uValue Value written.
1202	* @param uTagSrc The IRQ tag and source (for tracing).
1203	*/
1204	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1205
1206	/**
1207	* Checks if the given address is an MMIO2 or pre-registered MMIO base address.
1208	*
1209	* @returns true/false accordingly.
1210	* @param pDevIns The PCI device instance.
1211	* @param pOwner The owner of the memory, optional.
1212	* @param GCPhys The address to check.
1213	* @sa PGMR3PhysMMIOExIsBase
1214	*/
1215	DECLR3CALLBACKMEMBER(bool, pfnIsMMIOExBase,(PPDMDEVINS pDevIns, PPDMDEVINS pOwner, RTGCPHYS GCPhys));
1216
1217	/**
1218	* Acquires the PDM lock.
1219	*
1220	* @returns VINF_SUCCESS on success.
1221	* @returns Fatal error on failure.
1222	* @param pDevIns The PCI device instance.
1223	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1224	*/
1225	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1226
1227	/**
1228	* Releases the PDM lock.
1229	*
1230	* @param pDevIns The PCI device instance.
1231	*/
1232	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1233
1234	/**
1235	* Gets a bus by it's PDM ordinal (typically the parent bus).
1236	*
1237	* @returns Pointer to the device instance of the bus.
1238	* @param pDevIns The PCI bus device instance.
1239	* @param idxPdmBus The PDM ordinal value of the bus to get.
1240	*/
1241	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1242
1243	/** Just a safety precaution. */
1244	uint32_t u32TheEnd;
1245	} PDMPCIHLPR3;
1246	/** Pointer to PCI helpers. */
1247	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1248	/** Pointer to const PCI helpers. */
1249	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1250
1251	/** Current PDMPCIHLPR3 version number. */
1252	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 4, 0)
1253
1254
1255	/**
1256	* Programmable Interrupt Controller registration structure.
1257	*/
1258	typedef struct PDMPICREG
1259	{
1260	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1261	uint32_t u32Version;
1262
1263	/**
1264	* Set the an IRQ.
1265	*
1266	* @param pDevIns Device instance of the PIC.
1267	* @param iIrq IRQ number to set.
1268	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1269	* @param uTagSrc The IRQ tag and source (for tracing).
1270	* @remarks Caller enters the PDM critical section.
1271	*/
1272	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1273
1274	/**
1275	* Get a pending interrupt.
1276	*
1277	* @returns Pending interrupt number.
1278	* @param pDevIns Device instance of the PIC.
1279	* @param puTagSrc Where to return the IRQ tag and source.
1280	* @remarks Caller enters the PDM critical section.
1281	*/
1282	DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1283
1284	/** The name of the RC SetIrq entry point. */
1285	const char *pszSetIrqRC;
1286	/** The name of the RC GetInterrupt entry point. */
1287	const char *pszGetInterruptRC;
1288
1289	/** The name of the R0 SetIrq entry point. */
1290	const char *pszSetIrqR0;
1291	/** The name of the R0 GetInterrupt entry point. */
1292	const char *pszGetInterruptR0;
1293	} PDMPICREG;
1294	/** Pointer to a PIC registration structure. */
1295	typedef PDMPICREG *PPDMPICREG;
1296
1297	/** Current PDMPICREG version number. */
1298	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 2, 0)
1299
1300	/**
1301	* PIC RC helpers.
1302	*/
1303	typedef struct PDMPICHLPRC
1304	{
1305	/** Structure version. PDM_PICHLPRC_VERSION defines the current version. */
1306	uint32_t u32Version;
1307
1308	/**
1309	* Set the interrupt force action flag.
1310	*
1311	* @param pDevIns Device instance of the PIC.
1312	*/
1313	DECLRCCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1314
1315	/**
1316	* Clear the interrupt force action flag.
1317	*
1318	* @param pDevIns Device instance of the PIC.
1319	*/
1320	DECLRCCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1321
1322	/**
1323	* Acquires the PDM lock.
1324	*
1325	* @returns VINF_SUCCESS on success.
1326	* @returns rc if we failed to acquire the lock.
1327	* @param pDevIns The PIC device instance.
1328	* @param rc What to return if we fail to acquire the lock.
1329	*/
1330	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1331
1332	/**
1333	* Releases the PDM lock.
1334	*
1335	* @param pDevIns The PIC device instance.
1336	*/
1337	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1338
1339	/** Just a safety precaution. */
1340	uint32_t u32TheEnd;
1341	} PDMPICHLPRC;
1342
1343	/** Pointer to PIC RC helpers. */
1344	typedef RCPTRTYPE(PDMPICHLPRC *) PPDMPICHLPRC;
1345	/** Pointer to const PIC RC helpers. */
1346	typedef RCPTRTYPE(const PDMPICHLPRC *) PCPDMPICHLPRC;
1347
1348	/** Current PDMPICHLPRC version number. */
1349	#define PDM_PICHLPRC_VERSION PDM_VERSION_MAKE(0xfff9, 2, 0)
1350
1351
1352	/**
1353	* PIC R0 helpers.
1354	*/
1355	typedef struct PDMPICHLPR0
1356	{
1357	/** Structure version. PDM_PICHLPR0_VERSION defines the current version. */
1358	uint32_t u32Version;
1359
1360	/**
1361	* Set the interrupt force action flag.
1362	*
1363	* @param pDevIns Device instance of the PIC.
1364	*/
1365	DECLR0CALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1366
1367	/**
1368	* Clear the interrupt force action flag.
1369	*
1370	* @param pDevIns Device instance of the PIC.
1371	*/
1372	DECLR0CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1373
1374	/**
1375	* Acquires the PDM lock.
1376	*
1377	* @returns VINF_SUCCESS on success.
1378	* @returns rc if we failed to acquire the lock.
1379	* @param pDevIns The PIC device instance.
1380	* @param rc What to return if we fail to acquire the lock.
1381	*/
1382	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1383
1384	/**
1385	* Releases the PDM lock.
1386	*
1387	* @param pDevIns The PCI device instance.
1388	*/
1389	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1390
1391	/** Just a safety precaution. */
1392	uint32_t u32TheEnd;
1393	} PDMPICHLPR0;
1394
1395	/** Pointer to PIC R0 helpers. */
1396	typedef R0PTRTYPE(PDMPICHLPR0 *) PPDMPICHLPR0;
1397	/** Pointer to const PIC R0 helpers. */
1398	typedef R0PTRTYPE(const PDMPICHLPR0 *) PCPDMPICHLPR0;
1399
1400	/** Current PDMPICHLPR0 version number. */
1401	#define PDM_PICHLPR0_VERSION PDM_VERSION_MAKE(0xfff8, 1, 0)
1402
1403	/**
1404	* PIC R3 helpers.
1405	*/
1406	typedef struct PDMPICHLPR3
1407	{
1408	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1409	uint32_t u32Version;
1410
1411	/**
1412	* Set the interrupt force action flag.
1413	*
1414	* @param pDevIns Device instance of the PIC.
1415	*/
1416	DECLR3CALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1417
1418	/**
1419	* Clear the interrupt force action flag.
1420	*
1421	* @param pDevIns Device instance of the PIC.
1422	*/
1423	DECLR3CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1424
1425	/**
1426	* Acquires the PDM lock.
1427	*
1428	* @returns VINF_SUCCESS on success.
1429	* @returns Fatal error on failure.
1430	* @param pDevIns The PIC device instance.
1431	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1432	*/
1433	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1434
1435	/**
1436	* Releases the PDM lock.
1437	*
1438	* @param pDevIns The PIC device instance.
1439	*/
1440	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1441
1442	/**
1443	* Gets the address of the RC PIC helpers.
1444	*
1445	* This should be called at both construction and relocation time
1446	* to obtain the correct address of the RC helpers.
1447	*
1448	* @returns RC pointer to the PIC helpers.
1449	* @param pDevIns Device instance of the PIC.
1450	*/
1451	DECLR3CALLBACKMEMBER(PCPDMPICHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1452
1453	/**
1454	* Gets the address of the R0 PIC helpers.
1455	*
1456	* This should be called at both construction and relocation time
1457	* to obtain the correct address of the R0 helpers.
1458	*
1459	* @returns R0 pointer to the PIC helpers.
1460	* @param pDevIns Device instance of the PIC.
1461	*/
1462	DECLR3CALLBACKMEMBER(PCPDMPICHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1463
1464	/** Just a safety precaution. */
1465	uint32_t u32TheEnd;
1466	} PDMPICHLPR3;
1467
1468	/** Pointer to PIC R3 helpers. */
1469	typedef R3PTRTYPE(PDMPICHLPR3 *) PPDMPICHLPR3;
1470	/** Pointer to const PIC R3 helpers. */
1471	typedef R3PTRTYPE(const PDMPICHLPR3 *) PCPDMPICHLPR3;
1472
1473	/** Current PDMPICHLPR3 version number. */
1474	#define PDM_PICHLPR3_VERSION PDM_VERSION_MAKE(0xfff7, 1, 0)
1475
1476
1477
1478	/**
1479	* Firmware registration structure.
1480	*/
1481	typedef struct PDMFWREG
1482	{
1483	/** Struct version+magic number (PDM_FWREG_VERSION). */
1484	uint32_t u32Version;
1485
1486	/**
1487	* Checks whether this is a hard or soft reset.
1488	*
1489	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1490	* is 5, 9 or 0xA.
1491	*
1492	* @returns true if hard reset, false if soft.
1493	* @param pDevIns Device instance of the firmware.
1494	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1495	*/
1496	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1497
1498	/** Just a safety precaution. */
1499	uint32_t u32TheEnd;
1500	} PDMFWREG;
1501	/** Pointer to a FW registration structure. */
1502	typedef PDMFWREG *PPDMFWREG;
1503	/** Pointer to a const FW registration structure. */
1504	typedef PDMFWREG const *PCPDMFWREG;
1505
1506	/** Current PDMFWREG version number. */
1507	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1508
1509	/**
1510	* Firmware R3 helpers.
1511	*/
1512	typedef struct PDMFWHLPR3
1513	{
1514	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1515	uint32_t u32Version;
1516
1517	/** Just a safety precaution. */
1518	uint32_t u32TheEnd;
1519	} PDMFWHLPR3;
1520
1521	/** Pointer to FW R3 helpers. */
1522	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1523	/** Pointer to const FW R3 helpers. */
1524	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1525
1526	/** Current PDMFWHLPR3 version number. */
1527	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1528
1529
1530	/**
1531	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1532	*
1533	* Also used in saved-states, CFGM don't change existing values.
1534	*/
1535	typedef enum PDMAPICMODE
1536	{
1537	/** Invalid 0 entry. */
1538	PDMAPICMODE_INVALID = 0,
1539	/** No APIC. */
1540	PDMAPICMODE_NONE,
1541	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1542	PDMAPICMODE_APIC,
1543	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1544	PDMAPICMODE_X2APIC,
1545	/** The usual 32-bit paranoia. */
1546	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1547	} PDMAPICMODE;
1548
1549	/**
1550	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1551	*/
1552	typedef enum PDMAPICIRQ
1553	{
1554	/** Invalid 0 entry. */
1555	PDMAPICIRQ_INVALID = 0,
1556	/** Normal hardware interrupt. */
1557	PDMAPICIRQ_HARDWARE,
1558	/** NMI. */
1559	PDMAPICIRQ_NMI,
1560	/** SMI. */
1561	PDMAPICIRQ_SMI,
1562	/** ExtINT (HW interrupt via PIC). */
1563	PDMAPICIRQ_EXTINT,
1564	/** Interrupt arrived, needs to be updated to the IRR. */
1565	PDMAPICIRQ_UPDATE_PENDING,
1566	/** The usual 32-bit paranoia. */
1567	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1568	} PDMAPICIRQ;
1569
1570
1571	/**
1572	* I/O APIC registration structure.
1573	*/
1574	typedef struct PDMIOAPICREG
1575	{
1576	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1577	uint32_t u32Version;
1578
1579	/**
1580	* Set an IRQ.
1581	*
1582	* @param pDevIns Device instance of the I/O APIC.
1583	* @param iIrq IRQ number to set.
1584	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1585	* @param uTagSrc The IRQ tag and source (for tracing).
1586	*
1587	* @remarks Caller enters the PDM critical section
1588	* Actually, as per 2018-07-21 this isn't true (bird).
1589	*/
1590	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1591
1592	/** The name of the RC SetIrq entry point. */
1593	const char *pszSetIrqRC;
1594
1595	/** The name of the R0 SetIrq entry point. */
1596	const char *pszSetIrqR0;
1597
1598	/**
1599	* Send a MSI.
1600	*
1601	* @param pDevIns Device instance of the I/O APIC.
1602	* @param GCPhys Request address.
1603	* @param uValue Request value.
1604	* @param uTagSrc The IRQ tag and source (for tracing).
1605	*
1606	* @remarks Caller enters the PDM critical section
1607	* Actually, as per 2018-07-21 this isn't true (bird).
1608	*/
1609	DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
1610
1611	/** The name of the RC SendMsi entry point. */
1612	const char *pszSendMsiRC;
1613
1614	/** The name of the R0 SendMsi entry point. */
1615	const char *pszSendMsiR0;
1616
1617	/**
1618	* Set the EOI for an interrupt vector.
1619	*
1620	* @returns Strict VBox status code - only the following informational status codes:
1621	* @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.2
1622	* @retval VINF_SUCCESS
1623	*
1624	* @param pDevIns Device instance of the I/O APIC.
1625	* @param u8Vector The vector.
1626	*
1627	* @remarks Caller enters the PDM critical section
1628	* Actually, as per 2018-07-21 this isn't true (bird).
1629	*/
1630	DECLR3CALLBACKMEMBER(int, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1631
1632	/** The name of the RC SetEoi entry point. */
1633	const char *pszSetEoiRC;
1634
1635	/** The name of the R0 SetEoi entry point. */
1636	const char *pszSetEoiR0;
1637	} PDMIOAPICREG;
1638	/** Pointer to an APIC registration structure. */
1639	typedef PDMIOAPICREG *PPDMIOAPICREG;
1640
1641	/** Current PDMAPICREG version number. */
1642	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 5, 0)
1643
1644
1645	/**
1646	* IOAPIC RC helpers.
1647	*/
1648	typedef struct PDMIOAPICHLPRC
1649	{
1650	/** Structure version. PDM_IOAPICHLPRC_VERSION defines the current version. */
1651	uint32_t u32Version;
1652
1653	/**
1654	* Private interface between the IOAPIC and APIC.
1655	*
1656	* See comments about this hack on PDMAPICREG::pfnBusDeliverR3.
1657	*
1658	* @returns status code.
1659	* @param pDevIns Device instance of the IOAPIC.
1660	* @param u8Dest See APIC implementation.
1661	* @param u8DestMode See APIC implementation.
1662	* @param u8DeliveryMode See APIC implementation.
1663	* @param uVector See APIC implementation.
1664	* @param u8Polarity See APIC implementation.
1665	* @param u8TriggerMode See APIC implementation.
1666	* @param uTagSrc The IRQ tag and source (for tracing).
1667	*/
1668	DECLRCCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1669	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1670
1671	/**
1672	* Acquires the PDM lock.
1673	*
1674	* @returns VINF_SUCCESS on success.
1675	* @returns rc if we failed to acquire the lock.
1676	* @param pDevIns The IOAPIC device instance.
1677	* @param rc What to return if we fail to acquire the lock.
1678	*/
1679	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1680
1681	/**
1682	* Releases the PDM lock.
1683	*
1684	* @param pDevIns The IOAPIC device instance.
1685	*/
1686	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1687
1688	/** Just a safety precaution. */
1689	uint32_t u32TheEnd;
1690	} PDMIOAPICHLPRC;
1691	/** Pointer to IOAPIC RC helpers. */
1692	typedef RCPTRTYPE(PDMIOAPICHLPRC *) PPDMIOAPICHLPRC;
1693	/** Pointer to const IOAPIC helpers. */
1694	typedef RCPTRTYPE(const PDMIOAPICHLPRC *) PCPDMIOAPICHLPRC;
1695
1696	/** Current PDMIOAPICHLPRC version number. */
1697	#define PDM_IOAPICHLPRC_VERSION PDM_VERSION_MAKE(0xfff1, 2, 0)
1698
1699
1700	/**
1701	* IOAPIC R0 helpers.
1702	*/
1703	typedef struct PDMIOAPICHLPR0
1704	{
1705	/** Structure version. PDM_IOAPICHLPR0_VERSION defines the current version. */
1706	uint32_t u32Version;
1707
1708	/**
1709	* Private interface between the IOAPIC and APIC.
1710	*
1711	* See comments about this hack on PDMAPICREG::pfnBusDeliverR3.
1712	*
1713	* @returns status code.
1714	* @param pDevIns Device instance of the IOAPIC.
1715	* @param u8Dest See APIC implementation.
1716	* @param u8DestMode See APIC implementation.
1717	* @param u8DeliveryMode See APIC implementation.
1718	* @param uVector See APIC implementation.
1719	* @param u8Polarity See APIC implementation.
1720	* @param u8TriggerMode See APIC implementation.
1721	* @param uTagSrc The IRQ tag and source (for tracing).
1722	*/
1723	DECLR0CALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1724	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1725
1726	/**
1727	* Acquires the PDM lock.
1728	*
1729	* @returns VINF_SUCCESS on success.
1730	* @returns rc if we failed to acquire the lock.
1731	* @param pDevIns The IOAPIC device instance.
1732	* @param rc What to return if we fail to acquire the lock.
1733	*/
1734	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1735
1736	/**
1737	* Releases the PDM lock.
1738	*
1739	* @param pDevIns The IOAPIC device instance.
1740	*/
1741	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1742
1743	/** Just a safety precaution. */
1744	uint32_t u32TheEnd;
1745	} PDMIOAPICHLPR0;
1746	/** Pointer to IOAPIC R0 helpers. */
1747	typedef R0PTRTYPE(PDMIOAPICHLPR0 *) PPDMIOAPICHLPR0;
1748	/** Pointer to const IOAPIC helpers. */
1749	typedef R0PTRTYPE(const PDMIOAPICHLPR0 *) PCPDMIOAPICHLPR0;
1750
1751	/** Current PDMIOAPICHLPR0 version number. */
1752	#define PDM_IOAPICHLPR0_VERSION PDM_VERSION_MAKE(0xfff0, 2, 0)
1753
1754	/**
1755	* IOAPIC R3 helpers.
1756	*/
1757	typedef struct PDMIOAPICHLPR3
1758	{
1759	/** Structure version. PDM_IOAPICHLPR3_VERSION defines the current version. */
1760	uint32_t u32Version;
1761
1762	/**
1763	* Private interface between the IOAPIC and APIC.
1764	*
1765	* See comments about this hack on PDMAPICREG::pfnBusDeliverR3.
1766	*
1767	* @returns status code
1768	* @param pDevIns Device instance of the IOAPIC.
1769	* @param u8Dest See APIC implementation.
1770	* @param u8DestMode See APIC implementation.
1771	* @param u8DeliveryMode See APIC implementation.
1772	* @param uVector See APIC implementation.
1773	* @param u8Polarity See APIC implementation.
1774	* @param u8TriggerMode See APIC implementation.
1775	* @param uTagSrc The IRQ tag and source (for tracing).
1776	*/
1777	DECLR3CALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1778	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1779
1780	/**
1781	* Acquires the PDM lock.
1782	*
1783	* @returns VINF_SUCCESS on success.
1784	* @returns Fatal error on failure.
1785	* @param pDevIns The IOAPIC device instance.
1786	* @param rc Dummy for making the interface identical to the GC and R0 versions.
1787	*/
1788	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1789
1790	/**
1791	* Releases the PDM lock.
1792	*
1793	* @param pDevIns The IOAPIC device instance.
1794	*/
1795	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1796
1797	/**
1798	* Gets the address of the RC IOAPIC helpers.
1799	*
1800	* This should be called at both construction and relocation time
1801	* to obtain the correct address of the RC helpers.
1802	*
1803	* @returns RC pointer to the IOAPIC helpers.
1804	* @param pDevIns Device instance of the IOAPIC.
1805	*/
1806	DECLR3CALLBACKMEMBER(PCPDMIOAPICHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1807
1808	/**
1809	* Gets the address of the R0 IOAPIC helpers.
1810	*
1811	* This should be called at both construction and relocation time
1812	* to obtain the correct address of the R0 helpers.
1813	*
1814	* @returns R0 pointer to the IOAPIC helpers.
1815	* @param pDevIns Device instance of the IOAPIC.
1816	*/
1817	DECLR3CALLBACKMEMBER(PCPDMIOAPICHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1818
1819	/** Just a safety precaution. */
1820	uint32_t u32TheEnd;
1821	} PDMIOAPICHLPR3;
1822	/** Pointer to IOAPIC R3 helpers. */
1823	typedef R3PTRTYPE(PDMIOAPICHLPR3 *) PPDMIOAPICHLPR3;
1824	/** Pointer to const IOAPIC helpers. */
1825	typedef R3PTRTYPE(const PDMIOAPICHLPR3 *) PCPDMIOAPICHLPR3;
1826
1827	/** Current PDMIOAPICHLPR3 version number. */
1828	#define PDM_IOAPICHLPR3_VERSION PDM_VERSION_MAKE(0xffef, 2, 0)
1829
1830
1831	/**
1832	* HPET registration structure.
1833	*/
1834	typedef struct PDMHPETREG
1835	{
1836	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1837	uint32_t u32Version;
1838
1839	} PDMHPETREG;
1840	/** Pointer to an HPET registration structure. */
1841	typedef PDMHPETREG *PPDMHPETREG;
1842
1843	/** Current PDMHPETREG version number. */
1844	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1845
1846	/**
1847	* HPET RC helpers.
1848	*
1849	* @remarks Keep this around in case HPET will need PDM interaction in again RC
1850	* at some later point.
1851	*/
1852	typedef struct PDMHPETHLPRC
1853	{
1854	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1855	uint32_t u32Version;
1856
1857	/** Just a safety precaution. */
1858	uint32_t u32TheEnd;
1859	} PDMHPETHLPRC;
1860
1861	/** Pointer to HPET RC helpers. */
1862	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1863	/** Pointer to const HPET RC helpers. */
1864	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1865
1866	/** Current PDMHPETHLPRC version number. */
1867	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1868
1869
1870	/**
1871	* HPET R0 helpers.
1872	*
1873	* @remarks Keep this around in case HPET will need PDM interaction in again R0
1874	* at some later point.
1875	*/
1876	typedef struct PDMHPETHLPR0
1877	{
1878	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1879	uint32_t u32Version;
1880
1881	/** Just a safety precaution. */
1882	uint32_t u32TheEnd;
1883	} PDMHPETHLPR0;
1884
1885	/** Pointer to HPET R0 helpers. */
1886	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1887	/** Pointer to const HPET R0 helpers. */
1888	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1889
1890	/** Current PDMHPETHLPR0 version number. */
1891	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1892
1893	/**
1894	* HPET R3 helpers.
1895	*/
1896	typedef struct PDMHPETHLPR3
1897	{
1898	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1899	uint32_t u32Version;
1900
1901	/**
1902	* Gets the address of the RC HPET helpers.
1903	*
1904	* This should be called at both construction and relocation time
1905	* to obtain the correct address of the RC helpers.
1906	*
1907	* @returns RC pointer to the HPET helpers.
1908	* @param pDevIns Device instance of the HPET.
1909	*/
1910	DECLR3CALLBACKMEMBER(PCPDMHPETHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
1911
1912	/**
1913	* Gets the address of the R0 HPET helpers.
1914	*
1915	* This should be called at both construction and relocation time
1916	* to obtain the correct address of the R0 helpers.
1917	*
1918	* @returns R0 pointer to the HPET helpers.
1919	* @param pDevIns Device instance of the HPET.
1920	*/
1921	DECLR3CALLBACKMEMBER(PCPDMHPETHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
1922
1923	/**
1924	* Set legacy mode on PIT and RTC.
1925	*
1926	* @returns VINF_SUCCESS on success.
1927	* @returns rc if we failed to set legacy mode.
1928	* @param pDevIns Device instance of the HPET.
1929	* @param fActivated Whether legacy mode is activated or deactivated.
1930	*/
1931	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1932
1933
1934	/**
1935	* Set IRQ, bypassing ISA bus override rules.
1936	*
1937	* @returns VINF_SUCCESS on success.
1938	* @returns rc if we failed to set legacy mode.
1939	* @param pDevIns Device instance of the HPET.
1940	* @param iIrq IRQ number to set.
1941	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1942	*/
1943	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1944
1945	/** Just a safety precaution. */
1946	uint32_t u32TheEnd;
1947	} PDMHPETHLPR3;
1948
1949	/** Pointer to HPET R3 helpers. */
1950	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1951	/** Pointer to const HPET R3 helpers. */
1952	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1953
1954	/** Current PDMHPETHLPR3 version number. */
1955	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 2, 0)
1956
1957
1958	/**
1959	* Raw PCI device registration structure.
1960	*/
1961	typedef struct PDMPCIRAWREG
1962	{
1963	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1964	uint32_t u32Version;
1965	/** Just a safety precaution. */
1966	uint32_t u32TheEnd;
1967	} PDMPCIRAWREG;
1968	/** Pointer to a raw PCI registration structure. */
1969	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1970
1971	/** Current PDMPCIRAWREG version number. */
1972	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1973
1974	/**
1975	* Raw PCI device raw-mode context helpers.
1976	*/
1977	typedef struct PDMPCIRAWHLPRC
1978	{
1979	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1980	uint32_t u32Version;
1981	/** Just a safety precaution. */
1982	uint32_t u32TheEnd;
1983	} PDMPCIRAWHLPRC;
1984	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1985	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1986	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1987	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1988
1989	/** Current PDMPCIRAWHLPRC version number. */
1990	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1991
1992	/**
1993	* Raw PCI device ring-0 context helpers.
1994	*/
1995	typedef struct PDMPCIRAWHLPR0
1996	{
1997	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
1998	uint32_t u32Version;
1999	/** Just a safety precaution. */
2000	uint32_t u32TheEnd;
2001	} PDMPCIRAWHLPR0;
2002	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2003	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2004	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2005	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2006
2007	/** Current PDMPCIRAWHLPR0 version number. */
2008	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2009
2010
2011	/**
2012	* Raw PCI device ring-3 context helpers.
2013	*/
2014	typedef struct PDMPCIRAWHLPR3
2015	{
2016	/** Undefined structure version and magic number. */
2017	uint32_t u32Version;
2018
2019	/**
2020	* Gets the address of the RC raw PCI device helpers.
2021	*
2022	* This should be called at both construction and relocation time to obtain
2023	* the correct address of the RC helpers.
2024	*
2025	* @returns RC pointer to the raw PCI device helpers.
2026	* @param pDevIns Device instance of the raw PCI device.
2027	*/
2028	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2029
2030	/**
2031	* Gets the address of the R0 raw PCI device helpers.
2032	*
2033	* This should be called at both construction and relocation time to obtain
2034	* the correct address of the R0 helpers.
2035	*
2036	* @returns R0 pointer to the raw PCI device helpers.
2037	* @param pDevIns Device instance of the raw PCI device.
2038	*/
2039	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2040
2041	/** Just a safety precaution. */
2042	uint32_t u32TheEnd;
2043	} PDMPCIRAWHLPR3;
2044	/** Pointer to raw PCI R3 helpers. */
2045	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2046	/** Pointer to const raw PCI R3 helpers. */
2047	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2048
2049	/** Current PDMPCIRAWHLPR3 version number. */
2050	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2051
2052
2053	#ifdef IN_RING3
2054
2055	/**
2056	* DMA Transfer Handler.
2057	*
2058	* @returns Number of bytes transferred.
2059	* @param pDevIns Device instance of the DMA.
2060	* @param pvUser User pointer.
2061	* @param uChannel Channel number.
2062	* @param off DMA position.
2063	* @param cb Block size.
2064	* @remarks The device lock is not taken, however, the DMA device lock is held.
2065	*/
2066	typedef DECLCALLBACK(uint32_t) FNDMATRANSFERHANDLER(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel, uint32_t off, uint32_t cb);
2067	/** Pointer to a FNDMATRANSFERHANDLER(). */
2068	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2069
2070	/**
2071	* DMA Controller registration structure.
2072	*/
2073	typedef struct PDMDMAREG
2074	{
2075	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2076	uint32_t u32Version;
2077
2078	/**
2079	* Execute pending transfers.
2080	*
2081	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2082	* @param pDevIns Device instance of the DMAC.
2083	* @remarks No locks held, called on EMT(0) as a form of serialization.
2084	*/
2085	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2086
2087	/**
2088	* Register transfer function for DMA channel.
2089	*
2090	* @param pDevIns Device instance of the DMAC.
2091	* @param uChannel Channel number.
2092	* @param pfnTransferHandler Device specific transfer function.
2093	* @param pvUser User pointer to be passed to the callback.
2094	* @remarks No locks held, called on an EMT.
2095	*/
2096	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2097
2098	/**
2099	* Read memory
2100	*
2101	* @returns Number of bytes read.
2102	* @param pDevIns Device instance of the DMAC.
2103	* @param uChannel Channel number.
2104	* @param pvBuffer Pointer to target buffer.
2105	* @param off DMA position.
2106	* @param cbBlock Block size.
2107	* @remarks No locks held, called on an EMT.
2108	*/
2109	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2110
2111	/**
2112	* Write memory
2113	*
2114	* @returns Number of bytes written.
2115	* @param pDevIns Device instance of the DMAC.
2116	* @param uChannel Channel number.
2117	* @param pvBuffer Memory to write.
2118	* @param off DMA position.
2119	* @param cbBlock Block size.
2120	* @remarks No locks held, called on an EMT.
2121	*/
2122	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2123
2124	/**
2125	* Set the DREQ line.
2126	*
2127	* @param pDevIns Device instance of the DMAC.
2128	* @param uChannel Channel number.
2129	* @param uLevel Level of the line.
2130	* @remarks No locks held, called on an EMT.
2131	*/
2132	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2133
2134	/**
2135	* Get channel mode
2136	*
2137	* @returns Channel mode.
2138	* @param pDevIns Device instance of the DMAC.
2139	* @param uChannel Channel number.
2140	* @remarks No locks held, called on an EMT.
2141	*/
2142	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2143
2144	} PDMDMACREG;
2145	/** Pointer to a DMAC registration structure. */
2146	typedef PDMDMACREG *PPDMDMACREG;
2147
2148	/** Current PDMDMACREG version number. */
2149	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 1, 0)
2150
2151
2152	/**
2153	* DMA Controller device helpers.
2154	*/
2155	typedef struct PDMDMACHLP
2156	{
2157	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2158	uint32_t u32Version;
2159
2160	/* to-be-defined */
2161
2162	} PDMDMACHLP;
2163	/** Pointer to DMAC helpers. */
2164	typedef PDMDMACHLP *PPDMDMACHLP;
2165	/** Pointer to const DMAC helpers. */
2166	typedef const PDMDMACHLP *PCPDMDMACHLP;
2167
2168	/** Current PDMDMACHLP version number. */
2169	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2170
2171	#endif /* IN_RING3 */
2172
2173
2174
2175	/**
2176	* RTC registration structure.
2177	*/
2178	typedef struct PDMRTCREG
2179	{
2180	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2181	uint32_t u32Version;
2182	uint32_t u32Alignment; /*< structure size alignment. /
2183
2184	/**
2185	* Write to a CMOS register and update the checksum if necessary.
2186	*
2187	* @returns VBox status code.
2188	* @param pDevIns Device instance of the RTC.
2189	* @param iReg The CMOS register index.
2190	* @param u8Value The CMOS register value.
2191	* @remarks Caller enters the device critical section.
2192	*/
2193	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2194
2195	/**
2196	* Read a CMOS register.
2197	*
2198	* @returns VBox status code.
2199	* @param pDevIns Device instance of the RTC.
2200	* @param iReg The CMOS register index.
2201	* @param pu8Value Where to store the CMOS register value.
2202	* @remarks Caller enters the device critical section.
2203	*/
2204	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2205
2206	} PDMRTCREG;
2207	/** Pointer to a RTC registration structure. */
2208	typedef PDMRTCREG *PPDMRTCREG;
2209	/** Pointer to a const RTC registration structure. */
2210	typedef const PDMRTCREG *PCPDMRTCREG;
2211
2212	/** Current PDMRTCREG version number. */
2213	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2214
2215
2216	/**
2217	* RTC device helpers.
2218	*/
2219	typedef struct PDMRTCHLP
2220	{
2221	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2222	uint32_t u32Version;
2223
2224	/* to-be-defined */
2225
2226	} PDMRTCHLP;
2227	/** Pointer to RTC helpers. */
2228	typedef PDMRTCHLP *PPDMRTCHLP;
2229	/** Pointer to const RTC helpers. */
2230	typedef const PDMRTCHLP *PCPDMRTCHLP;
2231
2232	/** Current PDMRTCHLP version number. */
2233	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2234
2235
2236
2237	/** @name Flags for PCI I/O region registration
2238	* @{ */
2239	/** No handle is passed. */
2240	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2241	/** An I/O port handle is passed. */
2242	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2243	/** An MMIO range handle is passed. */
2244	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2245	/** An MMIO2 handle is passed. */
2246	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2247	/** Handle type mask. */
2248	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2249	/** New-style (mostly wrt callbacks). */
2250	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2251	/** Mask of valid flags. */
2252	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2253	/** @} */
2254
2255
2256	#ifdef IN_RING3
2257
2258	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2259	* @{ */
2260	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2261	* This is handy when registering multiple PCI device functions and the device
2262	* number is left up to the PCI bus. In order to facilitate one PDM device
2263	* instance for each PCI function, this searches earlier PDM device
2264	* instances as well. */
2265	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2266	/** Use the first unused device number (all functions must be unused). */
2267	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2268	/** Use the first unused device function. */
2269	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2270
2271	/** The device and function numbers are not mandatory, just suggestions. */
2272	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2273	/** Registering a PCI bridge device. */
2274	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2275	/** Valid flag mask. */
2276	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2277	/** @} */
2278
2279	/** Current PDMDEVHLPR3 version number. */
2280	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 31, 0)
2281
2282	/**
2283	* PDM Device API.
2284	*/
2285	typedef struct PDMDEVHLPR3
2286	{
2287	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2288	uint32_t u32Version;
2289
2290	/** @name I/O ports
2291	* @{ */
2292	/**
2293	* Creates a range of I/O ports for a device.
2294	*
2295	* The I/O port range must be mapped in a separately call. Any ring-0 and
2296	* raw-mode context callback handlers needs to be set up in the respective
2297	* contexts.
2298	*
2299	* @returns VBox status.
2300	* @param pDevIns The device instance to register the ports with.
2301	* @param cPorts Number of ports to register.
2302	* @param fFlags IOM_IOPORT_F_XXX.
2303	* @param pPciDev The PCI device the range is associated with, if
2304	* applicable.
2305	* @param iPciRegion The PCI device region in the high 16-bit word and
2306	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2307	* @param pfnOut Pointer to function which is gonna handle OUT
2308	* operations. Optional.
2309	* @param pfnIn Pointer to function which is gonna handle IN operations.
2310	* Optional.
2311	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2312	* operations. Optional.
2313	* @param pfnInStr Pointer to function which is gonna handle string IN
2314	* operations. Optional.
2315	* @param pvUser User argument to pass to the callbacks.
2316	* @param pszDesc Pointer to description string. This must not be freed.
2317	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2318	* coverage is allowed. This must not be freed.
2319	* @param phIoPorts Where to return the I/O port range handle.
2320	*
2321	* @remarks Caller enters the device critical section prior to invoking the
2322	* registered callback methods.
2323	*
2324	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2325	* PDMDevHlpIoPortUnmap.
2326	*/
2327	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2328	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2329	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2330	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2331
2332	/**
2333	* Maps an I/O port range.
2334	*
2335	* @returns VBox status.
2336	* @param pDevIns The device instance to register the ports with.
2337	* @param hIoPorts The I/O port range handle.
2338	* @param Port Where to map the range.
2339	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2340	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2341	*/
2342	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2343
2344	/**
2345	* Unmaps an I/O port range.
2346	*
2347	* @returns VBox status.
2348	* @param pDevIns The device instance to register the ports with.
2349	* @param hIoPorts The I/O port range handle.
2350	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2351	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2352	*/
2353	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2354
2355	/**
2356	* Gets the mapping address of the I/O port range @a hIoPorts.
2357	*
2358	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2359	* parameters).
2360	* @param pDevIns The device instance to register the ports with.
2361	* @param hIoPorts The I/O port range handle.
2362	*/
2363	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2364	/** @} */
2365
2366	/**
2367	* Register a number of I/O ports with a device.
2368	*
2369	* These callbacks are of course for the host context (HC).
2370	* Register HC handlers before guest context (GC) handlers! There must be a
2371	* HC handler for every GC handler!
2372	*
2373	* @returns VBox status.
2374	* @param pDevIns The device instance to register the ports with.
2375	* @param Port First port number in the range.
2376	* @param cPorts Number of ports to register.
2377	* @param pvUser User argument.
2378	* @param pfnOut Pointer to function which is gonna handle OUT operations.
2379	* @param pfnIn Pointer to function which is gonna handle IN operations.
2380	* @param pfnOutStr Pointer to function which is gonna handle string OUT operations.
2381	* @param pfnInStr Pointer to function which is gonna handle string IN operations.
2382	* @param pszDesc Pointer to description string. This must not be freed.
2383	* @remarks Caller enters the device critical section prior to invoking the
2384	* registered callback methods.
2385	* @deprecated
2386	*/
2387	DECLR3CALLBACKMEMBER(int, pfnIOPortRegister,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser,
2388	PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
2389	PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc));
2390
2391	/**
2392	* Register a number of I/O ports with a device for RC.
2393	*
2394	* These callbacks are for the raw-mode context (RC). Register ring-3 context
2395	* (R3) handlers before raw-mode context handlers! There must be a R3 handler
2396	* for every RC handler!
2397	*
2398	* @returns VBox status.
2399	* @param pDevIns The device instance to register the ports with
2400	* and which RC module to resolve the names
2401	* against.
2402	* @param Port First port number in the range.
2403	* @param cPorts Number of ports to register.
2404	* @param pvUser User argument.
2405	* @param pszOut Name of the RC function which is gonna handle OUT operations.
2406	* @param pszIn Name of the RC function which is gonna handle IN operations.
2407	* @param pszOutStr Name of the RC function which is gonna handle string OUT operations.
2408	* @param pszInStr Name of the RC function which is gonna handle string IN operations.
2409	* @param pszDesc Pointer to description string. This must not be freed.
2410	* @remarks Caller enters the device critical section prior to invoking the
2411	* registered callback methods.
2412	* @deprecated
2413	*/
2414	DECLR3CALLBACKMEMBER(int, pfnIOPortRegisterRC,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
2415	const char pszOut, const char pszIn,
2416	const char pszOutStr, const char pszInStr, const char *pszDesc));
2417
2418	/**
2419	* Register a number of I/O ports with a device.
2420	*
2421	* These callbacks are of course for the ring-0 host context (R0).
2422	* Register R3 (HC) handlers before R0 (R0) handlers! There must be a R3 (HC) handler for every R0 handler!
2423	*
2424	* @returns VBox status.
2425	* @param pDevIns The device instance to register the ports with.
2426	* @param Port First port number in the range.
2427	* @param cPorts Number of ports to register.
2428	* @param pvUser User argument. (if pointer, then it must be in locked memory!)
2429	* @param pszOut Name of the R0 function which is gonna handle OUT operations.
2430	* @param pszIn Name of the R0 function which is gonna handle IN operations.
2431	* @param pszOutStr Name of the R0 function which is gonna handle string OUT operations.
2432	* @param pszInStr Name of the R0 function which is gonna handle string IN operations.
2433	* @param pszDesc Pointer to description string. This must not be freed.
2434	* @remarks Caller enters the device critical section prior to invoking the
2435	* registered callback methods.
2436	* @deprecated
2437	*/
2438	DECLR3CALLBACKMEMBER(int, pfnIOPortRegisterR0,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
2439	const char pszOut, const char pszIn,
2440	const char pszOutStr, const char pszInStr, const char *pszDesc));
2441
2442	/**
2443	* Deregister I/O ports.
2444	*
2445	* This naturally affects both guest context (GC), ring-0 (R0) and ring-3 (R3/HC) handlers.
2446	*
2447	* @returns VBox status.
2448	* @param pDevIns The device instance owning the ports.
2449	* @param Port First port number in the range.
2450	* @param cPorts Number of ports to deregister.
2451	*/
2452	DECLR3CALLBACKMEMBER(int, pfnIOPortDeregister,(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts));
2453
2454	/** @name MMIO
2455	* @{ */
2456	/**
2457	* Creates a memory mapped I/O (MMIO) region for a device.
2458	*
2459	* The MMIO region must be mapped in a separately call. Any ring-0 and
2460	* raw-mode context callback handlers needs to be set up in the respective
2461	* contexts.
2462	*
2463	* @returns VBox status.
2464	* @param pDevIns The device instance to register the ports with.
2465	* @param cbRegion The size of the region in bytes.
2466	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2467	* @param pPciDev The PCI device the range is associated with, if
2468	* applicable.
2469	* @param iPciRegion The PCI device region in the high 16-bit word and
2470	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2471	* @param pfnWrite Pointer to function which is gonna handle Write
2472	* operations.
2473	* @param pfnRead Pointer to function which is gonna handle Read
2474	* operations.
2475	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2476	* operations. (optional)
2477	* @param pvUser User argument to pass to the callbacks.
2478	* @param pszDesc Pointer to description string. This must not be freed.
2479	* @param phRegion Where to return the MMIO region handle.
2480	*
2481	* @remarks Caller enters the device critical section prior to invoking the
2482	* registered callback methods.
2483	*
2484	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2485	*/
2486	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2487	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2488	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2489	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2490
2491	/**
2492	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2493	*
2494	* @returns VBox status.
2495	* @param pDevIns The device instance the region is associated with.
2496	* @param hRegion The MMIO region handle.
2497	* @param GCPhys Where to map the region.
2498	* @note An MMIO range may overlap with base memory if a lot of RAM is
2499	* configured for the VM, in which case we'll drop the base memory
2500	* pages. Presently we will make no attempt to preserve anything that
2501	* happens to be present in the base memory that is replaced, this is
2502	* technically incorrect but it's just not worth the effort to do
2503	* right, at least not at this point.
2504	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2505	* PDMDevHlpMmioSetUpContext
2506	*/
2507	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2508
2509	/**
2510	* Unmaps a memory mapped I/O (MMIO) region.
2511	*
2512	* @returns VBox status.
2513	* @param pDevIns The device instance the region is associated with.
2514	* @param hRegion The MMIO region handle.
2515	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2516	* PDMDevHlpMmioSetUpContext
2517	*/
2518	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2519
2520	/**
2521	* Reduces the length of a MMIO range.
2522	*
2523	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2524	* only work during saved state restore. It will not call the PCI bus code, as
2525	* that is expected to restore the saved resource configuration.
2526	*
2527	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2528	* called it will only map @a cbRegion bytes and not the value set during
2529	* registration.
2530	*
2531	* @return VBox status code.
2532	* @param pDevIns The device owning the range.
2533	* @param hRegion The MMIO region handle.
2534	* @param cbRegion The new size, must be smaller.
2535	*/
2536	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2537
2538	/**
2539	* Gets the mapping address of the MMIO region @a hRegion.
2540	*
2541	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2542	* @param pDevIns The device instance to register the ports with.
2543	* @param hRegion The MMIO region handle.
2544	*/
2545	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2546	/** @} */
2547
2548	/**
2549	* Register a Memory Mapped I/O (MMIO) region.
2550	*
2551	* These callbacks are of course for the ring-3 context (R3). Register HC
2552	* handlers before raw-mode context (RC) and ring-0 context (R0) handlers! There
2553	* must be a R3 handler for every RC and R0 handler!
2554	*
2555	* @returns VBox status.
2556	* @param pDevIns The device instance to register the MMIO with.
2557	* @param GCPhysStart First physical address in the range.
2558	* @param cbRange The size of the range (in bytes).
2559	* @param pvUser User argument.
2560	* @param pfnWrite Pointer to function which is gonna handle Write operations.
2561	* @param pfnRead Pointer to function which is gonna handle Read operations.
2562	* @param pfnFill Pointer to function which is gonna handle Fill/memset operations. (optional)
2563	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2564	* @param pszDesc Pointer to description string. This must not be freed.
2565	* @remarks Caller enters the device critical section prior to invoking the
2566	* registered callback methods.
2567	* @deprecated
2568	*/
2569	DECLR3CALLBACKMEMBER(int, pfnMMIORegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
2570	PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
2571	uint32_t fFlags, const char *pszDesc));
2572
2573	/**
2574	* Register a Memory Mapped I/O (MMIO) region for RC.
2575	*
2576	* These callbacks are for the raw-mode context (RC). Register ring-3 context
2577	* (R3) handlers before guest context handlers! There must be a R3 handler for
2578	* every RC handler!
2579	*
2580	* @returns VBox status.
2581	* @param pDevIns The device instance to register the MMIO with.
2582	* @param GCPhysStart First physical address in the range.
2583	* @param cbRange The size of the range (in bytes).
2584	* @param pvUser User argument.
2585	* @param pszWrite Name of the RC function which is gonna handle Write operations.
2586	* @param pszRead Name of the RC function which is gonna handle Read operations.
2587	* @param pszFill Name of the RC function which is gonna handle Fill/memset operations. (optional)
2588	* @remarks Caller enters the device critical section prior to invoking the
2589	* registered callback methods.
2590	* @deprecated
2591	*/
2592	DECLR3CALLBACKMEMBER(int, pfnMMIORegisterRC,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
2593	const char pszWrite, const char pszRead, const char *pszFill));
2594
2595	/**
2596	* Register a Memory Mapped I/O (MMIO) region for R0.
2597	*
2598	* These callbacks are for the ring-0 host context (R0). Register ring-3
2599	* constext (R3) handlers before R0 handlers! There must be a R3 handler for
2600	* every R0 handler!
2601	*
2602	* @returns VBox status.
2603	* @param pDevIns The device instance to register the MMIO with.
2604	* @param GCPhysStart First physical address in the range.
2605	* @param cbRange The size of the range (in bytes).
2606	* @param pvUser User argument. (if pointer, then it must be in locked memory!)
2607	* @param pszWrite Name of the RC function which is gonna handle Write operations.
2608	* @param pszRead Name of the RC function which is gonna handle Read operations.
2609	* @param pszFill Name of the RC function which is gonna handle Fill/memset operations. (optional)
2610	* @remarks Caller enters the device critical section prior to invoking the
2611	* registered callback methods.
2612	* @deprecated
2613	*/
2614	DECLR3CALLBACKMEMBER(int, pfnMMIORegisterR0,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
2615	const char pszWrite, const char pszRead, const char *pszFill));
2616
2617	/**
2618	* Deregister a Memory Mapped I/O (MMIO) region.
2619	*
2620	* This naturally affects both guest context (GC), ring-0 (R0) and ring-3 (R3/HC) handlers.
2621	*
2622	* @returns VBox status.
2623	* @param pDevIns The device instance owning the MMIO region(s).
2624	* @param GCPhysStart First physical address in the range.
2625	* @param cbRange The size of the range (in bytes).
2626	* @deprecated
2627	*/
2628	DECLR3CALLBACKMEMBER(int, pfnMMIODeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange));
2629
2630	/** @name MMIO2
2631	* @{ */
2632	/**
2633	* Creates a MMIO2 region.
2634	*
2635	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2636	* associated with a device. It is also non-shared memory with a permanent
2637	* ring-3 mapping and page backing (presently).
2638	*
2639	* @returns VBox status.
2640	* @param pDevIns The device instance.
2641	* @param pPciDev The PCI device the region is associated with, or
2642	* NULL if no PCI device association.
2643	* @param iPciRegion The region number. Use the PCI region number as
2644	* this must be known to the PCI bus device too. If
2645	* it's not associated with the PCI device, then
2646	* any number up to UINT8_MAX is fine.
2647	* @param cb The size (in bytes) of the region.
2648	* @param fFlags Reserved for future use, must be zero.
2649	* @param ppvMapping Where to store the address of the ring-3 mapping
2650	* of the memory.
2651	* @param pszDesc Pointer to description string. This must not be
2652	* freed.
2653	* @param phRegion Where to return the MMIO2 region handle.
2654	*
2655	* @thread EMT(0)
2656	*/
2657	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2658	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2659
2660	/**
2661	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2662	*
2663	* Any physical access handlers registered for the region must be deregistered
2664	* before calling this function.
2665	*
2666	* @returns VBox status code.
2667	* @param pDevIns The device instance.
2668	* @param hRegion The MMIO2 region handle.
2669	* @thread EMT.
2670	*/
2671	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2672
2673	/**
2674	* Maps a MMIO2 region (into the guest physical address space).
2675	*
2676	* @returns VBox status.
2677	* @param pDevIns The device instance the region is associated with.
2678	* @param hRegion The MMIO2 region handle.
2679	* @param GCPhys Where to map the region.
2680	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2681	* configured for the VM, in which case we'll drop the base memory
2682	* pages. Presently we will make no attempt to preserve anything that
2683	* happens to be present in the base memory that is replaced, this is
2684	* technically incorrect but it's just not worth the effort to do
2685	* right, at least not at this point.
2686	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2687	*/
2688	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2689
2690	/**
2691	* Unmaps a MMIO2 region.
2692	*
2693	* @returns VBox status.
2694	* @param pDevIns The device instance the region is associated with.
2695	* @param hRegion The MMIO2 region handle.
2696	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2697	*/
2698	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2699
2700	/**
2701	* Reduces the length of a MMIO range.
2702	*
2703	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2704	* only work during saved state restore. It will not call the PCI bus code, as
2705	* that is expected to restore the saved resource configuration.
2706	*
2707	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2708	* called it will only map @a cbRegion bytes and not the value set during
2709	* registration.
2710	*
2711	* @return VBox status code.
2712	* @param pDevIns The device owning the range.
2713	* @param hRegion The MMIO2 region handle.
2714	* @param cbRegion The new size, must be smaller.
2715	*/
2716	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2717
2718	/**
2719	* Gets the mapping address of the MMIO region @a hRegion.
2720	*
2721	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2722	* @param pDevIns The device instance to register the ports with.
2723	* @param hRegion The MMIO2 region handle.
2724	*/
2725	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2726
2727	/**
2728	* Changes the number of an MMIO2 or pre-registered MMIO region.
2729	*
2730	* This should only be used to deal with saved state problems, so there is no
2731	* convenience inline wrapper for this method.
2732	*
2733	* @returns VBox status code.
2734	* @param pDevIns The device instance.
2735	* @param hRegion The MMIO2 region handle.
2736	* @param iNewRegion The new region index.
2737	*
2738	* @sa @bugref{9359}
2739	*/
2740	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2741	/** @} */
2742
2743	/**
2744	* Allocate and register a MMIO2 region.
2745	*
2746	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2747	* associated with a device. It is also non-shared memory with a permanent
2748	* ring-3 mapping and page backing (presently).
2749	*
2750	* @returns VBox status.
2751	* @param pDevIns The device instance.
2752	* @param pPciDev The PCI device the region is associated with, or
2753	* NULL if no PCI device association.
2754	* @param iRegion The region number. Use the PCI region number as
2755	* this must be known to the PCI bus device too. If
2756	* it's not associated with the PCI device, then
2757	* any number up to UINT8_MAX is fine.
2758	* @param cb The size (in bytes) of the region.
2759	* @param fFlags Reserved for future use, must be zero.
2760	* @param ppv Where to store the address of the ring-3 mapping
2761	* of the memory.
2762	* @param pszDesc Pointer to description string. This must not be
2763	* freed.
2764	* @thread EMT.
2765	* @deprecated
2766	*/
2767	DECLR3CALLBACKMEMBER(int, pfnMMIO2Register,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
2768	uint32_t fFlags, void *ppv, const char pszDesc));
2769
2770	/**
2771	* Deregisters and frees a MMIO or MMIO2 region.
2772	*
2773	* Any physical (and virtual) access handlers registered for the region must
2774	* be deregistered before calling this function (MMIO2 only).
2775	*
2776	* @returns VBox status code.
2777	* @param pDevIns The device instance.
2778	* @param pPciDev The PCI device the region is associated with, or
2779	* NULL if not associated with any.
2780	* @param iRegion The region number used during registration.
2781	* @thread EMT.
2782	* @deprecated
2783	*/
2784	DECLR3CALLBACKMEMBER(int, pfnMMIOExDeregister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion));
2785
2786	/**
2787	* Maps a MMIO or MMIO2 region into the physical memory space.
2788	*
2789	* A MMIO2 range or a pre-registered MMIO range may overlap with base memory if
2790	* a lot of RAM is configured for the VM, in which case we'll drop the base
2791	* memory pages. Presently we will make no attempt to preserve anything that
2792	* happens to be present in the base memory that is replaced, this is of course
2793	* incorrect but it's too much effort.
2794	*
2795	* @returns VBox status code.
2796	* @param pDevIns The device instance.
2797	* @param pPciDev The PCI device the region is associated with, or
2798	* NULL if not associated with any.
2799	* @param iRegion The region number used during registration.
2800	* @param GCPhys The physical address to map it at.
2801	* @thread EMT.
2802	* @deprecated for MMIO
2803	*/
2804	DECLR3CALLBACKMEMBER(int, pfnMMIOExMap,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys));
2805
2806	/**
2807	* Unmaps a MMIO or MMIO2 region previously mapped using pfnMMIOExMap.
2808	*
2809	* @returns VBox status code.
2810	* @param pDevIns The device instance.
2811	* @param pPciDev The PCI device the region is associated with, or
2812	* NULL if not associated with any.
2813	* @param iRegion The region number used during registration.
2814	* @param GCPhys The physical address it's currently mapped at.
2815	* @thread EMT.
2816	* @deprecated for MMIO
2817	*/
2818	DECLR3CALLBACKMEMBER(int, pfnMMIOExUnmap,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys));
2819
2820	/**
2821	* Reduces the length of a MMIO2 or pre-registered MMIO range.
2822	*
2823	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2824	* only work during saved state restore. It will not call the PCI bus code, as
2825	* that is expected to restore the saved resource configuration.
2826	*
2827	* It just adjusts the mapping length of the region so that when pfnMMIOExMap is
2828	* called it will only map @a cbRegion bytes and not the value set during
2829	* registration.
2830	*
2831	* @return VBox status code.
2832	* @param pDevIns The device owning the range.
2833	* @param pPciDev The PCI device the region is associated with, or
2834	* NULL if not associated with any.
2835	* @param iRegion The region.
2836	* @param cbRegion The new size, must be smaller.
2837	*/
2838	DECLR3CALLBACKMEMBER(int, pfnMMIOExReduce,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion));
2839
2840	/**
2841	* Maps a portion of an MMIO2 region into the hypervisor region.
2842	*
2843	* Callers of this API must never deregister the MMIO2 region before the
2844	* VM is powered off.
2845	*
2846	* @return VBox status code.
2847	* @param pDevIns The device owning the MMIO2 memory.
2848	* @param pPciDev The PCI device the region is associated with, or
2849	* NULL if not associated with any.
2850	* @param iRegion The region.
2851	* @param off The offset into the region. Will be rounded down
2852	* to closest page boundary.
2853	* @param cb The number of bytes to map. Will be rounded up
2854	* to the closest page boundary.
2855	* @param pszDesc Mapping description.
2856	* @param pRCPtr Where to store the RC address.
2857	*/
2858	DECLR3CALLBACKMEMBER(int, pfnMMHyperMapMMIO2,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
2859	RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr));
2860
2861	/**
2862	* Maps a portion of an MMIO2 region into kernel space (host).
2863	*
2864	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
2865	* or the VM is terminated.
2866	*
2867	* @return VBox status code.
2868	* @param pDevIns The device owning the MMIO2 memory.
2869	* @param pPciDev The PCI device the region is associated with, or
2870	* NULL if not associated with any.
2871	* @param iRegion The region.
2872	* @param off The offset into the region. Must be page
2873	* aligned.
2874	* @param cb The number of bytes to map. Must be page
2875	* aligned.
2876	* @param pszDesc Mapping description.
2877	* @param pR0Ptr Where to store the R0 address.
2878	*/
2879	DECLR3CALLBACKMEMBER(int, pfnMMIO2MapKernel,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
2880	RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr));
2881
2882	/**
2883	* Register a ROM (BIOS) region.
2884	*
2885	* It goes without saying that this is read-only memory. The memory region must be
2886	* in unassigned memory. I.e. from the top of the address space or on the PC in
2887	* the 0xa0000-0xfffff range.
2888	*
2889	* @returns VBox status.
2890	* @param pDevIns The device instance owning the ROM region.
2891	* @param GCPhysStart First physical address in the range.
2892	* Must be page aligned!
2893	* @param cbRange The size of the range (in bytes).
2894	* Must be page aligned!
2895	* @param pvBinary Pointer to the binary data backing the ROM image.
2896	* @param cbBinary The size of the binary pointer. This must
2897	* be equal or smaller than @a cbRange.
2898	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2899	* @param pszDesc Pointer to description string. This must not be freed.
2900	*
2901	* @remark There is no way to remove the rom, automatically on device cleanup or
2902	* manually from the device yet. At present I doubt we need such features...
2903	*/
2904	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2905	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2906
2907	/**
2908	* Changes the protection of shadowed ROM mapping.
2909	*
2910	* This is intented for use by the system BIOS, chipset or device in question to
2911	* change the protection of shadowed ROM code after init and on reset.
2912	*
2913	* @param pDevIns The device instance.
2914	* @param GCPhysStart Where the mapping starts.
2915	* @param cbRange The size of the mapping.
2916	* @param enmProt The new protection type.
2917	*/
2918	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2919
2920	/**
2921	* Register a save state data unit.
2922	*
2923	* @returns VBox status.
2924	* @param pDevIns The device instance.
2925	* @param uVersion Data layout version number.
2926	* @param cbGuess The approximate amount of data in the unit.
2927	* Only for progress indicators.
2928	* @param pszBefore Name of data unit which we should be put in
2929	* front of. Optional (NULL).
2930	*
2931	* @param pfnLivePrep Prepare live save callback, optional.
2932	* @param pfnLiveExec Execute live save callback, optional.
2933	* @param pfnLiveVote Vote live save callback, optional.
2934	*
2935	* @param pfnSavePrep Prepare save callback, optional.
2936	* @param pfnSaveExec Execute save callback, optional.
2937	* @param pfnSaveDone Done save callback, optional.
2938	*
2939	* @param pfnLoadPrep Prepare load callback, optional.
2940	* @param pfnLoadExec Execute load callback, optional.
2941	* @param pfnLoadDone Done load callback, optional.
2942	* @remarks Caller enters the device critical section prior to invoking the
2943	* registered callback methods.
2944	*/
2945	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2946	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2947	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2948	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2949
2950	/** @name Exported SSM Functions
2951	* @{ */
2952	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2953	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2954	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2955	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2956	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2957	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2958	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2959	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2960	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2961	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2962	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2963	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2964	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2965	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2966	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2967	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2968	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2969	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2970	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2971	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2972	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2973	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2974	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2975	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2976	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2977	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2978	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2979	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2980	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2981	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2982	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2983	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2984	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2985	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2986	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2987	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2988	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2989	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2990	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2991	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2992	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2993	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2994	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2995	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2996	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2997	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2998	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2999	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
3000	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
3001	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
3002	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
3003	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
3004	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
3005	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
3006	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
3007	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
3008	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
3009	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3010	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3011	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
3012	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
3013	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
3014	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
3015	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
3016	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
3017	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
3018	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
3019	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
3020	/** @} */
3021
3022	/**
3023	* Creates a timer.
3024	*
3025	* @returns VBox status.
3026	* @param pDevIns The device instance.
3027	* @param enmClock The clock to use on this timer.
3028	* @param pfnCallback Callback function.
3029	* @param pvUser User argument for the callback.
3030	* @param fFlags Flags, see TMTIMER_FLAGS_*.
3031	* @param pszDesc Pointer to description string which must stay around
3032	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
3033	* @param ppTimer Where to store the timer on success.
3034	* @remarks Caller enters the device critical section prior to invoking the
3035	* callback.
3036	*/
3037	DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
3038	void pvUser, uint32_t fFlags, const char pszDesc, PPTMTIMERR3 ppTimer));
3039
3040	/**
3041	* Creates a timer w/ a cross context handle.
3042	*
3043	* @returns VBox status.
3044	* @param pDevIns The device instance.
3045	* @param enmClock The clock to use on this timer.
3046	* @param pfnCallback Callback function.
3047	* @param pvUser User argument for the callback.
3048	* @param fFlags Flags, see TMTIMER_FLAGS_*.
3049	* @param pszDesc Pointer to description string which must stay around
3050	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
3051	* @param phTimer Where to store the timer handle on success.
3052	* @remarks Caller enters the device critical section prior to invoking the
3053	* callback.
3054	*/
3055	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
3056	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
3057
3058	/**
3059	* Translates a timer handle to a pointer.
3060	*
3061	* @returns The time address.
3062	* @param pDevIns The device instance.
3063	* @param hTimer The timer handle.
3064	*/
3065	DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3066
3067	/** @name Timer handle method wrappers
3068	* @{ */
3069	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
3070	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
3071	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
3072	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3073	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3074	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3075	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3076	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3077	DECLR3CALLBACKMEMBER(int, pfnTimerLock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
3078	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
3079	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
3080	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
3081	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
3082	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
3083	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
3084	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3085	DECLR3CALLBACKMEMBER(void, pfnTimerUnlock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3086	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3087	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3088	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3089	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3090	/** @sa TMR3TimerSkip */
3091	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
3092	/** @} */
3093
3094	/**
3095	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
3096	*
3097	* @returns pTime.
3098	* @param pDevIns The device instance.
3099	* @param pTime Where to store the time.
3100	*/
3101	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
3102
3103	/** @name Exported CFGM Functions.
3104	* @{ */
3105	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
3106	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
3107	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
3108	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3109	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3110	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3111	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3112	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
3113	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3114	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3115	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
3116	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
3117	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
3118	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
3119	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
3120	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
3121	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
3122	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
3123	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
3124	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
3125	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
3126	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
3127	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
3128	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
3129	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
3130	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
3131	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3132	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3133	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3134	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3135	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3136	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3137	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
3138	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
3139	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3140	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3141	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3142	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3143	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3144	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3145	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3146	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3147	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3148	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3149	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3150	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3151	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3152	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3153	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3154	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3155	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3156	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3157	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3158	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3159	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3160	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3161	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3162	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3163	const char pszValidValues, const char pszValidNodes,
3164	const char *pszWho, uint32_t uInstance));
3165	/** @} */
3166
3167	/**
3168	* Read physical memory.
3169	*
3170	* @returns VINF_SUCCESS (for now).
3171	* @param pDevIns The device instance.
3172	* @param GCPhys Physical address start reading from.
3173	* @param pvBuf Where to put the read bits.
3174	* @param cbRead How many bytes to read.
3175	* @thread Any thread, but the call may involve the emulation thread.
3176	*/
3177	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
3178
3179	/**
3180	* Write to physical memory.
3181	*
3182	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3183	* @param pDevIns The device instance.
3184	* @param GCPhys Physical address to write to.
3185	* @param pvBuf What to write.
3186	* @param cbWrite How many bytes to write.
3187	* @thread Any thread, but the call may involve the emulation thread.
3188	*/
3189	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
3190
3191	/**
3192	* Requests the mapping of a guest page into ring-3.
3193	*
3194	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3195	* release it.
3196	*
3197	* This API will assume your intention is to write to the page, and will
3198	* therefore replace shared and zero pages. If you do not intend to modify the
3199	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3200	*
3201	* @returns VBox status code.
3202	* @retval VINF_SUCCESS on success.
3203	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3204	* backing or if the page has any active access handlers. The caller
3205	* must fall back on using PGMR3PhysWriteExternal.
3206	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3207	*
3208	* @param pDevIns The device instance.
3209	* @param GCPhys The guest physical address of the page that
3210	* should be mapped.
3211	* @param fFlags Flags reserved for future use, MBZ.
3212	* @param ppv Where to store the address corresponding to
3213	* GCPhys.
3214	* @param pLock Where to store the lock information that
3215	* pfnPhysReleasePageMappingLock needs.
3216	*
3217	* @remark Avoid calling this API from within critical sections (other than the
3218	* PGM one) because of the deadlock risk when we have to delegating the
3219	* task to an EMT.
3220	* @thread Any.
3221	*/
3222	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3223	PPGMPAGEMAPLOCK pLock));
3224
3225	/**
3226	* Requests the mapping of a guest page into ring-3, external threads.
3227	*
3228	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3229	* release it.
3230	*
3231	* @returns VBox status code.
3232	* @retval VINF_SUCCESS on success.
3233	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3234	* backing or if the page as an active ALL access handler. The caller
3235	* must fall back on using PGMPhysRead.
3236	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3237	*
3238	* @param pDevIns The device instance.
3239	* @param GCPhys The guest physical address of the page that
3240	* should be mapped.
3241	* @param fFlags Flags reserved for future use, MBZ.
3242	* @param ppv Where to store the address corresponding to
3243	* GCPhys.
3244	* @param pLock Where to store the lock information that
3245	* pfnPhysReleasePageMappingLock needs.
3246	*
3247	* @remark Avoid calling this API from within critical sections.
3248	* @thread Any.
3249	*/
3250	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3251	void const **ppv, PPGMPAGEMAPLOCK pLock));
3252
3253	/**
3254	* Release the mapping of a guest page.
3255	*
3256	* This is the counter part of pfnPhysGCPhys2CCPtr and
3257	* pfnPhysGCPhys2CCPtrReadOnly.
3258	*
3259	* @param pDevIns The device instance.
3260	* @param pLock The lock structure initialized by the mapping
3261	* function.
3262	*/
3263	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3264
3265	/**
3266	* Read guest physical memory by virtual address.
3267	*
3268	* @param pDevIns The device instance.
3269	* @param pvDst Where to put the read bits.
3270	* @param GCVirtSrc Guest virtual address to start reading from.
3271	* @param cb How many bytes to read.
3272	* @thread The emulation thread.
3273	*/
3274	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3275
3276	/**
3277	* Write to guest physical memory by virtual address.
3278	*
3279	* @param pDevIns The device instance.
3280	* @param GCVirtDst Guest virtual address to write to.
3281	* @param pvSrc What to write.
3282	* @param cb How many bytes to write.
3283	* @thread The emulation thread.
3284	*/
3285	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3286
3287	/**
3288	* Convert a guest virtual address to a guest physical address.
3289	*
3290	* @returns VBox status code.
3291	* @param pDevIns The device instance.
3292	* @param GCPtr Guest virtual address.
3293	* @param pGCPhys Where to store the GC physical address
3294	* corresponding to GCPtr.
3295	* @thread The emulation thread.
3296	* @remark Careful with page boundaries.
3297	*/
3298	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3299
3300	/**
3301	* Allocate memory which is associated with current VM instance
3302	* and automatically freed on it's destruction.
3303	*
3304	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3305	* @param pDevIns The device instance.
3306	* @param cb Number of bytes to allocate.
3307	*/
3308	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3309
3310	/**
3311	* Allocate memory which is associated with current VM instance
3312	* and automatically freed on it's destruction. The memory is ZEROed.
3313	*
3314	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3315	* @param pDevIns The device instance.
3316	* @param cb Number of bytes to allocate.
3317	*/
3318	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3319
3320	/**
3321	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3322	*
3323	* @param pDevIns The device instance.
3324	* @param pv Pointer to the memory to free.
3325	*/
3326	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3327
3328	/**
3329	* Gets the VM state.
3330	*
3331	* @returns VM state.
3332	* @param pDevIns The device instance.
3333	* @thread Any thread (just keep in mind that it's volatile info).
3334	*/
3335	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3336
3337	/**
3338	* Checks if the VM was teleported and hasn't been fully resumed yet.
3339	*
3340	* @returns true / false.
3341	* @param pDevIns The device instance.
3342	* @thread Any thread.
3343	*/
3344	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3345
3346	/**
3347	* Set the VM error message
3348	*
3349	* @returns rc.
3350	* @param pDevIns The device instance.
3351	* @param rc VBox status code.
3352	* @param SRC_POS Use RT_SRC_POS.
3353	* @param pszFormat Error message format string.
3354	* @param ... Error message arguments.
3355	*/
3356	DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3357	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3358
3359	/**
3360	* Set the VM error message
3361	*
3362	* @returns rc.
3363	* @param pDevIns The device instance.
3364	* @param rc VBox status code.
3365	* @param SRC_POS Use RT_SRC_POS.
3366	* @param pszFormat Error message format string.
3367	* @param va Error message arguments.
3368	*/
3369	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3370	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3371
3372	/**
3373	* Set the VM runtime error message
3374	*
3375	* @returns VBox status code.
3376	* @param pDevIns The device instance.
3377	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3378	* @param pszErrorId Error ID string.
3379	* @param pszFormat Error message format string.
3380	* @param ... Error message arguments.
3381	*/
3382	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3383	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3384
3385	/**
3386	* Set the VM runtime error message
3387	*
3388	* @returns VBox status code.
3389	* @param pDevIns The device instance.
3390	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3391	* @param pszErrorId Error ID string.
3392	* @param pszFormat Error message format string.
3393	* @param va Error message arguments.
3394	*/
3395	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3396	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3397
3398	/**
3399	* Stops the VM and enters the debugger to look at the guest state.
3400	*
3401	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3402	* invoking this function directly.
3403	*
3404	* @returns VBox status code which must be passed up to the VMM.
3405	* @param pDevIns The device instance.
3406	* @param pszFile Filename of the assertion location.
3407	* @param iLine The linenumber of the assertion location.
3408	* @param pszFunction Function of the assertion location.
3409	* @param pszFormat Message. (optional)
3410	* @param args Message parameters.
3411	*/
3412	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3413	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3414
3415	/**
3416	* Register a info handler with DBGF.
3417	*
3418	* @returns VBox status code.
3419	* @param pDevIns The device instance.
3420	* @param pszName The identifier of the info.
3421	* @param pszDesc The description of the info and any arguments
3422	* the handler may take.
3423	* @param pfnHandler The handler function to be called to display the
3424	* info.
3425	*/
3426	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3427
3428	/**
3429	* Register a info handler with DBGF, argv style.
3430	*
3431	* @returns VBox status code.
3432	* @param pDevIns The device instance.
3433	* @param pszName The identifier of the info.
3434	* @param pszDesc The description of the info and any arguments
3435	* the handler may take.
3436	* @param pfnHandler The handler function to be called to display the
3437	* info.
3438	*/
3439	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3440
3441	/**
3442	* Registers a set of registers for a device.
3443	*
3444	* The @a pvUser argument of the getter and setter callbacks will be
3445	* @a pDevIns. The register names will be prefixed by the device name followed
3446	* immediately by the instance number.
3447	*
3448	* @returns VBox status code.
3449	* @param pDevIns The device instance.
3450	* @param paRegisters The register descriptors.
3451	*
3452	* @remarks The device critical section is NOT entered prior to working the
3453	* callbacks registered via this helper!
3454	*/
3455	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3456
3457	/**
3458	* Gets the trace buffer handle.
3459	*
3460	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3461	* really inteded for direct usage, thus no inline wrapper function.
3462	*
3463	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3464	* @param pDevIns The device instance.
3465	*/
3466	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3467
3468	/**
3469	* Registers a statistics sample if statistics are enabled.
3470	*
3471	* @param pDevIns Device instance of the DMA.
3472	* @param pvSample Pointer to the sample.
3473	* @param enmType Sample type. This indicates what pvSample is
3474	* pointing at.
3475	* @param pszName Sample name. The name is on this form
3476	* "/<component>/<sample>". Further nesting is
3477	* possible.
3478	* @param enmUnit Sample unit.
3479	* @param pszDesc Sample description.
3480	*/
3481	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3482
3483	/**
3484	* Same as pfnSTAMRegister except that the name is specified in a
3485	* RTStrPrintf like fashion.
3486	*
3487	* @returns VBox status.
3488	* @param pDevIns Device instance of the DMA.
3489	* @param pvSample Pointer to the sample.
3490	* @param enmType Sample type. This indicates what pvSample is
3491	* pointing at.
3492	* @param enmVisibility Visibility type specifying whether unused
3493	* statistics should be visible or not.
3494	* @param enmUnit Sample unit.
3495	* @param pszDesc Sample description.
3496	* @param pszName The sample name format string.
3497	* @param ... Arguments to the format string.
3498	*/
3499	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterF,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3500	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3501	const char *pszName, ...) RT_IPRT_FORMAT_ATTR(7, 8));
3502
3503	/**
3504	* Same as pfnSTAMRegister except that the name is specified in a
3505	* RTStrPrintfV like fashion.
3506	*
3507	* @returns VBox status.
3508	* @param pDevIns Device instance of the DMA.
3509	* @param pvSample Pointer to the sample.
3510	* @param enmType Sample type. This indicates what pvSample is
3511	* pointing at.
3512	* @param enmVisibility Visibility type specifying whether unused
3513	* statistics should be visible or not.
3514	* @param enmUnit Sample unit.
3515	* @param pszDesc Sample description.
3516	* @param pszName The sample name format string.
3517	* @param args Arguments to the format string.
3518	*/
3519	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3520	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3521	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3522
3523	/**
3524	* Registers a PCI device with the default PCI bus.
3525	*
3526	* If a PDM device has more than one PCI device, they must be registered in the
3527	* order of PDMDEVINSR3::apPciDevs.
3528	*
3529	* @returns VBox status code.
3530	* @param pDevIns The device instance.
3531	* @param pPciDev The PCI device structure.
3532	* This must be kept in the instance data.
3533	* The PCI configuration must be initialized before registration.
3534	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
3535	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3536	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3537	* device number (0-31). This will be ignored if
3538	* the CFGM configuration contains a PCIDeviceNo
3539	* value.
3540	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3541	* function number (0-7). This will be ignored if
3542	* the CFGM configuration contains a PCIFunctionNo
3543	* value.
3544	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3545	* The pointer is saved, so don't free or changed.
3546	* @note The PCI device configuration is now implicit from the apPciDevs
3547	* index, meaning that the zero'th entry is the primary one and
3548	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3549	*/
3550	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3551	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3552
3553	/**
3554	* Initialize MSI or MSI-X emulation support for the given PCI device.
3555	*
3556	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3557	*
3558	* @returns VBox status code.
3559	* @param pDevIns The device instance.
3560	* @param pPciDev The PCI device. NULL is an alias for the first
3561	* one registered.
3562	* @param pMsiReg MSI emulation registration structure.
3563	*/
3564	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3565
3566	/**
3567	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3568	*
3569	* @returns VBox status code.
3570	* @param pDevIns The device instance.
3571	* @param pPciDev The PCI device structure. If NULL the default
3572	* PCI device for this device instance is used.
3573	* @param iRegion The region number.
3574	* @param cbRegion Size of the region.
3575	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3576	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3577	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3578	* @a fFlags, UINT64_MAX if no handle is passed
3579	* (old style).
3580	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3581	* handle is specified. The callback will be
3582	* invoked holding only the PDM lock. The device
3583	* lock will _not_ be taken (due to lock order).
3584	*/
3585	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3586	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3587	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3588
3589	/**
3590	* Register PCI configuration space read/write callbacks.
3591	*
3592	* @returns VBox status code.
3593	* @param pDevIns The device instance.
3594	* @param pPciDev The PCI device structure. If NULL the default
3595	* PCI device for this device instance is used.
3596	* @param pfnRead Pointer to the user defined PCI config read function.
3597	* to call default PCI config read function. Can be NULL.
3598	* @param pfnWrite Pointer to the user defined PCI config write function.
3599	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3600	* is NOT take because that is very likely be a lock order violation.
3601	* @thread EMT(0)
3602	* @note Only callable during VM creation.
3603	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3604	*/
3605	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3606	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3607
3608	/**
3609	* Perform a PCI configuration space write.
3610	*
3611	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3612	*
3613	* @returns Strict VBox status code (mainly DBGFSTOP).
3614	* @param pDevIns The device instance.
3615	* @param pPciDev The PCI device which config space is being read.
3616	* @param uAddress The config space address.
3617	* @param cb The size of the read: 1, 2 or 4 bytes.
3618	* @param u32Value The value to write.
3619	*/
3620	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3621	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3622
3623	/**
3624	* Perform a PCI configuration space read.
3625	*
3626	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3627	*
3628	* @returns Strict VBox status code (mainly DBGFSTOP).
3629	* @param pDevIns The device instance.
3630	* @param pPciDev The PCI device which config space is being read.
3631	* @param uAddress The config space address.
3632	* @param cb The size of the read: 1, 2 or 4 bytes.
3633	* @param pu32Value Where to return the value.
3634	*/
3635	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3636	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3637
3638	/**
3639	* Bus master physical memory read.
3640	*
3641	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3642	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3643	* @param pDevIns The device instance.
3644	* @param pPciDev The PCI device structure. If NULL the default
3645	* PCI device for this device instance is used.
3646	* @param GCPhys Physical address start reading from.
3647	* @param pvBuf Where to put the read bits.
3648	* @param cbRead How many bytes to read.
3649	* @thread Any thread, but the call may involve the emulation thread.
3650	*/
3651	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
3652
3653	/**
3654	* Bus master physical memory write.
3655	*
3656	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3657	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3658	* @param pDevIns The device instance.
3659	* @param pPciDev The PCI device structure. If NULL the default
3660	* PCI device for this device instance is used.
3661	* @param GCPhys Physical address to write to.
3662	* @param pvBuf What to write.
3663	* @param cbWrite How many bytes to write.
3664	* @thread Any thread, but the call may involve the emulation thread.
3665	*/
3666	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
3667
3668	/**
3669	* Sets the IRQ for the given PCI device.
3670	*
3671	* @param pDevIns The device instance.
3672	* @param pPciDev The PCI device structure. If NULL the default
3673	* PCI device for this device instance is used.
3674	* @param iIrq IRQ number to set.
3675	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3676	* @thread Any thread, but will involve the emulation thread.
3677	*/
3678	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3679
3680	/**
3681	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3682	* the request when not called from EMT.
3683	*
3684	* @param pDevIns The device instance.
3685	* @param pPciDev The PCI device structure. If NULL the default
3686	* PCI device for this device instance is used.
3687	* @param iIrq IRQ number to set.
3688	* @param iLevel IRQ level.
3689	* @thread Any thread, but will involve the emulation thread.
3690	*/
3691	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3692
3693	/**
3694	* Set ISA IRQ for a device.
3695	*
3696	* @param pDevIns The device instance.
3697	* @param iIrq IRQ number to set.
3698	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3699	* @thread Any thread, but will involve the emulation thread.
3700	*/
3701	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3702
3703	/**
3704	* Set the ISA IRQ for a device, but don't wait for EMT to process
3705	* the request when not called from EMT.
3706	*
3707	* @param pDevIns The device instance.
3708	* @param iIrq IRQ number to set.
3709	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3710	* @thread Any thread, but will involve the emulation thread.
3711	*/
3712	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3713
3714	/**
3715	* Send an MSI straight to the I/O APIC.
3716	*
3717	* @param pDevIns PCI device instance.
3718	* @param GCPhys Physical address MSI request was written.
3719	* @param uValue Value written.
3720	* @thread Any thread, but will involve the emulation thread.
3721	*/
3722	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
3723
3724	/**
3725	* Attaches a driver (chain) to the device.
3726	*
3727	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3728	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3729	*
3730	* @returns VBox status code.
3731	* @param pDevIns The device instance.
3732	* @param iLun The logical unit to attach.
3733	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3734	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3735	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3736	* for the live of the device instance.
3737	*/
3738	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3739	PPDMIBASE ppBaseInterface, const char pszDesc));
3740
3741	/**
3742	* Detaches an attached driver (chain) from the device again.
3743	*
3744	* @returns VBox status code.
3745	* @param pDevIns The device instance.
3746	* @param pDrvIns The driver instance to detach.
3747	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3748	*/
3749	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3750
3751	/** @name Exported PDM Queue Functions
3752	* @{ */
3753	/**
3754	* Create a queue.
3755	*
3756	* @returns VBox status code.
3757	* @param pDevIns The device instance.
3758	* @param cbItem The size of a queue item.
3759	* @param cItems The number of items in the queue.
3760	* @param cMilliesInterval The number of milliseconds between polling the queue.
3761	* If 0 then the emulation thread will be notified whenever an item arrives.
3762	* @param pfnCallback The consumer function.
3763	* @param fRZEnabled Set if the queue should work in RC and R0.
3764	* @param pszName The queue base name. The instance number will be
3765	* appended automatically.
3766	* @param ppQueue Where to store the queue pointer on success.
3767	* @thread The emulation thread.
3768	* @remarks The device critical section will NOT be entered before calling the
3769	* callback. No locks will be held, but for now it's safe to assume
3770	* that only one EMT will do queue callbacks at any one time.
3771	*/
3772	DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3773	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3774	PPDMQUEUE *ppQueue));
3775
3776	/**
3777	* Create a queue.
3778	*
3779	* @returns VBox status code.
3780	* @param pDevIns The device instance.
3781	* @param cbItem The size of a queue item.
3782	* @param cItems The number of items in the queue.
3783	* @param cMilliesInterval The number of milliseconds between polling the queue.
3784	* If 0 then the emulation thread will be notified whenever an item arrives.
3785	* @param pfnCallback The consumer function.
3786	* @param fRZEnabled Set if the queue should work in RC and R0.
3787	* @param pszName The queue base name. The instance number will be
3788	* appended automatically.
3789	* @param phQueue Where to store the queue handle on success.
3790	* @thread EMT(0)
3791	* @remarks The device critical section will NOT be entered before calling the
3792	* callback. No locks will be held, but for now it's safe to assume
3793	* that only one EMT will do queue callbacks at any one time.
3794	*/
3795	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3796	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3797	PDMQUEUEHANDLE *phQueue));
3798
3799	DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3800	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3801	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3802	DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3803	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3804	/** @} */
3805
3806	/** @name PDM Task
3807	* @{ */
3808	/**
3809	* Create an asynchronous ring-3 task.
3810	*
3811	* @returns VBox status code.
3812	* @param pDevIns The device instance.
3813	* @param fFlags PDMTASK_F_XXX
3814	* @param pszName The function name or similar. Used for statistics,
3815	* so no slashes.
3816	* @param pfnCallback The task function.
3817	* @param pvUser User argument for the task function.
3818	* @param phTask Where to return the task handle.
3819	* @thread EMT(0)
3820	*/
3821	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3822	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3823	/**
3824	* Triggers the running the given task.
3825	*
3826	* @returns VBox status code.
3827	* @retval VINF_ALREADY_POSTED is the task is already pending.
3828	* @param pDevIns The device instance.
3829	* @param hTask The task to trigger.
3830	* @thread Any thread.
3831	*/
3832	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3833	/** @} */
3834
3835	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3836	* These semaphores can be signalled from ring-0.
3837	* @{ */
3838	/** @sa SUPSemEventCreate */
3839	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3840	/** @sa SUPSemEventClose */
3841	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3842	/** @sa SUPSemEventSignal */
3843	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3844	/** @sa SUPSemEventWaitNoResume */
3845	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3846	/** @sa SUPSemEventWaitNsAbsIntr */
3847	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3848	/** @sa SUPSemEventWaitNsRelIntr */
3849	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3850	/** @sa SUPSemEventGetResolution */
3851	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3852	/** @} */
3853
3854	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3855	* These semaphores can be signalled from ring-0.
3856	* @{ */
3857	/** @sa SUPSemEventMultiCreate */
3858	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3859	/** @sa SUPSemEventMultiClose */
3860	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3861	/** @sa SUPSemEventMultiSignal */
3862	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3863	/** @sa SUPSemEventMultiReset */
3864	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3865	/** @sa SUPSemEventMultiWaitNoResume */
3866	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3867	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3868	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3869	/** @sa SUPSemEventMultiWaitNsRelIntr */
3870	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3871	/** @sa SUPSemEventMultiGetResolution */
3872	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3873	/** @} */
3874
3875	/**
3876	* Initializes a PDM critical section.
3877	*
3878	* The PDM critical sections are derived from the IPRT critical sections, but
3879	* works in RC and R0 as well.
3880	*
3881	* @returns VBox status code.
3882	* @param pDevIns The device instance.
3883	* @param pCritSect Pointer to the critical section.
3884	* @param SRC_POS Use RT_SRC_POS.
3885	* @param pszNameFmt Format string for naming the critical section.
3886	* For statistics and lock validation.
3887	* @param va Arguments for the format string.
3888	*/
3889	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3890	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3891
3892	/**
3893	* Gets the NOP critical section.
3894	*
3895	* @returns The ring-3 address of the NOP critical section.
3896	* @param pDevIns The device instance.
3897	*/
3898	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3899
3900	/**
3901	* Gets the NOP critical section.
3902	*
3903	* @returns The ring-0 address of the NOP critical section.
3904	* @param pDevIns The device instance.
3905	* @deprecated
3906	*/
3907	DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3908
3909	/**
3910	* Gets the NOP critical section.
3911	*
3912	* @returns The raw-mode context address of the NOP critical section.
3913	* @param pDevIns The device instance.
3914	* @deprecated
3915	*/
3916	DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3917
3918	/**
3919	* Changes the device level critical section from the automatically created
3920	* default to one desired by the device constructor.
3921	*
3922	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3923	* the additional contexts.
3924	*
3925	* @returns VBox status code.
3926	* @param pDevIns The device instance.
3927	* @param pCritSect The critical section to use. NULL is not
3928	* valid, instead use the NOP critical
3929	* section.
3930	*/
3931	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3932
3933	/** @name Exported PDM Critical Section Functions
3934	* @{ */
3935	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3936	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3937	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3938	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3939	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3940	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3941	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3942	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3943	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3944	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3945	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3946	/** @} */
3947
3948	/**
3949	* Creates a PDM thread.
3950	*
3951	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3952	* resuming, and destroying the thread as the VM state changes.
3953	*
3954	* @returns VBox status code.
3955	* @param pDevIns The device instance.
3956	* @param ppThread Where to store the thread 'handle'.
3957	* @param pvUser The user argument to the thread function.
3958	* @param pfnThread The thread function.
3959	* @param pfnWakeup The wakup callback. This is called on the EMT
3960	* thread when a state change is pending.
3961	* @param cbStack See RTThreadCreate.
3962	* @param enmType See RTThreadCreate.
3963	* @param pszName See RTThreadCreate.
3964	* @remarks The device critical section will NOT be entered prior to invoking
3965	* the function pointers.
3966	*/
3967	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3968	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3969
3970	/**
3971	* Set up asynchronous handling of a suspend, reset or power off notification.
3972	*
3973	* This shall only be called when getting the notification. It must be called
3974	* for each one.
3975	*
3976	* @returns VBox status code.
3977	* @param pDevIns The device instance.
3978	* @param pfnAsyncNotify The callback.
3979	* @thread EMT(0)
3980	* @remarks The caller will enter the device critical section prior to invoking
3981	* the callback.
3982	*/
3983	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3984
3985	/**
3986	* Notify EMT(0) that the device has completed the asynchronous notification
3987	* handling.
3988	*
3989	* This can be called at any time, spurious calls will simply be ignored.
3990	*
3991	* @param pDevIns The device instance.
3992	* @thread Any
3993	*/
3994	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3995
3996	/**
3997	* Register the RTC device.
3998	*
3999	* @returns VBox status code.
4000	* @param pDevIns The device instance.
4001	* @param pRtcReg Pointer to a RTC registration structure.
4002	* @param ppRtcHlp Where to store the pointer to the helper
4003	* functions.
4004	*/
4005	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4006
4007	/**
4008	* Register a PCI Bus.
4009	*
4010	* @returns VBox status code, but the positive values 0..31 are used to indicate
4011	* bus number rather than informational status codes.
4012	* @param pDevIns The device instance.
4013	* @param pPciBusReg Pointer to PCI bus registration structure.
4014	* @param ppPciHlp Where to store the pointer to the PCI Bus
4015	* helpers.
4016	* @param piBus Where to return the PDM bus number. Optional.
4017	*/
4018	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4019	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4020
4021	/**
4022	* Register the PIC device.
4023	*
4024	* @returns VBox status code.
4025	* @param pDevIns The device instance.
4026	* @param pPicReg Pointer to a PIC registration structure.
4027	* @param ppPicHlpR3 Where to store the pointer to the PIC HC
4028	* helpers.
4029	*/
4030	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3));
4031
4032	/**
4033	* Register the APIC device.
4034	*
4035	* @returns VBox status code.
4036	* @param pDevIns The device instance.
4037	*/
4038	DECLR3CALLBACKMEMBER(int, pfnAPICRegister,(PPDMDEVINS pDevIns));
4039
4040	/**
4041	* Register the I/O APIC device.
4042	*
4043	* @returns VBox status code.
4044	* @param pDevIns The device instance.
4045	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4046	* @param ppIoApicHlpR3 Where to store the pointer to the IOAPIC
4047	* helpers.
4048	*/
4049	DECLR3CALLBACKMEMBER(int, pfnIOAPICRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3));
4050
4051	/**
4052	* Register the HPET device.
4053	*
4054	* @returns VBox status code.
4055	* @param pDevIns The device instance.
4056	* @param pHpetReg Pointer to a HPET registration structure.
4057	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4058	* helpers.
4059	*/
4060	DECLR3CALLBACKMEMBER(int, pfnHPETRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4061
4062	/**
4063	* Register a raw PCI device.
4064	*
4065	* @returns VBox status code.
4066	* @param pDevIns The device instance.
4067	* @param pPciRawReg Pointer to a raw PCI registration structure.
4068	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4069	* device helpers.
4070	*/
4071	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4072
4073	/**
4074	* Register the DMA device.
4075	*
4076	* @returns VBox status code.
4077	* @param pDevIns The device instance.
4078	* @param pDmacReg Pointer to a DMAC registration structure.
4079	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4080	*/
4081	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4082
4083	/**
4084	* Register transfer function for DMA channel.
4085	*
4086	* @returns VBox status code.
4087	* @param pDevIns The device instance.
4088	* @param uChannel Channel number.
4089	* @param pfnTransferHandler Device specific transfer callback function.
4090	* @param pvUser User pointer to pass to the callback.
4091	* @thread EMT
4092	*/
4093	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4094
4095	/**
4096	* Read memory.
4097	*
4098	* @returns VBox status code.
4099	* @param pDevIns The device instance.
4100	* @param uChannel Channel number.
4101	* @param pvBuffer Pointer to target buffer.
4102	* @param off DMA position.
4103	* @param cbBlock Block size.
4104	* @param pcbRead Where to store the number of bytes which was
4105	* read. optional.
4106	* @thread EMT
4107	*/
4108	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4109
4110	/**
4111	* Write memory.
4112	*
4113	* @returns VBox status code.
4114	* @param pDevIns The device instance.
4115	* @param uChannel Channel number.
4116	* @param pvBuffer Memory to write.
4117	* @param off DMA position.
4118	* @param cbBlock Block size.
4119	* @param pcbWritten Where to store the number of bytes which was
4120	* written. optional.
4121	* @thread EMT
4122	*/
4123	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4124
4125	/**
4126	* Set the DREQ line.
4127	*
4128	* @returns VBox status code.
4129	* @param pDevIns Device instance.
4130	* @param uChannel Channel number.
4131	* @param uLevel Level of the line.
4132	* @thread EMT
4133	*/
4134	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4135
4136	/**
4137	* Get channel mode.
4138	*
4139	* @returns Channel mode. See specs.
4140	* @param pDevIns The device instance.
4141	* @param uChannel Channel number.
4142	* @thread EMT
4143	*/
4144	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4145
4146	/**
4147	* Schedule DMA execution.
4148	*
4149	* @param pDevIns The device instance.
4150	* @thread Any thread.
4151	*/
4152	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4153
4154	/**
4155	* Write CMOS value and update the checksum(s).
4156	*
4157	* @returns VBox status code.
4158	* @param pDevIns The device instance.
4159	* @param iReg The CMOS register index.
4160	* @param u8Value The CMOS register value.
4161	* @thread EMT
4162	*/
4163	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4164
4165	/**
4166	* Read CMOS value.
4167	*
4168	* @returns VBox status code.
4169	* @param pDevIns The device instance.
4170	* @param iReg The CMOS register index.
4171	* @param pu8Value Where to store the CMOS register value.
4172	* @thread EMT
4173	*/
4174	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4175
4176	/**
4177	* Assert that the current thread is the emulation thread.
4178	*
4179	* @returns True if correct.
4180	* @returns False if wrong.
4181	* @param pDevIns The device instance.
4182	* @param pszFile Filename of the assertion location.
4183	* @param iLine The linenumber of the assertion location.
4184	* @param pszFunction Function of the assertion location.
4185	*/
4186	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4187
4188	/**
4189	* Assert that the current thread is NOT the emulation thread.
4190	*
4191	* @returns True if correct.
4192	* @returns False if wrong.
4193	* @param pDevIns The device instance.
4194	* @param pszFile Filename of the assertion location.
4195	* @param iLine The linenumber of the assertion location.
4196	* @param pszFunction Function of the assertion location.
4197	*/
4198	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4199
4200	/**
4201	* Resolves the symbol for a raw-mode context interface.
4202	*
4203	* @returns VBox status code.
4204	* @param pDevIns The device instance.
4205	* @param pvInterface The interface structure.
4206	* @param cbInterface The size of the interface structure.
4207	* @param pszSymPrefix What to prefix the symbols in the list with
4208	* before resolving them. This must start with
4209	* 'dev' and contain the driver name.
4210	* @param pszSymList List of symbols corresponding to the interface.
4211	* There is generally a there is generally a define
4212	* holding this list associated with the interface
4213	* definition (INTERFACE_SYM_LIST). For more
4214	* details see PDMR3LdrGetInterfaceSymbols.
4215	* @thread EMT
4216	*/
4217	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4218	const char pszSymPrefix, const char pszSymList));
4219
4220	/**
4221	* Resolves the symbol for a ring-0 context interface.
4222	*
4223	* @returns VBox status code.
4224	* @param pDevIns The device instance.
4225	* @param pvInterface The interface structure.
4226	* @param cbInterface The size of the interface structure.
4227	* @param pszSymPrefix What to prefix the symbols in the list with
4228	* before resolving them. This must start with
4229	* 'dev' and contain the driver name.
4230	* @param pszSymList List of symbols corresponding to the interface.
4231	* There is generally a there is generally a define
4232	* holding this list associated with the interface
4233	* definition (INTERFACE_SYM_LIST). For more
4234	* details see PDMR3LdrGetInterfaceSymbols.
4235	* @thread EMT
4236	*/
4237	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4238	const char pszSymPrefix, const char pszSymList));
4239
4240	/**
4241	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4242	*
4243	* @returns VBox status code.
4244	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4245	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4246	*
4247	* @param pDevIns The device instance.
4248	* @param uOperation The operation to perform.
4249	* @param u64Arg 64-bit integer argument.
4250	* @thread EMT
4251	*/
4252	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4253
4254	/**
4255	* Gets the reason for the most recent VM suspend.
4256	*
4257	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4258	* suspend has been made or if the pDevIns is invalid.
4259	* @param pDevIns The device instance.
4260	*/
4261	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4262
4263	/**
4264	* Gets the reason for the most recent VM resume.
4265	*
4266	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4267	* resume has been made or if the pDevIns is invalid.
4268	* @param pDevIns The device instance.
4269	*/
4270	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4271
4272	/**
4273	* Requests the mapping of multiple guest page into ring-3.
4274	*
4275	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4276	* ASAP to release them.
4277	*
4278	* This API will assume your intention is to write to the pages, and will
4279	* therefore replace shared and zero pages. If you do not intend to modify the
4280	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4281	*
4282	* @returns VBox status code.
4283	* @retval VINF_SUCCESS on success.
4284	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4285	* backing or if any of the pages the page has any active access
4286	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4287	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4288	* an invalid physical address.
4289	*
4290	* @param pDevIns The device instance.
4291	* @param cPages Number of pages to lock.
4292	* @param paGCPhysPages The guest physical address of the pages that
4293	* should be mapped (@a cPages entries).
4294	* @param fFlags Flags reserved for future use, MBZ.
4295	* @param papvPages Where to store the ring-3 mapping addresses
4296	* corresponding to @a paGCPhysPages.
4297	* @param paLocks Where to store the locking information that
4298	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4299	* in length).
4300	*
4301	* @remark Avoid calling this API from within critical sections (other than the
4302	* PGM one) because of the deadlock risk when we have to delegating the
4303	* task to an EMT.
4304	* @thread Any.
4305	* @since 6.0.6
4306	*/
4307	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4308	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4309
4310	/**
4311	* Requests the mapping of multiple guest page into ring-3, for reading only.
4312	*
4313	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4314	* ASAP to release them.
4315	*
4316	* @returns VBox status code.
4317	* @retval VINF_SUCCESS on success.
4318	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4319	* backing or if any of the pages the page has an active ALL access
4320	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4321	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4322	* an invalid physical address.
4323	*
4324	* @param pDevIns The device instance.
4325	* @param cPages Number of pages to lock.
4326	* @param paGCPhysPages The guest physical address of the pages that
4327	* should be mapped (@a cPages entries).
4328	* @param fFlags Flags reserved for future use, MBZ.
4329	* @param papvPages Where to store the ring-3 mapping addresses
4330	* corresponding to @a paGCPhysPages.
4331	* @param paLocks Where to store the lock information that
4332	* pfnPhysReleasePageMappingLock needs (@a cPages
4333	* in length).
4334	*
4335	* @remark Avoid calling this API from within critical sections.
4336	* @thread Any.
4337	* @since 6.0.6
4338	*/
4339	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4340	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4341
4342	/**
4343	* Release the mappings of multiple guest pages.
4344	*
4345	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4346	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4347	*
4348	* @param pDevIns The device instance.
4349	* @param cPages Number of pages to unlock.
4350	* @param paLocks The lock structures initialized by the mapping
4351	* function (@a cPages in length).
4352	* @thread Any.
4353	* @since 6.0.6
4354	*/
4355	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4356
4357	/**
4358	* Changes the number of an MMIO2 or pre-registered MMIO region.
4359	*
4360	* This should only be used to deal with saved state problems, so there is no
4361	* convenience inline wrapper for this method.
4362	*
4363	* @returns VBox status code.
4364	* @param pDevIns The device instance.
4365	* @param pPciDev The PCI device the region is associated with, or
4366	* NULL if not associated with any.
4367	* @param iRegion The region.
4368	* @param iNewRegion The new region index.
4369	*
4370	* @sa @bugref{9359}
4371	*/
4372	DECLR3CALLBACKMEMBER(int, pfnMMIOExChangeRegionNo,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4373	uint32_t iNewRegion));
4374
4375	/** Space reserved for future members.
4376	* @{ */
4377	DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4378	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4379	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4380	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4381	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4382	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4383	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4384	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4385	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4386	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4387	/** @} */
4388
4389
4390	/** API available to trusted devices only.
4391	*
4392	* These APIs are providing unrestricted access to the guest and the VM,
4393	* or they are interacting intimately with PDM.
4394	*
4395	* @{
4396	*/
4397
4398	/**
4399	* Gets the user mode VM handle. Restricted API.
4400	*
4401	* @returns User mode VM Handle.
4402	* @param pDevIns The device instance.
4403	*/
4404	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4405
4406	/**
4407	* Gets the global VM handle. Restricted API.
4408	*
4409	* @returns VM Handle.
4410	* @param pDevIns The device instance.
4411	*/
4412	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4413
4414	/**
4415	* Gets the VMCPU handle. Restricted API.
4416	*
4417	* @returns VMCPU Handle.
4418	* @param pDevIns The device instance.
4419	*/
4420	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4421
4422	/**
4423	* The the VM CPU ID of the current thread (restricted API).
4424	*
4425	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4426	* @param pDevIns The device instance.
4427	*/
4428	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4429
4430	/**
4431	* Registers the VMM device heap or notifies about mapping/unmapping.
4432	*
4433	* This interface serves three purposes:
4434	*
4435	* -# Register the VMM device heap during device construction
4436	* for the HM to use.
4437	* -# Notify PDM/HM that it's mapped into guest address
4438	* space (i.e. usable).
4439	* -# Notify PDM/HM that it is being unmapped from the guest
4440	* address space (i.e. not usable).
4441	*
4442	* @returns VBox status code.
4443	* @param pDevIns The device instance.
4444	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4445	* not mapped.
4446	* @param pvHeap Ring 3 heap pointer.
4447	* @param cbHeap Size of the heap.
4448	* @thread EMT.
4449	*/
4450	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4451
4452	/**
4453	* Registers the firmware (BIOS, EFI) device with PDM.
4454	*
4455	* The firmware provides a callback table and gets a special PDM helper table.
4456	* There can only be one firmware device for a VM.
4457	*
4458	* @returns VBox status code.
4459	* @param pDevIns The device instance.
4460	* @param pFwReg Firmware registration structure.
4461	* @param ppFwHlp Where to return the firmware helper structure.
4462	* @remarks Only valid during device construction.
4463	* @thread EMT(0)
4464	*/
4465	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4466
4467	/**
4468	* Resets the VM.
4469	*
4470	* @returns The appropriate VBox status code to pass around on reset.
4471	* @param pDevIns The device instance.
4472	* @param fFlags PDMVMRESET_F_XXX flags.
4473	* @thread The emulation thread.
4474	*/
4475	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4476
4477	/**
4478	* Suspends the VM.
4479	*
4480	* @returns The appropriate VBox status code to pass around on suspend.
4481	* @param pDevIns The device instance.
4482	* @thread The emulation thread.
4483	*/
4484	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4485
4486	/**
4487	* Suspends, saves and powers off the VM.
4488	*
4489	* @returns The appropriate VBox status code to pass around.
4490	* @param pDevIns The device instance.
4491	* @thread An emulation thread.
4492	*/
4493	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4494
4495	/**
4496	* Power off the VM.
4497	*
4498	* @returns The appropriate VBox status code to pass around on power off.
4499	* @param pDevIns The device instance.
4500	* @thread The emulation thread.
4501	*/
4502	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4503
4504	/**
4505	* Checks if the Gate A20 is enabled or not.
4506	*
4507	* @returns true if A20 is enabled.
4508	* @returns false if A20 is disabled.
4509	* @param pDevIns The device instance.
4510	* @thread The emulation thread.
4511	*/
4512	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4513
4514	/**
4515	* Enables or disables the Gate A20.
4516	*
4517	* @param pDevIns The device instance.
4518	* @param fEnable Set this flag to enable the Gate A20; clear it
4519	* to disable.
4520	* @thread The emulation thread.
4521	*/
4522	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4523
4524	/**
4525	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4526	* thread.
4527	*
4528	* @param pDevIns The device instance.
4529	* @param iLeaf The CPUID leaf to get.
4530	* @param pEax Where to store the EAX value.
4531	* @param pEbx Where to store the EBX value.
4532	* @param pEcx Where to store the ECX value.
4533	* @param pEdx Where to store the EDX value.
4534	* @thread EMT.
4535	*/
4536	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4537
4538	/**
4539	* Get the current virtual clock time in a VM. The clock frequency must be
4540	* queried separately.
4541	*
4542	* @returns Current clock time.
4543	* @param pDevIns The device instance.
4544	*/
4545	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4546
4547	/**
4548	* Get the frequency of the virtual clock.
4549	*
4550	* @returns The clock frequency (not variable at run-time).
4551	* @param pDevIns The device instance.
4552	*/
4553	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4554
4555	/**
4556	* Get the current virtual clock time in a VM, in nanoseconds.
4557	*
4558	* @returns Current clock time (in ns).
4559	* @param pDevIns The device instance.
4560	*/
4561	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4562
4563	/**
4564	* Gets the support driver session.
4565	*
4566	* This is intended for working with the semaphore API.
4567	*
4568	* @returns Support driver session handle.
4569	* @param pDevIns The device instance.
4570	*/
4571	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4572
4573	/**
4574	* Queries a generic object from the VMM user.
4575	*
4576	* @returns Pointer to the object if found, NULL if not.
4577	* @param pDevIns The device instance.
4578	* @param pUuid The UUID of what's being queried. The UUIDs and
4579	* the usage conventions are defined by the user.
4580	*
4581	* @note It is strictly forbidden to call this internally in VBox! This
4582	* interface is exclusively for hacks in externally developed devices.
4583	*/
4584	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4585
4586	/** @} */
4587
4588	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4589	uint32_t u32TheEnd;
4590	} PDMDEVHLPR3;
4591	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4592	/** Pointer to the R3 PDM Device API. */
4593	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4594	/** Pointer to the R3 PDM Device API, const variant. */
4595	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4596
4597
4598	/**
4599	* PDM Device API - RC Variant.
4600	*/
4601	typedef struct PDMDEVHLPRC
4602	{
4603	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4604	uint32_t u32Version;
4605
4606	/**
4607	* Sets up raw-mode context callback handlers for an I/O port range.
4608	*
4609	* The range must have been registered in ring-3 first using
4610	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4611	*
4612	* @returns VBox status.
4613	* @param pDevIns The device instance to register the ports with.
4614	* @param hIoPorts The I/O port range handle.
4615	* @param pfnOut Pointer to function which is gonna handle OUT
4616	* operations. Optional.
4617	* @param pfnIn Pointer to function which is gonna handle IN operations.
4618	* Optional.
4619	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4620	* operations. Optional.
4621	* @param pfnInStr Pointer to function which is gonna handle string IN
4622	* operations. Optional.
4623	* @param pvUser User argument to pass to the callbacks.
4624	*
4625	* @remarks Caller enters the device critical section prior to invoking the
4626	* registered callback methods.
4627	*
4628	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4629	* PDMDevHlpIoPortUnmap.
4630	*/
4631	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4632	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4633	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4634	void *pvUser));
4635
4636	/**
4637	* Sets up raw-mode context callback handlers for an MMIO region.
4638	*
4639	* The region must have been registered in ring-3 first using
4640	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4641	*
4642	* @returns VBox status.
4643	* @param pDevIns The device instance to register the ports with.
4644	* @param hRegion The MMIO region handle.
4645	* @param pfnWrite Pointer to function which is gonna handle Write
4646	* operations.
4647	* @param pfnRead Pointer to function which is gonna handle Read
4648	* operations.
4649	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4650	* operations. (optional)
4651	* @param pvUser User argument to pass to the callbacks.
4652	*
4653	* @remarks Caller enters the device critical section prior to invoking the
4654	* registered callback methods.
4655	*
4656	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4657	* PDMDevHlpMmioUnmap.
4658	*/
4659	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4660	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4661
4662	/**
4663	* Sets up a raw-mode mapping for an MMIO2 region.
4664	*
4665	* The region must have been created in ring-3 first using
4666	* PDMDevHlpMmio2Create().
4667	*
4668	* @returns VBox status.
4669	* @param pDevIns The device instance to register the ports with.
4670	* @param hRegion The MMIO2 region handle.
4671	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4672	* @param cbSub Number of bytes to map into raw-mode. Must be page
4673	* aligned. Zero is an alias for everything.
4674	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4675	* @thread EMT(0)
4676	* @note Only available at VM creation time.
4677	*
4678	* @sa PDMDevHlpMmio2Create().
4679	*/
4680	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4681	size_t offSub, size_t cbSub, void **ppvMapping));
4682
4683	/**
4684	* Bus master physical memory read from the given PCI device.
4685	*
4686	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4687	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4688	* @param pDevIns The device instance.
4689	* @param pPciDev The PCI device structure. If NULL the default
4690	* PCI device for this device instance is used.
4691	* @param GCPhys Physical address start reading from.
4692	* @param pvBuf Where to put the read bits.
4693	* @param cbRead How many bytes to read.
4694	* @thread Any thread, but the call may involve the emulation thread.
4695	*/
4696	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4697	void *pvBuf, size_t cbRead));
4698
4699	/**
4700	* Bus master physical memory write from the given PCI device.
4701	*
4702	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4703	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4704	* @param pDevIns The device instance.
4705	* @param pPciDev The PCI device structure. If NULL the default
4706	* PCI device for this device instance is used.
4707	* @param GCPhys Physical address to write to.
4708	* @param pvBuf What to write.
4709	* @param cbWrite How many bytes to write.
4710	* @thread Any thread, but the call may involve the emulation thread.
4711	*/
4712	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4713	const void *pvBuf, size_t cbWrite));
4714
4715	/**
4716	* Set the IRQ for the given PCI device.
4717	*
4718	* @param pDevIns Device instance.
4719	* @param pPciDev The PCI device structure. If NULL the default
4720	* PCI device for this device instance is used.
4721	* @param iIrq IRQ number to set.
4722	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4723	* @thread Any thread, but will involve the emulation thread.
4724	*/
4725	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4726
4727	/**
4728	* Set ISA IRQ for a device.
4729	*
4730	* @param pDevIns Device instance.
4731	* @param iIrq IRQ number to set.
4732	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4733	* @thread Any thread, but will involve the emulation thread.
4734	*/
4735	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4736
4737	/**
4738	* Send an MSI straight to the I/O APIC.
4739	*
4740	* @param pDevIns PCI device instance.
4741	* @param GCPhys Physical address MSI request was written.
4742	* @param uValue Value written.
4743	* @thread Any thread, but will involve the emulation thread.
4744	*/
4745	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
4746
4747	/**
4748	* Read physical memory.
4749	*
4750	* @returns VINF_SUCCESS (for now).
4751	* @param pDevIns Device instance.
4752	* @param GCPhys Physical address start reading from.
4753	* @param pvBuf Where to put the read bits.
4754	* @param cbRead How many bytes to read.
4755	*/
4756	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
4757
4758	/**
4759	* Write to physical memory.
4760	*
4761	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4762	* @param pDevIns Device instance.
4763	* @param GCPhys Physical address to write to.
4764	* @param pvBuf What to write.
4765	* @param cbWrite How many bytes to write.
4766	*/
4767	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
4768
4769	/**
4770	* Checks if the Gate A20 is enabled or not.
4771	*
4772	* @returns true if A20 is enabled.
4773	* @returns false if A20 is disabled.
4774	* @param pDevIns Device instance.
4775	* @thread The emulation thread.
4776	*/
4777	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4778
4779	/**
4780	* Gets the VM state.
4781	*
4782	* @returns VM state.
4783	* @param pDevIns The device instance.
4784	* @thread Any thread (just keep in mind that it's volatile info).
4785	*/
4786	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4787
4788	/**
4789	* Set the VM error message
4790	*
4791	* @returns rc.
4792	* @param pDevIns Driver instance.
4793	* @param rc VBox status code.
4794	* @param SRC_POS Use RT_SRC_POS.
4795	* @param pszFormat Error message format string.
4796	* @param ... Error message arguments.
4797	*/
4798	DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4799	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4800
4801	/**
4802	* Set the VM error message
4803	*
4804	* @returns rc.
4805	* @param pDevIns Driver instance.
4806	* @param rc VBox status code.
4807	* @param SRC_POS Use RT_SRC_POS.
4808	* @param pszFormat Error message format string.
4809	* @param va Error message arguments.
4810	*/
4811	DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4812	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4813
4814	/**
4815	* Set the VM runtime error message
4816	*
4817	* @returns VBox status code.
4818	* @param pDevIns Device instance.
4819	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4820	* @param pszErrorId Error ID string.
4821	* @param pszFormat Error message format string.
4822	* @param ... Error message arguments.
4823	*/
4824	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4825	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4826
4827	/**
4828	* Set the VM runtime error message
4829	*
4830	* @returns VBox status code.
4831	* @param pDevIns Device instance.
4832	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4833	* @param pszErrorId Error ID string.
4834	* @param pszFormat Error message format string.
4835	* @param va Error message arguments.
4836	*/
4837	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4838	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4839
4840	/**
4841	* Gets the VM handle. Restricted API.
4842	*
4843	* @returns VM Handle.
4844	* @param pDevIns Device instance.
4845	*/
4846	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4847
4848	/**
4849	* Gets the VMCPU handle. Restricted API.
4850	*
4851	* @returns VMCPU Handle.
4852	* @param pDevIns The device instance.
4853	*/
4854	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4855
4856	/**
4857	* The the VM CPU ID of the current thread (restricted API).
4858	*
4859	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4860	* @param pDevIns The device instance.
4861	*/
4862	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4863
4864	/**
4865	* Get the current virtual clock time in a VM. The clock frequency must be
4866	* queried separately.
4867	*
4868	* @returns Current clock time.
4869	* @param pDevIns The device instance.
4870	*/
4871	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4872
4873	/**
4874	* Get the frequency of the virtual clock.
4875	*
4876	* @returns The clock frequency (not variable at run-time).
4877	* @param pDevIns The device instance.
4878	*/
4879	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4880
4881	/**
4882	* Get the current virtual clock time in a VM, in nanoseconds.
4883	*
4884	* @returns Current clock time (in ns).
4885	* @param pDevIns The device instance.
4886	*/
4887	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4888
4889	/**
4890	* Gets the NOP critical section.
4891	*
4892	* @returns The ring-3 address of the NOP critical section.
4893	* @param pDevIns The device instance.
4894	*/
4895	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4896
4897	/**
4898	* Changes the device level critical section from the automatically created
4899	* default to one desired by the device constructor.
4900	*
4901	* Must first be done in ring-3.
4902	*
4903	* @returns VBox status code.
4904	* @param pDevIns The device instance.
4905	* @param pCritSect The critical section to use. NULL is not
4906	* valid, instead use the NOP critical
4907	* section.
4908	*/
4909	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4910
4911	/** @name Exported PDM Critical Section Functions
4912	* @{ */
4913	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4914	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4915	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4916	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4917	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4918	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4919	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4920	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4921	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4922	/** @} */
4923
4924	/**
4925	* Gets the trace buffer handle.
4926	*
4927	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4928	* really inteded for direct usage, thus no inline wrapper function.
4929	*
4930	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4931	* @param pDevIns The device instance.
4932	*/
4933	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4934
4935	/**
4936	* Sets up the PCI bus for the raw-mode context.
4937	*
4938	* This must be called after ring-3 has registered the PCI bus using
4939	* PDMDevHlpPCIBusRegister().
4940	*
4941	* @returns VBox status code.
4942	* @param pDevIns The device instance.
4943	* @param pPciBusReg The PCI bus registration information for raw-mode,
4944	* considered volatile.
4945	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4946	*/
4947	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4948
4949	/** Space reserved for future members.
4950	* @{ */
4951	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4952	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4953	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4954	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4955	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4956	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4957	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4958	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4959	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4960	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4961	/** @} */
4962
4963	/** Just a safety precaution. */
4964	uint32_t u32TheEnd;
4965	} PDMDEVHLPRC;
4966	/** Pointer PDM Device RC API. */
4967	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4968	/** Pointer PDM Device RC API. */
4969	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4970
4971	/** Current PDMDEVHLP version number. */
4972	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 9, 0)
4973
4974
4975	/**
4976	* PDM Device API - R0 Variant.
4977	*/
4978	typedef struct PDMDEVHLPR0
4979	{
4980	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4981	uint32_t u32Version;
4982
4983	/**
4984	* Sets up ring-0 callback handlers for an I/O port range.
4985	*
4986	* The range must have been created in ring-3 first using
4987	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4988	*
4989	* @returns VBox status.
4990	* @param pDevIns The device instance to register the ports with.
4991	* @param hIoPorts The I/O port range handle.
4992	* @param pfnOut Pointer to function which is gonna handle OUT
4993	* operations. Optional.
4994	* @param pfnIn Pointer to function which is gonna handle IN operations.
4995	* Optional.
4996	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4997	* operations. Optional.
4998	* @param pfnInStr Pointer to function which is gonna handle string IN
4999	* operations. Optional.
5000	* @param pvUser User argument to pass to the callbacks.
5001	*
5002	* @remarks Caller enters the device critical section prior to invoking the
5003	* registered callback methods.
5004	*
5005	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5006	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5007	*/
5008	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5009	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5010	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5011	void *pvUser));
5012
5013	/**
5014	* Sets up ring-0 callback handlers for an MMIO region.
5015	*
5016	* The region must have been created in ring-3 first using
5017	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5018	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5019	*
5020	* @returns VBox status.
5021	* @param pDevIns The device instance to register the ports with.
5022	* @param hRegion The MMIO region handle.
5023	* @param pfnWrite Pointer to function which is gonna handle Write
5024	* operations.
5025	* @param pfnRead Pointer to function which is gonna handle Read
5026	* operations.
5027	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5028	* operations. (optional)
5029	* @param pvUser User argument to pass to the callbacks.
5030	*
5031	* @remarks Caller enters the device critical section prior to invoking the
5032	* registered callback methods.
5033	*
5034	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5035	* PDMDevHlpMmioUnmap().
5036	*/
5037	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5038	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5039
5040	/**
5041	* Sets up a ring-0 mapping for an MMIO2 region.
5042	*
5043	* The region must have been created in ring-3 first using
5044	* PDMDevHlpMmio2Create().
5045	*
5046	* @returns VBox status.
5047	* @param pDevIns The device instance to register the ports with.
5048	* @param hRegion The MMIO2 region handle.
5049	* @param offSub Start of what to map into ring-0. Must be page aligned.
5050	* @param cbSub Number of bytes to map into ring-0. Must be page
5051	* aligned. Zero is an alias for everything.
5052	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5053	*
5054	* @thread EMT(0)
5055	* @note Only available at VM creation time.
5056	*
5057	* @sa PDMDevHlpMmio2Create().
5058	*/
5059	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5060	void **ppvMapping));
5061
5062	/**
5063	* Bus master physical memory read from the given PCI device.
5064	*
5065	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5066	* VERR_EM_MEMORY.
5067	* @param pDevIns The device instance.
5068	* @param pPciDev The PCI device structure. If NULL the default
5069	* PCI device for this device instance is used.
5070	* @param GCPhys Physical address start reading from.
5071	* @param pvBuf Where to put the read bits.
5072	* @param cbRead How many bytes to read.
5073	* @thread Any thread, but the call may involve the emulation thread.
5074	*/
5075	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5076	void *pvBuf, size_t cbRead));
5077
5078	/**
5079	* Bus master physical memory write from the given PCI device.
5080	*
5081	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5082	* VERR_EM_MEMORY.
5083	* @param pDevIns The device instance.
5084	* @param pPciDev The PCI device structure. If NULL the default
5085	* PCI device for this device instance is used.
5086	* @param GCPhys Physical address to write to.
5087	* @param pvBuf What to write.
5088	* @param cbWrite How many bytes to write.
5089	* @thread Any thread, but the call may involve the emulation thread.
5090	*/
5091	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5092	const void *pvBuf, size_t cbWrite));
5093
5094	/**
5095	* Set the IRQ for the given PCI device.
5096	*
5097	* @param pDevIns Device instance.
5098	* @param pPciDev The PCI device structure. If NULL the default
5099	* PCI device for this device instance is used.
5100	* @param iIrq IRQ number to set.
5101	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5102	* @thread Any thread, but will involve the emulation thread.
5103	*/
5104	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5105
5106	/**
5107	* Set ISA IRQ for a device.
5108	*
5109	* @param pDevIns Device instance.
5110	* @param iIrq IRQ number to set.
5111	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5112	* @thread Any thread, but will involve the emulation thread.
5113	*/
5114	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5115
5116	/**
5117	* Send an MSI straight to the I/O APIC.
5118	*
5119	* @param pDevIns PCI device instance.
5120	* @param GCPhys Physical address MSI request was written.
5121	* @param uValue Value written.
5122	* @thread Any thread, but will involve the emulation thread.
5123	*/
5124	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue));
5125
5126	/**
5127	* Read physical memory.
5128	*
5129	* @returns VINF_SUCCESS (for now).
5130	* @param pDevIns Device instance.
5131	* @param GCPhys Physical address start reading from.
5132	* @param pvBuf Where to put the read bits.
5133	* @param cbRead How many bytes to read.
5134	*/
5135	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
5136
5137	/**
5138	* Write to physical memory.
5139	*
5140	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5141	* @param pDevIns Device instance.
5142	* @param GCPhys Physical address to write to.
5143	* @param pvBuf What to write.
5144	* @param cbWrite How many bytes to write.
5145	*/
5146	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
5147
5148	/**
5149	* Checks if the Gate A20 is enabled or not.
5150	*
5151	* @returns true if A20 is enabled.
5152	* @returns false if A20 is disabled.
5153	* @param pDevIns Device instance.
5154	* @thread The emulation thread.
5155	*/
5156	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5157
5158	/**
5159	* Gets the VM state.
5160	*
5161	* @returns VM state.
5162	* @param pDevIns The device instance.
5163	* @thread Any thread (just keep in mind that it's volatile info).
5164	*/
5165	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5166
5167	/**
5168	* Set the VM error message
5169	*
5170	* @returns rc.
5171	* @param pDevIns Driver instance.
5172	* @param rc VBox status code.
5173	* @param SRC_POS Use RT_SRC_POS.
5174	* @param pszFormat Error message format string.
5175	* @param ... Error message arguments.
5176	*/
5177	DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5178	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
5179
5180	/**
5181	* Set the VM error message
5182	*
5183	* @returns rc.
5184	* @param pDevIns Driver instance.
5185	* @param rc VBox status code.
5186	* @param SRC_POS Use RT_SRC_POS.
5187	* @param pszFormat Error message format string.
5188	* @param va Error message arguments.
5189	*/
5190	DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5191	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
5192
5193	/**
5194	* Set the VM runtime error message
5195	*
5196	* @returns VBox status code.
5197	* @param pDevIns Device instance.
5198	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5199	* @param pszErrorId Error ID string.
5200	* @param pszFormat Error message format string.
5201	* @param ... Error message arguments.
5202	*/
5203	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5204	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
5205
5206	/**
5207	* Set the VM runtime error message
5208	*
5209	* @returns VBox status code.
5210	* @param pDevIns Device instance.
5211	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5212	* @param pszErrorId Error ID string.
5213	* @param pszFormat Error message format string.
5214	* @param va Error message arguments.
5215	*/
5216	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5217	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5218
5219	/**
5220	* Gets the VM handle. Restricted API.
5221	*
5222	* @returns VM Handle.
5223	* @param pDevIns Device instance.
5224	*/
5225	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5226
5227	/**
5228	* Gets the VMCPU handle. Restricted API.
5229	*
5230	* @returns VMCPU Handle.
5231	* @param pDevIns The device instance.
5232	*/
5233	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5234
5235	/**
5236	* The the VM CPU ID of the current thread (restricted API).
5237	*
5238	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5239	* @param pDevIns The device instance.
5240	*/
5241	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5242
5243	/**
5244	* Translates a timer handle to a pointer.
5245	*
5246	* @returns The time address.
5247	* @param pDevIns The device instance.
5248	* @param hTimer The timer handle.
5249	*/
5250	DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5251
5252	/** @name Timer handle method wrappers
5253	* @{ */
5254	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5255	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5256	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5257	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5258	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5259	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5260	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5261	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5262	DECLR0CALLBACKMEMBER(int, pfnTimerLock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5263	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5264	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5265	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5266	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5267	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5268	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5269	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5270	DECLR0CALLBACKMEMBER(void, pfnTimerUnlock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5271	/** @} */
5272
5273	/**
5274	* Get the current virtual clock time in a VM. The clock frequency must be
5275	* queried separately.
5276	*
5277	* @returns Current clock time.
5278	* @param pDevIns The device instance.
5279	*/
5280	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5281
5282	/**
5283	* Get the frequency of the virtual clock.
5284	*
5285	* @returns The clock frequency (not variable at run-time).
5286	* @param pDevIns The device instance.
5287	*/
5288	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5289
5290	/**
5291	* Get the current virtual clock time in a VM, in nanoseconds.
5292	*
5293	* @returns Current clock time (in ns).
5294	* @param pDevIns The device instance.
5295	*/
5296	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5297
5298	/** @name Exported PDM Queue Functions
5299	* @{ */
5300	DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5301	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5302	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5303	DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5304	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5305	/** @} */
5306
5307	/** @name PDM Task
5308	* @{ */
5309	/**
5310	* Triggers the running the given task.
5311	*
5312	* @returns VBox status code.
5313	* @retval VINF_ALREADY_POSTED is the task is already pending.
5314	* @param pDevIns The device instance.
5315	* @param hTask The task to trigger.
5316	* @thread Any thread.
5317	*/
5318	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5319	/** @} */
5320
5321	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5322	* These semaphores can be signalled from ring-0.
5323	* @{ */
5324	/** @sa SUPSemEventSignal */
5325	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5326	/** @sa SUPSemEventWaitNoResume */
5327	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5328	/** @sa SUPSemEventWaitNsAbsIntr */
5329	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5330	/** @sa SUPSemEventWaitNsRelIntr */
5331	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5332	/** @sa SUPSemEventGetResolution */
5333	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5334	/** @} */
5335
5336	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5337	* These semaphores can be signalled from ring-0.
5338	* @{ */
5339	/** @sa SUPSemEventMultiSignal */
5340	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5341	/** @sa SUPSemEventMultiReset */
5342	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5343	/** @sa SUPSemEventMultiWaitNoResume */
5344	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5345	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5346	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5347	/** @sa SUPSemEventMultiWaitNsRelIntr */
5348	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5349	/** @sa SUPSemEventMultiGetResolution */
5350	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5351	/** @} */
5352
5353	/**
5354	* Gets the NOP critical section.
5355	*
5356	* @returns The ring-3 address of the NOP critical section.
5357	* @param pDevIns The device instance.
5358	*/
5359	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5360
5361	/**
5362	* Changes the device level critical section from the automatically created
5363	* default to one desired by the device constructor.
5364	*
5365	* Must first be done in ring-3.
5366	*
5367	* @returns VBox status code.
5368	* @param pDevIns The device instance.
5369	* @param pCritSect The critical section to use. NULL is not
5370	* valid, instead use the NOP critical
5371	* section.
5372	*/
5373	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5374
5375	/** @name Exported PDM Critical Section Functions
5376	* @{ */
5377	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5378	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5379	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5380	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5381	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5382	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5383	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5384	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5385	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5386	/** @} */
5387
5388	/**
5389	* Gets the trace buffer handle.
5390	*
5391	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5392	* really inteded for direct usage, thus no inline wrapper function.
5393	*
5394	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5395	* @param pDevIns The device instance.
5396	*/
5397	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5398
5399	/**
5400	* Sets up the PCI bus for the ring-0 context.
5401	*
5402	* This must be called after ring-3 has registered the PCI bus using
5403	* PDMDevHlpPCIBusRegister().
5404	*
5405	* @returns VBox status code.
5406	* @param pDevIns The device instance.
5407	* @param pPciBusReg The PCI bus registration information for ring-0,
5408	* considered volatile.
5409	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5410	*/
5411	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5412
5413	/** Space reserved for future members.
5414	* @{ */
5415	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5416	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5417	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5418	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5419	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5420	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5421	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5422	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5423	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5424	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5425	/** @} */
5426
5427	/** Just a safety precaution. */
5428	uint32_t u32TheEnd;
5429	} PDMDEVHLPR0;
5430	/** Pointer PDM Device R0 API. */
5431	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5432	/** Pointer PDM Device GC API. */
5433	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5434
5435	/** Current PDMDEVHLP version number. */
5436	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 11, 0)
5437
5438
5439	/**
5440	* PDM Device Instance.
5441	*/
5442	typedef struct PDMDEVINSR3
5443	{
5444	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5445	uint32_t u32Version;
5446	/** Device instance number. */
5447	uint32_t iInstance;
5448	/** Size of the ring-3, raw-mode and shared bits. */
5449	uint32_t cbRing3;
5450	/** Set if ring-0 context is enabled. */
5451	bool fR0Enabled;
5452	/** Set if raw-mode context is enabled. */
5453	bool fRCEnabled;
5454	/** Alignment padding. */
5455	bool afReserved[2];
5456	/** Pointer the HC PDM Device API. */
5457	PCPDMDEVHLPR3 pHlpR3;
5458	/** Pointer to the shared device instance data. */
5459	RTR3PTR pvInstanceDataR3;
5460	/** Pointer to the device instance data for ring-3. */
5461	RTR3PTR pvInstanceDataForR3;
5462	/** The critical section for the device.
5463	*
5464	* TM and IOM will enter this critical section before calling into the device
5465	* code. PDM will when doing power on, power off, reset, suspend and resume
5466	* notifications. SSM will currently not, but this will be changed later on.
5467	*
5468	* The device gets a critical section automatically assigned to it before
5469	* the constructor is called. If the constructor wishes to use a different
5470	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5471	* very early on.
5472	*/
5473	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5474	/** Pointer to device registration structure. */
5475	R3PTRTYPE(PCPDMDEVREG) pReg;
5476	/** Configuration handle. */
5477	R3PTRTYPE(PCFGMNODE) pCfg;
5478	/** The base interface of the device.
5479	*
5480	* The device constructor initializes this if it has any
5481	* device level interfaces to export. To obtain this interface
5482	* call PDMR3QueryDevice(). */
5483	PDMIBASE IBase;
5484
5485	/** Tracing indicator. */
5486	uint32_t fTracing;
5487	/** The tracing ID of this device. */
5488	uint32_t idTracing;
5489
5490	/** Ring-3 pointer to the raw-mode device instance. */
5491	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5492	/** Raw-mode address of the raw-mode device instance. */
5493	RTRGPTR pDevInsForRC;
5494	/** Ring-3 pointer to the raw-mode instance data. */
5495	RTR3PTR pvInstanceDataForRCR3;
5496
5497	/** PCI device structure size. */
5498	uint32_t cbPciDev;
5499	/** Number of PCI devices in apPciDevs. */
5500	uint32_t cPciDevs;
5501	/** Pointer to the PCI devices for this device.
5502	* (Allocated after the shared instance data.)
5503	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5504	* two devices ever needing it can use cbPciDev and do the address
5505	* calculations that for entries 8+. */
5506	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5507
5508	/** Temporarily. */
5509	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5510	/** Temporarily. */
5511	RTR0PTR pvInstanceDataR0;
5512	/** Temporarily. */
5513	RTRCPTR pvInstanceDataRC;
5514	/** Align the internal data more naturally. */
5515	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5516
5517	/** Internal data. */
5518	union
5519	{
5520	#ifdef PDMDEVINSINT_DECLARED
5521	PDMDEVINSINTR3 s;
5522	#endif
5523	uint8_t padding[HC_ARCH_BITS == 32 ? 0x30 : 0x50];
5524	} Internal;
5525
5526	/** Device instance data for ring-3. The size of this area is defined
5527	* in the PDMDEVREG::cbInstanceR3 field. */
5528	char achInstanceData[8];
5529	} PDMDEVINSR3;
5530
5531	/** Current PDMDEVINSR3 version number. */
5532	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5533
5534	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5535	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5536
5537
5538	/**
5539	* PDM ring-0 device instance.
5540	*/
5541	typedef struct PDMDEVINSR0
5542	{
5543	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5544	uint32_t u32Version;
5545	/** Device instance number. */
5546	uint32_t iInstance;
5547
5548	/** Pointer the HC PDM Device API. */
5549	PCPDMDEVHLPR0 pHlpR0;
5550	/** Pointer to the shared device instance data. */
5551	RTR0PTR pvInstanceDataR0;
5552	/** Pointer to the device instance data for ring-0. */
5553	RTR0PTR pvInstanceDataForR0;
5554	/** The critical section for the device.
5555	*
5556	* TM and IOM will enter this critical section before calling into the device
5557	* code. PDM will when doing power on, power off, reset, suspend and resume
5558	* notifications. SSM will currently not, but this will be changed later on.
5559	*
5560	* The device gets a critical section automatically assigned to it before
5561	* the constructor is called. If the constructor wishes to use a different
5562	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5563	* very early on.
5564	*/
5565	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5566	/** Pointer to the ring-0 device registration structure. */
5567	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5568	/** Ring-3 address of the ring-3 device instance. */
5569	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5570	/** Ring-0 pointer to the ring-3 device instance. */
5571	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5572	/** Ring-0 pointer to the ring-3 instance data. */
5573	RTR0PTR pvInstanceDataForR3R0;
5574	/** Raw-mode address of the raw-mode device instance. */
5575	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5576	/** Ring-0 pointer to the raw-mode device instance. */
5577	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5578	/** Ring-0 pointer to the raw-mode instance data. */
5579	RTR0PTR pvInstanceDataForRCR0;
5580
5581	/** PCI device structure size. */
5582	uint32_t cbPciDev;
5583	/** Number of PCI devices in apPciDevs. */
5584	uint32_t cPciDevs;
5585	/** Pointer to the PCI devices for this device.
5586	* (Allocated after the shared instance data.)
5587	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5588	* two devices ever needing it can use cbPciDev and do the address
5589	* calculations that for entries 8+. */
5590	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5591
5592	/** Align the internal data more naturally. */
5593	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5594
5595	/** Internal data. */
5596	union
5597	{
5598	#ifdef PDMDEVINSINT_DECLARED
5599	PDMDEVINSINTR0 s;
5600	#endif
5601	uint8_t padding[HC_ARCH_BITS == 32 ? 0x20 : 0x40];
5602	} Internal;
5603
5604	/** Device instance data for ring-0. The size of this area is defined
5605	* in the PDMDEVREG::cbInstanceR0 field. */
5606	char achInstanceData[8];
5607	} PDMDEVINSR0;
5608
5609	/** Current PDMDEVINSR0 version number. */
5610	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5611
5612
5613	/**
5614	* PDM raw-mode device instance.
5615	*/
5616	typedef struct PDMDEVINSRC
5617	{
5618	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5619	uint32_t u32Version;
5620	/** Device instance number. */
5621	uint32_t iInstance;
5622
5623	/** Pointer the HC PDM Device API. */
5624	PCPDMDEVHLPRC pHlpRC;
5625	/** Pointer to the shared device instance data. */
5626	RTRGPTR pvInstanceDataRC;
5627	/** Pointer to the device instance data for raw-mode. */
5628	RTRGPTR pvInstanceDataForRC;
5629	/** The critical section for the device.
5630	*
5631	* TM and IOM will enter this critical section before calling into the device
5632	* code. PDM will when doing power on, power off, reset, suspend and resume
5633	* notifications. SSM will currently not, but this will be changed later on.
5634	*
5635	* The device gets a critical section automatically assigned to it before
5636	* the constructor is called. If the constructor wishes to use a different
5637	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5638	* very early on.
5639	*/
5640	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5641	/** Pointer to the raw-mode device registration structure. */
5642	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5643
5644	/** PCI device structure size. */
5645	uint32_t cbPciDev;
5646	/** Number of PCI devices in apPciDevs. */
5647	uint32_t cPciDevs;
5648	/** Pointer to the PCI devices for this device.
5649	* (Allocated after the shared instance data.) */
5650	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5651
5652	/** Align the internal data more naturally. */
5653	uint32_t au32Padding[14];
5654
5655	/** Internal data. */
5656	union
5657	{
5658	#ifdef PDMDEVINSINT_DECLARED
5659	PDMDEVINSINTRC s;
5660	#endif
5661	uint8_t padding[0x10];
5662	} Internal;
5663
5664	/** Device instance data for ring-0. The size of this area is defined
5665	* in the PDMDEVREG::cbInstanceR0 field. */
5666	char achInstanceData[8];
5667	} PDMDEVINSRC;
5668
5669	/** Current PDMDEVINSR0 version number. */
5670	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5671
5672
5673	/** @def PDM_DEVINS_VERSION
5674	* Current PDMDEVINS version number. */
5675	/** @typedef PDMDEVINS
5676	* The device instance structure for the current context. */
5677	#ifdef IN_RING3
5678	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5679	typedef PDMDEVINSR3 PDMDEVINS;
5680	#elif defined(IN_RING0)
5681	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5682	typedef PDMDEVINSR0 PDMDEVINS;
5683	#elif defined(IN_RC)
5684	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5685	typedef PDMDEVINSRC PDMDEVINS;
5686	#else
5687	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5688	#endif
5689
5690	/**
5691	* Get the pointer to an PCI device.
5692	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5693	*/
5694	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5695	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5696	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5697
5698	/**
5699	* Calc the pointer to of a given PCI device.
5700	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5701	*/
5702	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5703	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5704	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5705	: (PPDMPCIDEV)NULL )
5706
5707
5708	/**
5709	* Checks the structure versions of the device instance and device helpers,
5710	* returning if they are incompatible.
5711	*
5712	* This is for use in the constructor.
5713	*
5714	* @param pDevIns The device instance pointer.
5715	*/
5716	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5717	do \
5718	{ \
5719	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5720	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5721	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5722	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5723	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5724	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5725	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5726	} while (0)
5727
5728	/**
5729	* Quietly checks the structure versions of the device instance and device
5730	* helpers, returning if they are incompatible.
5731	*
5732	* This is for use in the destructor.
5733	*
5734	* @param pDevIns The device instance pointer.
5735	*/
5736	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5737	do \
5738	{ \
5739	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5740	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5741	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5742	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5743	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5744	} while (0)
5745
5746	/**
5747	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5748	* constructor - returns on failure.
5749	*
5750	* This should be invoked after having initialized the instance data
5751	* sufficiently for the correct operation of the destructor. The destructor is
5752	* always called!
5753	*
5754	* @param pDevIns Pointer to the PDM device instance.
5755	* @param pszValidValues Patterns describing the valid value names. See
5756	* RTStrSimplePatternMultiMatch for details on the
5757	* pattern syntax.
5758	* @param pszValidNodes Patterns describing the valid node (key) names.
5759	* Pass empty string if no valid nodes.
5760	*/
5761	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5762	do \
5763	{ \
5764	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5765	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5766	if (RT_SUCCESS(rcValCfg)) \
5767	{ /* likely */ } else return rcValCfg; \
5768	} while (0)
5769
5770	/** @def PDMDEV_ASSERT_EMT
5771	* Assert that the current thread is the emulation thread.
5772	*/
5773	#ifdef VBOX_STRICT
5774	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5775	#else
5776	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5777	#endif
5778
5779	/** @def PDMDEV_ASSERT_OTHER
5780	* Assert that the current thread is NOT the emulation thread.
5781	*/
5782	#ifdef VBOX_STRICT
5783	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5784	#else
5785	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5786	#endif
5787
5788	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5789	* Assert that the current thread is owner of the VM lock.
5790	*/
5791	#ifdef VBOX_STRICT
5792	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5793	#else
5794	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5795	#endif
5796
5797	/** @def PDMDEV_SET_ERROR
5798	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5799	*/
5800	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5801	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5802
5803	/** @def PDMDEV_SET_RUNTIME_ERROR
5804	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5805	*/
5806	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5807	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5808
5809	/** @def PDMDEVINS_2_RCPTR
5810	* Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5811	*/
5812	#ifdef IN_RC
5813	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5814	#else
5815	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5816	#endif
5817
5818	/** @def PDMDEVINS_2_R3PTR
5819	* Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5820	*/
5821	#ifdef IN_RING3
5822	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5823	#else
5824	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5825	#endif
5826
5827	/** @def PDMDEVINS_2_R0PTR
5828	* Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5829	*/
5830	#ifdef IN_RING0
5831	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5832	#else
5833	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5834	#endif
5835
5836	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5837	* Converts a PDM device instance data pointer to a ring-0 one.
5838	* @deprecated
5839	*/
5840	#ifdef IN_RING0
5841	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5842	#else
5843	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5844	#endif
5845
5846
5847	/** @def PDMDEVINS_2_DATA
5848	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5849	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5850	*
5851	* @note Do no use this macro in common code working on a core structure which
5852	* device specific code has expanded.
5853	*/
5854	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5855	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5856	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5857	{ \
5858	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5859	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5860	return pLambdaRet; \
5861	}(a_pDevIns))
5862	#else
5863	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5864	#endif
5865
5866	/** @def PDMDEVINS_2_DATA_CC
5867	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5868	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5869	*
5870	* @note Do no use this macro in common code working on a core structure which
5871	* device specific code has expanded.
5872	*/
5873	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5874	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5875	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5876	{ \
5877	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5878	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5879	return pLambdaRet; \
5880	}(a_pDevIns))
5881	#else
5882	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5883	#endif
5884
5885
5886	#ifdef IN_RING3
5887
5888	/**
5889	* @copydoc PDMDEVHLPR3::pfnIOPortRegister
5890	*/
5891	DECLINLINE(int) PDMDevHlpIOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser,
5892	PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
5893	PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
5894	{
5895	return pDevIns->pHlpR3->pfnIOPortRegister(pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
5896	}
5897
5898	/**
5899	* @copydoc PDMDEVHLPR3::pfnIOPortRegisterRC
5900	*/
5901	DECLINLINE(int) PDMDevHlpIOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
5902	const char pszOut, const char pszIn, const char *pszOutStr,
5903	const char pszInStr, const char pszDesc)
5904	{
5905	return pDevIns->pHlpR3->pfnIOPortRegisterRC(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);
5906	}
5907
5908	/**
5909	* @copydoc PDMDEVHLPR3::pfnIOPortRegisterR0
5910	*/
5911	DECLINLINE(int) PDMDevHlpIOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
5912	const char pszOut, const char pszIn, const char *pszOutStr,
5913	const char pszInStr, const char pszDesc)
5914	{
5915	return pDevIns->pHlpR3->pfnIOPortRegisterR0(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);
5916	}
5917
5918	/**
5919	* @copydoc PDMDEVHLPR3::pfnIOPortDeregister
5920	*/
5921	DECLINLINE(int) PDMDevHlpIOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts)
5922	{
5923	return pDevIns->pHlpR3->pfnIOPortDeregister(pDevIns, Port, cPorts);
5924	}
5925
5926	/**
5927	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5928	*/
5929	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5930	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5931	PIOMIOPORTHANDLE phIoPorts)
5932	{
5933	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5934	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5935	if (RT_SUCCESS(rc))
5936	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5937	return rc;
5938	}
5939
5940	/**
5941	* @sa PDMDevHlpIoPortCreateEx
5942	*/
5943	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5944	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5945	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5946	{
5947	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5948	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5949	}
5950
5951	/**
5952	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5953	*/
5954	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5955	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5956	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5957	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5958	{
5959	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5960	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5961	}
5962
5963	/**
5964	* @copydoc PDMDEVHLPR3::pfnIoPortMap
5965	*/
5966	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5967	{
5968	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5969	}
5970
5971	/**
5972	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5973	*/
5974	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5975	{
5976	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
5977	}
5978
5979	/**
5980	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
5981	*/
5982	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5983	{
5984	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
5985	}
5986
5987
5988	#endif /* IN_RING3 */
5989	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
5990
5991	/**
5992	* @sa PDMDevHlpIoPortSetUpContextEx
5993	*/
5994	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5995	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
5996	{
5997	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
5998	}
5999
6000	/**
6001	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6002	*/
6003	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6004	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6005	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6006	{
6007	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6008	}
6009
6010	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6011	#ifdef IN_RING3
6012
6013	/**
6014	* @sa PDMDevHlpMmioCreateEx
6015	*/
6016	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6017	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6018	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6019	{
6020	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6021	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6022	}
6023
6024	/**
6025	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6026	*/
6027	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6028	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6029	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6030	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6031	{
6032	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6033	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6034	}
6035
6036	/**
6037	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6038	*/
6039	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6040	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6041	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6042	{
6043	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6044	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6045	if (RT_SUCCESS(rc))
6046	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6047	return rc;
6048	}
6049
6050	/**
6051	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6052	*/
6053	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6054	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6055	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6056	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6057	{
6058	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6059	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6060	if (RT_SUCCESS(rc))
6061	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6062	return rc;
6063	}
6064
6065	/**
6066	* @copydoc PDMDEVHLPR3::pfnMmioMap
6067	*/
6068	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6069	{
6070	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6071	}
6072
6073	/**
6074	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6075	*/
6076	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6077	{
6078	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6079	}
6080
6081	/**
6082	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6083	*/
6084	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6085	{
6086	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6087	}
6088
6089	/**
6090	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6091	*/
6092	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6093	{
6094	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6095	}
6096
6097	#endif /* IN_RING3 */
6098	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6099
6100	/**
6101	* @sa PDMDevHlpMmioSetUpContextEx
6102	*/
6103	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6104	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6105	{
6106	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6107	}
6108
6109	/**
6110	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6111	*/
6112	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6113	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6114	{
6115	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6116	}
6117
6118	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6119	#ifdef IN_RING3
6120
6121	/**
6122	* Register a Memory Mapped I/O (MMIO) region.
6123	*
6124	* These callbacks are of course for the ring-3 context (R3). Register HC
6125	* handlers before raw-mode context (RC) and ring-0 context (R0) handlers! There
6126	* must be a R3 handler for every RC and R0 handler!
6127	*
6128	* @returns VBox status.
6129	* @param pDevIns The device instance to register the MMIO with.
6130	* @param GCPhysStart First physical address in the range.
6131	* @param cbRange The size of the range (in bytes).
6132	* @param pvUser User argument.
6133	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
6134	* @param pfnWrite Pointer to function which is gonna handle Write operations.
6135	* @param pfnRead Pointer to function which is gonna handle Read operations.
6136	* @param pszDesc Pointer to description string. This must not be freed.
6137	*/
6138	DECLINLINE(int) PDMDevHlpMMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
6139	uint32_t fFlags, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, const char *pszDesc)
6140	{
6141	return pDevIns->pHlpR3->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, NULL /pfnFill/,
6142	fFlags, pszDesc);
6143	}
6144
6145	/**
6146	* Register a Memory Mapped I/O (MMIO) region for RC.
6147	*
6148	* These callbacks are for the raw-mode context (RC). Register ring-3 context
6149	* (R3) handlers before guest context handlers! There must be a R3 handler for
6150	* every RC handler!
6151	*
6152	* @returns VBox status.
6153	* @param pDevIns The device instance to register the MMIO with.
6154	* @param GCPhysStart First physical address in the range.
6155	* @param cbRange The size of the range (in bytes).
6156	* @param pvUser User argument.
6157	* @param pszWrite Name of the RC function which is gonna handle Write operations.
6158	* @param pszRead Name of the RC function which is gonna handle Read operations.
6159	*/
6160	DECLINLINE(int) PDMDevHlpMMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
6161	const char pszWrite, const char pszRead)
6162	{
6163	return pDevIns->pHlpR3->pfnMMIORegisterRC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, NULL /pszFill/);
6164	}
6165
6166	/**
6167	* Register a Memory Mapped I/O (MMIO) region for R0.
6168	*
6169	* These callbacks are for the ring-0 host context (R0). Register ring-3
6170	* constext (R3) handlers before R0 handlers! There must be a R3 handler for
6171	* every R0 handler!
6172	*
6173	* @returns VBox status.
6174	* @param pDevIns The device instance to register the MMIO with.
6175	* @param GCPhysStart First physical address in the range.
6176	* @param cbRange The size of the range (in bytes).
6177	* @param pvUser User argument. (if pointer, then it must be in locked memory!)
6178	* @param pszWrite Name of the RC function which is gonna handle Write operations.
6179	* @param pszRead Name of the RC function which is gonna handle Read operations.
6180	* @remarks Caller enters the device critical section prior to invoking the
6181	* registered callback methods.
6182	*/
6183	DECLINLINE(int) PDMDevHlpMMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
6184	const char pszWrite, const char pszRead)
6185	{
6186	return pDevIns->pHlpR3->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, NULL /pszFill/);
6187	}
6188
6189	/**
6190	* @copydoc PDMDEVHLPR3::pfnMMIORegister
6191	*/
6192	DECLINLINE(int) PDMDevHlpMMIORegisterEx(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
6193	uint32_t fFlags, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead,
6194	PFNIOMMMIOFILL pfnFill, const char *pszDesc)
6195	{
6196	return pDevIns->pHlpR3->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill,
6197	fFlags, pszDesc);
6198	}
6199
6200	/**
6201	* @copydoc PDMDEVHLPR3::pfnMMIORegisterRC
6202	*/
6203	DECLINLINE(int) PDMDevHlpMMIORegisterRCEx(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
6204	const char pszWrite, const char pszRead, const char *pszFill)
6205	{
6206	return pDevIns->pHlpR3->pfnMMIORegisterRC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill);
6207	}
6208
6209	/**
6210	* @copydoc PDMDEVHLPR3::pfnMMIORegisterR0
6211	*/
6212	DECLINLINE(int) PDMDevHlpMMIORegisterR0Ex(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
6213	const char pszWrite, const char pszRead, const char *pszFill)
6214	{
6215	return pDevIns->pHlpR3->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill);
6216	}
6217
6218	/**
6219	* @copydoc PDMDEVHLPR3::pfnMMIODeregister
6220	*/
6221	DECLINLINE(int) PDMDevHlpMMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange)
6222	{
6223	return pDevIns->pHlpR3->pfnMMIODeregister(pDevIns, GCPhysStart, cbRange);
6224	}
6225
6226	/**
6227	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6228	*/
6229	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6230	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6231	{
6232	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6233	}
6234
6235	/**
6236	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6237	*/
6238	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6239	{
6240	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6241	}
6242
6243	/**
6244	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6245	*/
6246	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6247	{
6248	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6249	}
6250
6251	/**
6252	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6253	*/
6254	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6255	{
6256	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6257	}
6258
6259	/**
6260	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6261	*/
6262	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6263	{
6264	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6265	}
6266
6267	#endif /* IN_RING3 */
6268	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6269
6270	/**
6271	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6272	*/
6273	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6274	size_t offSub, size_t cbSub, void **ppvMapping)
6275	{
6276	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6277	}
6278
6279	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6280	#ifdef IN_RING3
6281
6282	/**
6283	* @copydoc PDMDEVHLPR3::pfnMMIO2Register
6284	*/
6285	DECLINLINE(int) PDMDevHlpMMIO2Register(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
6286	uint32_t fFlags, void *ppv, const char pszDesc)
6287	{
6288	return pDevIns->pHlpR3->pfnMMIO2Register(pDevIns, pPciDev, iRegion, cb, fFlags, ppv, pszDesc);
6289	}
6290
6291	/**
6292	* @copydoc PDMDEVHLPR3::pfnMMIOExDeregister
6293	* @param pPciDev The PCI device the region is associated with, use
6294	* NULL to indicate it is not associated with a device.
6295	*/
6296	DECLINLINE(int) PDMDevHlpMMIOExDeregister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion)
6297	{
6298	return pDevIns->pHlpR3->pfnMMIOExDeregister(pDevIns, pPciDev, iRegion);
6299	}
6300
6301	/**
6302	* @copydoc PDMDEVHLPR3::pfnMMIOExMap
6303	* @param pPciDev The PCI device the region is associated with, use
6304	* NULL to indicate it is not associated with a device.
6305	*/
6306	DECLINLINE(int) PDMDevHlpMMIOExMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
6307	{
6308	return pDevIns->pHlpR3->pfnMMIOExMap(pDevIns, pPciDev, iRegion, GCPhys);
6309	}
6310
6311	/**
6312	* @copydoc PDMDEVHLPR3::pfnMMIOExUnmap
6313	* @param pPciDev The PCI device the region is associated with, use
6314	* NULL to indicate it is not associated with a device.
6315	*/
6316	DECLINLINE(int) PDMDevHlpMMIOExUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
6317	{
6318	return pDevIns->pHlpR3->pfnMMIOExUnmap(pDevIns, pPciDev, iRegion, GCPhys);
6319	}
6320
6321	/**
6322	* @copydoc PDMDEVHLPR3::pfnMMIOExReduce
6323	*/
6324	DECLINLINE(int) PDMDevHlpMMIOExReduce(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion)
6325	{
6326	return pDevIns->pHlpR3->pfnMMIOExReduce(pDevIns, pPciDev, iRegion, cbRegion);
6327	}
6328
6329	#ifdef VBOX_WITH_RAW_MODE_KEEP
6330	/**
6331	* @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
6332	*/
6333	DECLINLINE(int) PDMDevHlpMMHyperMapMMIO2(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
6334	const char *pszDesc, PRTRCPTR pRCPtr)
6335	{
6336	return pDevIns->pHlpR3->pfnMMHyperMapMMIO2(pDevIns, pPciDev, iRegion, off, cb, pszDesc, pRCPtr);
6337	}
6338	#endif
6339
6340	/**
6341	* @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
6342	*/
6343	DECLINLINE(int) PDMDevHlpMMIO2MapKernel(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
6344	const char *pszDesc, PRTR0PTR pR0Ptr)
6345	{
6346	return pDevIns->pHlpR3->pfnMMIO2MapKernel(pDevIns, pPciDev, iRegion, off, cb, pszDesc, pR0Ptr);
6347	}
6348
6349	/**
6350	* @copydoc PDMDEVHLPR3::pfnROMRegister
6351	*/
6352	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6353	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6354	{
6355	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6356	}
6357
6358	/**
6359	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6360	*/
6361	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6362	{
6363	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6364	}
6365
6366	/**
6367	* Register a save state data unit.
6368	*
6369	* @returns VBox status.
6370	* @param pDevIns The device instance.
6371	* @param uVersion Data layout version number.
6372	* @param cbGuess The approximate amount of data in the unit.
6373	* Only for progress indicators.
6374	* @param pfnSaveExec Execute save callback, optional.
6375	* @param pfnLoadExec Execute load callback, optional.
6376	*/
6377	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6378	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6379	{
6380	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6381	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6382	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6383	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6384	}
6385
6386	/**
6387	* Register a save state data unit with a live save callback as well.
6388	*
6389	* @returns VBox status.
6390	* @param pDevIns The device instance.
6391	* @param uVersion Data layout version number.
6392	* @param cbGuess The approximate amount of data in the unit.
6393	* Only for progress indicators.
6394	* @param pfnLiveExec Execute live callback, optional.
6395	* @param pfnSaveExec Execute save callback, optional.
6396	* @param pfnLoadExec Execute load callback, optional.
6397	*/
6398	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6399	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6400	{
6401	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6402	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6403	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6404	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6405	}
6406
6407	/**
6408	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6409	*/
6410	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6411	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6412	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6413	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6414	{
6415	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6416	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6417	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6418	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6419	}
6420
6421	/**
6422	* @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6423	*/
6424	DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6425	uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6426	{
6427	return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6428	}
6429
6430	/**
6431	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6432	*/
6433	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6434	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6435	{
6436	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6437	}
6438
6439	#endif /* IN_RING3 */
6440
6441	/**
6442	* @copydoc PDMDEVHLPR3::pfnTimerToPtr
6443	*/
6444	DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6445	{
6446	return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6447	}
6448
6449	/**
6450	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6451	*/
6452	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6453	{
6454	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6455	}
6456
6457	/**
6458	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6459	*/
6460	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6461	{
6462	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6463	}
6464
6465	/**
6466	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6467	*/
6468	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6469	{
6470	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6471	}
6472
6473	/**
6474	* @copydoc PDMDEVHLPR3::pfnTimerGet
6475	*/
6476	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6477	{
6478	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6479	}
6480
6481	/**
6482	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6483	*/
6484	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6485	{
6486	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6487	}
6488
6489	/**
6490	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6491	*/
6492	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6493	{
6494	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6495	}
6496
6497	/**
6498	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6499	*/
6500	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6501	{
6502	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6503	}
6504
6505	/**
6506	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6507	*/
6508	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6509	{
6510	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6511	}
6512
6513	/**
6514	* @copydoc PDMDEVHLPR3::pfnTimerLock
6515	*/
6516	DECLINLINE(int) PDMDevHlpTimerLock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6517	{
6518	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLock(pDevIns, hTimer, rcBusy);
6519	}
6520
6521	/**
6522	* @copydoc PDMDEVHLPR3::pfnTimerSet
6523	*/
6524	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6525	{
6526	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6527	}
6528
6529	/**
6530	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6531	*/
6532	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6533	{
6534	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6535	}
6536
6537	/**
6538	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6539	*/
6540	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6541	{
6542	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6543	}
6544
6545	/**
6546	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6547	*/
6548	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6549	{
6550	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6551	}
6552
6553	/**
6554	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6555	*/
6556	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6557	{
6558	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6559	}
6560
6561	/**
6562	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6563	*/
6564	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6565	{
6566	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6567	}
6568
6569	/**
6570	* @copydoc PDMDEVHLPR3::pfnTimerStop
6571	*/
6572	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6573	{
6574	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6575	}
6576
6577	/**
6578	* @copydoc PDMDEVHLPR3::pfnTimerUnlock
6579	*/
6580	DECLINLINE(void) PDMDevHlpTimerUnlock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6581	{
6582	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlock(pDevIns, hTimer);
6583	}
6584
6585	#ifdef IN_RING3
6586
6587	/**
6588	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6589	*/
6590	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6591	{
6592	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6593	}
6594
6595	/**
6596	* @copydoc PDMDEVHLPR3::pfnTimerSave
6597	*/
6598	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6599	{
6600	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6601	}
6602
6603	/**
6604	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6605	*/
6606	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6607	{
6608	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6609	}
6610
6611	/**
6612	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6613	*/
6614	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6615	{
6616	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6617	}
6618
6619	/**
6620	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6621	*/
6622	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6623	{
6624	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6625	}
6626
6627	#endif
6628
6629	/**
6630	* @copydoc PDMDEVHLPR3::pfnPhysRead
6631	*/
6632	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6633	{
6634	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
6635	}
6636
6637	/**
6638	* @copydoc PDMDEVHLPR3::pfnPhysWrite
6639	*/
6640	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6641	{
6642	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
6643	}
6644
6645	#ifdef IN_RING3
6646
6647	/**
6648	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6649	*/
6650	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6651	{
6652	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6653	}
6654
6655	/**
6656	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6657	*/
6658	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6659	PPGMPAGEMAPLOCK pLock)
6660	{
6661	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6662	}
6663
6664	/**
6665	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6666	*/
6667	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6668	{
6669	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6670	}
6671
6672	/**
6673	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6674	*/
6675	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6676	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6677	{
6678	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6679	}
6680
6681	/**
6682	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6683	*/
6684	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6685	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6686	{
6687	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6688	}
6689
6690	/**
6691	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6692	*/
6693	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6694	{
6695	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6696	}
6697
6698	/**
6699	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6700	*/
6701	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6702	{
6703	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6704	}
6705
6706	/**
6707	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6708	*/
6709	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6710	{
6711	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6712	}
6713
6714	/**
6715	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6716	*/
6717	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6718	{
6719	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6720	}
6721
6722	/**
6723	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6724	*/
6725	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6726	{
6727	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6728	}
6729
6730	/**
6731	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6732	*/
6733	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6734	{
6735	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6736	}
6737
6738	/**
6739	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6740	*/
6741	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6742	{
6743	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6744	}
6745	#endif /* IN_RING3 */
6746
6747	/**
6748	* @copydoc PDMDEVHLPR3::pfnVMState
6749	*/
6750	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6751	{
6752	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6753	}
6754
6755	#ifdef IN_RING3
6756	/**
6757	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6758	*/
6759	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6760	{
6761	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6762	}
6763	#endif /* IN_RING3 */
6764
6765	/**
6766	* @copydoc PDMDEVHLPR3::pfnVMSetError
6767	*/
6768	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6769	const char *pszFormat, ...)
6770	{
6771	va_list va;
6772	va_start(va, pszFormat);
6773	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6774	va_end(va);
6775	return rc;
6776	}
6777
6778	/**
6779	* @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6780	*/
6781	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6782	const char *pszFormat, ...)
6783	{
6784	va_list va;
6785	int rc;
6786	va_start(va, pszFormat);
6787	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6788	va_end(va);
6789	return rc;
6790	}
6791
6792	/**
6793	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6794	*
6795	* @returns VBox status code which must be passed up to the VMM. This will be
6796	* VINF_SUCCESS in non-strict builds.
6797	* @param pDevIns The device instance.
6798	* @param SRC_POS Use RT_SRC_POS.
6799	* @param pszFormat Message. (optional)
6800	* @param ... Message parameters.
6801	*/
6802	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6803	{
6804	#ifdef VBOX_STRICT
6805	# ifdef IN_RING3
6806	int rc;
6807	va_list args;
6808	va_start(args, pszFormat);
6809	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6810	va_end(args);
6811	return rc;
6812	# else
6813	NOREF(pDevIns);
6814	NOREF(pszFile);
6815	NOREF(iLine);
6816	NOREF(pszFunction);
6817	NOREF(pszFormat);
6818	return VINF_EM_DBG_STOP;
6819	# endif
6820	#else
6821	NOREF(pDevIns);
6822	NOREF(pszFile);
6823	NOREF(iLine);
6824	NOREF(pszFunction);
6825	NOREF(pszFormat);
6826	return VINF_SUCCESS;
6827	#endif
6828	}
6829
6830	#ifdef IN_RING3
6831
6832	/**
6833	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6834	*/
6835	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6836	{
6837	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6838	}
6839
6840	/**
6841	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6842	*/
6843	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6844	{
6845	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6846	}
6847
6848	/**
6849	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6850	*/
6851	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6852	{
6853	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6854	}
6855
6856	/**
6857	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6858	*/
6859	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6860	{
6861	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6862	}
6863
6864	/**
6865	* @copydoc PDMDEVHLPR3::pfnSTAMRegisterF
6866	*/
6867	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6868	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6869	const char pszDesc, const char pszName, ...)
6870	{
6871	va_list va;
6872	va_start(va, pszName);
6873	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6874	va_end(va);
6875	}
6876
6877	/**
6878	* Registers the device with the default PCI bus.
6879	*
6880	* @returns VBox status code.
6881	* @param pDevIns The device instance.
6882	* @param pPciDev The PCI device structure.
6883	* This must be kept in the instance data.
6884	* The PCI configuration must be initialized before registration.
6885	*/
6886	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6887	{
6888	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6889	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6890	}
6891
6892	/**
6893	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6894	*/
6895	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6896	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6897	{
6898	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6899	}
6900
6901	/**
6902	* Initialize MSI emulation support for the first PCI device.
6903	*
6904	* @returns VBox status code.
6905	* @param pDevIns The device instance.
6906	* @param pMsiReg MSI emulation registration structure.
6907	*/
6908	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6909	{
6910	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6911	}
6912
6913	/**
6914	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6915	*/
6916	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6917	{
6918	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6919	}
6920
6921	/**
6922	* Registers a I/O region (memory mapped or I/O ports) for the default PCI
6923	* device.
6924	*
6925	* @returns VBox status code.
6926	* @param pDevIns The device instance.
6927	* @param iRegion The region number.
6928	* @param cbRegion Size of the region.
6929	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
6930	* @param pfnMapUnmap Callback for doing the mapping.
6931	* @remarks The callback will be invoked holding the PDM lock. The device lock
6932	* is NOT take because that is very likely be a lock order violation.
6933	* @remarks Old callback style, won't get unmap calls.
6934	*/
6935	DECLINLINE(int) PDMDevHlpPCIIORegionRegister(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6936	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnMapUnmap)
6937	{
6938	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6939	PDMPCIDEV_IORGN_F_NO_HANDLE, UINT64_MAX, pfnMapUnmap);
6940	}
6941
6942	/**
6943	* @sa PDMDEVHLPR3::pfnPCIIORegionRegister
6944	* @remarks Old callback style, won't get unmap calls.
6945	*/
6946	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion,
6947	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnMapUnmap)
6948	{
6949	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6950	PDMPCIDEV_IORGN_F_NO_HANDLE, UINT64_MAX, pfnMapUnmap);
6951	}
6952
6953	/**
6954	* Registers a I/O port region for the default PCI device.
6955	*
6956	* @returns VBox status code.
6957	* @param pDevIns The device instance.
6958	* @param iRegion The region number.
6959	* @param cbRegion Size of the region.
6960	* @param hIoPorts Handle to the I/O port region.
6961	*/
6962	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6963	{
6964	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6965	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6966	}
6967
6968	/**
6969	* Registers a I/O port region for the default PCI device, custom map/unmap.
6970	*
6971	* @returns VBox status code.
6972	* @param pDevIns The device instance.
6973	* @param iRegion The region number.
6974	* @param cbRegion Size of the region.
6975	* @param hIoPorts Handle to the I/O port region.
6976	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6977	* callback will be invoked holding only the PDM lock.
6978	* The device lock will _not_ be taken (due to lock
6979	* order).
6980	*/
6981	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6982	PFNPCIIOREGIONMAP pfnMapUnmap)
6983	{
6984	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6985	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6986	UINT64_MAX, pfnMapUnmap);
6987	}
6988
6989	/**
6990	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6991	* and registering an I/O port region for the default PCI device.
6992	*
6993	* @returns VBox status code.
6994	* @param pDevIns The device instance to register the ports with.
6995	* @param cbPorts The size of the region in I/O ports.
6996	* @param iPciRegion The PCI device region.
6997	* @param pfnOut Pointer to function which is gonna handle OUT
6998	* operations. Optional.
6999	* @param pfnIn Pointer to function which is gonna handle IN operations.
7000	* Optional.
7001	* @param pvUser User argument to pass to the callbacks.
7002	* @param pszDesc Pointer to description string. This must not be freed.
7003	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7004	* coverage is allowed. This must not be freed.
7005	* @param phIoPorts Where to return the I/O port range handle.
7006	*
7007	*/
7008	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cbPorts,
7009	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7010	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7011
7012	{
7013	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cbPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7014	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7015	if (RT_SUCCESS(rc))
7016	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbPorts, PCI_ADDRESS_SPACE_IO,
7017	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7018	phIoPorts, NULL /pfnMapUnmap*/);
7019	return rc;
7020	}
7021
7022	/**
7023	* Registers an MMIO region for the default PCI device.
7024	*
7025	* @returns VBox status code.
7026	* @param pDevIns The device instance.
7027	* @param iRegion The region number.
7028	* @param cbRegion Size of the region.
7029	* @param enmType PCI_ADDRESS_SPACE_MEM or
7030	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7031	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7032	* @param hMmioRegion Handle to the MMIO region.
7033	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7034	* callback will be invoked holding only the PDM lock.
7035	* The device lock will _not_ be taken (due to lock
7036	* order).
7037	*/
7038	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7039	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7040	{
7041	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7042	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7043	hMmioRegion, pfnMapUnmap);
7044	}
7045
7046	/**
7047	* Registers an MMIO region for the default PCI device, extended version.
7048	*
7049	* @returns VBox status code.
7050	* @param pDevIns The device instance.
7051	* @param pPciDev The PCI device structure.
7052	* @param iRegion The region number.
7053	* @param cbRegion Size of the region.
7054	* @param enmType PCI_ADDRESS_SPACE_MEM or
7055	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7056	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7057	* @param hMmioRegion Handle to the MMIO region.
7058	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7059	* callback will be invoked holding only the PDM lock.
7060	* The device lock will _not_ be taken (due to lock
7061	* order).
7062	*/
7063	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7064	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7065	PFNPCIIOREGIONMAP pfnMapUnmap)
7066	{
7067	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7068	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7069	hMmioRegion, pfnMapUnmap);
7070	}
7071
7072	/**
7073	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7074	* and registering an MMIO region for the default PCI device.
7075	*
7076	* @returns VBox status code.
7077	* @param pDevIns The device instance to register the ports with.
7078	* @param cbRegion The size of the region in bytes.
7079	* @param iPciRegion The PCI device region.
7080	* @param enmType PCI_ADDRESS_SPACE_MEM or
7081	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7082	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7083	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7084	* @param pfnWrite Pointer to function which is gonna handle Write
7085	* operations.
7086	* @param pfnRead Pointer to function which is gonna handle Read
7087	* operations.
7088	* @param pvUser User argument to pass to the callbacks.
7089	* @param pszDesc Pointer to description string. This must not be freed.
7090	* @param phRegion Where to return the MMIO region handle.
7091	*
7092	*/
7093	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7094	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7095	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7096
7097	{
7098	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7099	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7100	if (RT_SUCCESS(rc))
7101	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7102	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7103	phRegion, NULL /pfnMapUnmap*/);
7104	return rc;
7105	}
7106
7107
7108	/**
7109	* Registers an MMIO2 region for the default PCI device.
7110	*
7111	* @returns VBox status code.
7112	* @param pDevIns The device instance.
7113	* @param iRegion The region number.
7114	* @param cbRegion Size of the region.
7115	* @param enmType PCI_ADDRESS_SPACE_MEM or
7116	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7117	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7118	* @param hMmio2Region Handle to the MMIO2 region.
7119	*/
7120	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7121	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7122	{
7123	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7124	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7125	hMmio2Region, NULL);
7126	}
7127
7128	/**
7129	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7130	* and registering an MMIO2 region for the default PCI device, extended edition.
7131	*
7132	* @returns VBox status code.
7133	* @param pDevIns The device instance to register the ports with.
7134	* @param cbRegion The size of the region in bytes.
7135	* @param iPciRegion The PCI device region.
7136	* @param enmType PCI_ADDRESS_SPACE_MEM or
7137	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7138	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7139	* @param pszDesc Pointer to description string. This must not be freed.
7140	* @param ppvMapping Where to store the address of the ring-3 mapping of
7141	* the memory.
7142	* @param phRegion Where to return the MMIO2 region handle.
7143	*
7144	*/
7145	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7146	PCIADDRESSSPACE enmType, const char *pszDesc,
7147	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7148
7149	{
7150	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7151	pszDesc, ppvMapping, phRegion);
7152	if (RT_SUCCESS(rc))
7153	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7154	PDMPCIDEV_IORGN_F_MMIO2_HANDLE, phRegion, NULL /pfnCallback*/);
7155	return rc;
7156	}
7157
7158	/**
7159	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7160	* and registering an MMIO2 region for the default PCI device.
7161	*
7162	* @returns VBox status code.
7163	* @param pDevIns The device instance to register the ports with.
7164	* @param cbRegion The size of the region in bytes.
7165	* @param iPciRegion The PCI device region.
7166	* @param enmType PCI_ADDRESS_SPACE_MEM or
7167	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7168	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7169	* @param fMmio2Flags To be defined, must be zero.
7170	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7171	* callback will be invoked holding only the PDM lock.
7172	* The device lock will _not_ be taken (due to lock
7173	* order).
7174	* @param pszDesc Pointer to description string. This must not be freed.
7175	* @param ppvMapping Where to store the address of the ring-3 mapping of
7176	* the memory.
7177	* @param phRegion Where to return the MMIO2 region handle.
7178	*
7179	*/
7180	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7181	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7182	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7183
7184	{
7185	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7186	pszDesc, ppvMapping, phRegion);
7187	if (RT_SUCCESS(rc))
7188	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7189	PDMPCIDEV_IORGN_F_MMIO2_HANDLE, *phRegion, pfnMapUnmap);
7190	return rc;
7191	}
7192
7193	/**
7194	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7195	*/
7196	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7197	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7198	{
7199	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7200	}
7201
7202	/**
7203	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7204	*/
7205	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7206	unsigned cb, uint32_t *pu32Value)
7207	{
7208	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7209	}
7210
7211	/**
7212	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7213	*/
7214	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7215	unsigned cb, uint32_t u32Value)
7216	{
7217	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7218	}
7219
7220	#endif /* IN_RING3 */
7221
7222	/**
7223	* Bus master physical memory read from the default PCI device.
7224	*
7225	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7226	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7227	* @param pDevIns The device instance.
7228	* @param GCPhys Physical address start reading from.
7229	* @param pvBuf Where to put the read bits.
7230	* @param cbRead How many bytes to read.
7231	* @thread Any thread, but the call may involve the emulation thread.
7232	*/
7233	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7234	{
7235	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead);
7236	}
7237
7238	/**
7239	* @copydoc PDMDEVHLPR3::pfnPCIPhysRead
7240	*/
7241	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7242	{
7243	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead);
7244	}
7245
7246	/**
7247	* Bus master physical memory write from the default PCI device.
7248	*
7249	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7250	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7251	* @param pDevIns The device instance.
7252	* @param GCPhys Physical address to write to.
7253	* @param pvBuf What to write.
7254	* @param cbWrite How many bytes to write.
7255	* @thread Any thread, but the call may involve the emulation thread.
7256	*/
7257	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7258	{
7259	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite);
7260	}
7261
7262	/**
7263	* @copydoc PDMDEVHLPR3::pfnPCIPhysWrite
7264	*/
7265	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7266	{
7267	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite);
7268	}
7269
7270	/**
7271	* Sets the IRQ for the default PCI device.
7272	*
7273	* @param pDevIns The device instance.
7274	* @param iIrq IRQ number to set.
7275	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7276	* @thread Any thread, but will involve the emulation thread.
7277	*/
7278	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7279	{
7280	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7281	}
7282
7283	/**
7284	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7285	*/
7286	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7287	{
7288	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7289	}
7290
7291	/**
7292	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7293	* the request when not called from EMT.
7294	*
7295	* @param pDevIns The device instance.
7296	* @param iIrq IRQ number to set.
7297	* @param iLevel IRQ level.
7298	* @thread Any thread, but will involve the emulation thread.
7299	*/
7300	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7301	{
7302	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7303	}
7304
7305	/**
7306	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7307	*/
7308	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7309	{
7310	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7311	}
7312
7313	/**
7314	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7315	*/
7316	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7317	{
7318	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7319	}
7320
7321	/**
7322	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7323	*/
7324	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7325	{
7326	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7327	}
7328
7329	/**
7330	* @copydoc PDMDEVHLPR3::pfnIoApicSendMsi
7331	*/
7332	DECLINLINE(void) PDMDevHlpIoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
7333	{
7334	pDevIns->CTX_SUFF(pHlp)->pfnIoApicSendMsi(pDevIns, GCPhys, uValue);
7335	}
7336
7337	#ifdef IN_RING3
7338
7339	/**
7340	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7341	*/
7342	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7343	{
7344	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7345	}
7346
7347	/**
7348	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7349	*/
7350	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7351	{
7352	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7353	}
7354
7355	/**
7356	* @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7357	*/
7358	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7359	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
7360	{
7361	return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7362	}
7363
7364	/**
7365	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7366	*/
7367	DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7368	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7369	{
7370	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7371	}
7372
7373	#endif /* IN_RING3 */
7374
7375	/**
7376	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7377	*/
7378	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7379	{
7380	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7381	}
7382
7383	/**
7384	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7385	*/
7386	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7387	{
7388	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7389	}
7390
7391	/**
7392	* @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7393	*/
7394	DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7395	{
7396	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7397	}
7398
7399	/**
7400	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7401	*/
7402	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7403	{
7404	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7405	}
7406
7407	#ifdef IN_RING3
7408	/**
7409	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7410	*/
7411	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7412	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7413	{
7414	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7415	}
7416	#endif
7417
7418	/**
7419	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7420	*/
7421	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7422	{
7423	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7424	}
7425
7426	#ifdef IN_RING3
7427
7428	/**
7429	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7430	*/
7431	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7432	{
7433	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7434	}
7435
7436	/**
7437	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7438	*/
7439	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7440	{
7441	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7442	}
7443
7444	#endif /* IN_RING3 */
7445
7446	/**
7447	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7448	*/
7449	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7450	{
7451	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7452	}
7453
7454	/**
7455	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7456	*/
7457	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7458	{
7459	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7460	}
7461
7462	/**
7463	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7464	*/
7465	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7466	{
7467	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7468	}
7469
7470	/**
7471	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7472	*/
7473	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7474	{
7475	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7476	}
7477
7478	/**
7479	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7480	*/
7481	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7482	{
7483	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7484	}
7485
7486	#ifdef IN_RING3
7487
7488	/**
7489	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7490	*/
7491	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7492	{
7493	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7494	}
7495
7496	/**
7497	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7498	*/
7499	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7500	{
7501	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7502	}
7503
7504	#endif /* IN_RING3 */
7505
7506	/**
7507	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7508	*/
7509	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7510	{
7511	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7512	}
7513
7514	/**
7515	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7516	*/
7517	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7518	{
7519	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7520	}
7521
7522	/**
7523	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7524	*/
7525	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7526	{
7527	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7528	}
7529
7530	/**
7531	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7532	*/
7533	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7534	{
7535	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7536	}
7537
7538	/**
7539	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7540	*/
7541	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7542	{
7543	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7544	}
7545
7546	/**
7547	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7548	*/
7549	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7550	{
7551	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7552	}
7553
7554	#ifdef IN_RING3
7555
7556	/**
7557	* Initializes a PDM critical section.
7558	*
7559	* The PDM critical sections are derived from the IPRT critical sections, but
7560	* works in RC and R0 as well.
7561	*
7562	* @returns VBox status code.
7563	* @param pDevIns The device instance.
7564	* @param pCritSect Pointer to the critical section.
7565	* @param SRC_POS Use RT_SRC_POS.
7566	* @param pszNameFmt Format string for naming the critical section.
7567	* For statistics and lock validation.
7568	* @param ... Arguments for the format string.
7569	*/
7570	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7571	const char *pszNameFmt, ...)
7572	{
7573	int rc;
7574	va_list va;
7575	va_start(va, pszNameFmt);
7576	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7577	va_end(va);
7578	return rc;
7579	}
7580
7581	#endif /* IN_RING3 */
7582
7583	/**
7584	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7585	*/
7586	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7587	{
7588	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7589	}
7590
7591	#ifdef IN_RING3
7592
7593	/**
7594	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7595	*/
7596	DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7597	{
7598	return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7599	}
7600
7601	/**
7602	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7603	*/
7604	DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7605	{
7606	return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7607	}
7608
7609	#endif /* IN_RING3 */
7610
7611	/**
7612	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7613	*/
7614	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7615	{
7616	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7617	}
7618
7619	/**
7620	* @copydoc PDMCritSectEnter
7621	* @param pDevIns The device instance.
7622	*/
7623	DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7624	{
7625	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7626	}
7627
7628	/**
7629	* @copydoc PDMCritSectEnterDebug
7630	* @param pDevIns The device instance.
7631	*/
7632	DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7633	{
7634	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7635	}
7636
7637	/**
7638	* @copydoc PDMCritSectTryEnter
7639	* @param pDevIns The device instance.
7640	*/
7641	DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7642	{
7643	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7644	}
7645
7646	/**
7647	* @copydoc PDMCritSectTryEnterDebug
7648	* @param pDevIns The device instance.
7649	*/
7650	DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7651	{
7652	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7653	}
7654
7655	/**
7656	* @copydoc PDMCritSectLeave
7657	* @param pDevIns The device instance.
7658	*/
7659	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7660	{
7661	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7662	}
7663
7664	/**
7665	* @copydoc PDMCritSectIsOwner
7666	* @param pDevIns The device instance.
7667	*/
7668	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7669	{
7670	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7671	}
7672
7673	/**
7674	* @copydoc PDMCritSectIsInitialized
7675	* @param pDevIns The device instance.
7676	*/
7677	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7678	{
7679	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7680	}
7681
7682	/**
7683	* @copydoc PDMCritSectHasWaiters
7684	* @param pDevIns The device instance.
7685	*/
7686	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7687	{
7688	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7689	}
7690
7691	/**
7692	* @copydoc PDMCritSectGetRecursion
7693	* @param pDevIns The device instance.
7694	*/
7695	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7696	{
7697	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7698	}
7699
7700	/* Strict build: Remap the two enter calls to the debug versions. */
7701	#ifdef VBOX_STRICT
7702	# ifdef IPRT_INCLUDED_asm_h
7703	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7704	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7705	# else
7706	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7707	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7708	# endif
7709	#endif
7710
7711	#ifdef IN_RING3
7712
7713	/**
7714	* @copydoc PDMR3CritSectDelete
7715	* @param pDevIns The device instance.
7716	*/
7717	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7718	{
7719	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7720	}
7721
7722	/**
7723	* @copydoc PDMDEVHLPR3::pfnThreadCreate
7724	*/
7725	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7726	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7727	{
7728	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7729	}
7730
7731	/**
7732	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7733	*/
7734	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7735	{
7736	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7737	}
7738
7739	/**
7740	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7741	*/
7742	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7743	{
7744	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7745	}
7746
7747	/**
7748	* @copydoc PDMDEVHLPR3::pfnA20Set
7749	*/
7750	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7751	{
7752	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7753	}
7754
7755	/**
7756	* @copydoc PDMDEVHLPR3::pfnRTCRegister
7757	*/
7758	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7759	{
7760	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7761	}
7762
7763	/**
7764	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7765	*/
7766	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
7767	{
7768	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7769	}
7770
7771	/**
7772	* @copydoc PDMDEVHLPR3::pfnPICRegister
7773	*/
7774	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
7775	{
7776	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlpR3);
7777	}
7778
7779	/**
7780	* @copydoc PDMDEVHLPR3::pfnAPICRegister
7781	*/
7782	DECLINLINE(int) PDMDevHlpAPICRegister(PPDMDEVINS pDevIns)
7783	{
7784	return pDevIns->pHlpR3->pfnAPICRegister(pDevIns);
7785	}
7786
7787	/**
7788	* @copydoc PDMDEVHLPR3::pfnIOAPICRegister
7789	*/
7790	DECLINLINE(int) PDMDevHlpIOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
7791	{
7792	return pDevIns->pHlpR3->pfnIOAPICRegister(pDevIns, pIoApicReg, ppIoApicHlpR3);
7793	}
7794
7795	/**
7796	* @copydoc PDMDEVHLPR3::pfnHPETRegister
7797	*/
7798	DECLINLINE(int) PDMDevHlpHPETRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
7799	{
7800	return pDevIns->pHlpR3->pfnHPETRegister(pDevIns, pHpetReg, ppHpetHlpR3);
7801	}
7802
7803	/**
7804	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
7805	*/
7806	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
7807	{
7808	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
7809	}
7810
7811	/**
7812	* @copydoc PDMDEVHLPR3::pfnDMACRegister
7813	*/
7814	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
7815	{
7816	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
7817	}
7818
7819	/**
7820	* @copydoc PDMDEVHLPR3::pfnDMARegister
7821	*/
7822	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
7823	{
7824	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
7825	}
7826
7827	/**
7828	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
7829	*/
7830	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
7831	{
7832	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
7833	}
7834
7835	/**
7836	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
7837	*/
7838	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
7839	{
7840	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
7841	}
7842
7843	/**
7844	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
7845	*/
7846	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
7847	{
7848	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
7849	}
7850
7851	/**
7852	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
7853	*/
7854	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
7855	{
7856	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
7857	}
7858
7859	/**
7860	* @copydoc PDMDEVHLPR3::pfnDMASchedule
7861	*/
7862	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
7863	{
7864	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
7865	}
7866
7867	/**
7868	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
7869	*/
7870	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
7871	{
7872	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
7873	}
7874
7875	/**
7876	* @copydoc PDMDEVHLPR3::pfnCMOSRead
7877	*/
7878	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
7879	{
7880	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
7881	}
7882
7883	/**
7884	* @copydoc PDMDEVHLPR3::pfnCallR0
7885	*/
7886	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
7887	{
7888	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
7889	}
7890
7891	/**
7892	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
7893	*/
7894	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
7895	{
7896	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
7897	}
7898
7899	/**
7900	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
7901	*/
7902	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
7903	{
7904	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
7905	}
7906
7907	/**
7908	* @copydoc PDMDEVHLPR3::pfnGetUVM
7909	*/
7910	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
7911	{
7912	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
7913	}
7914
7915	#else /* !IN_RING3 */
7916
7917	/**
7918	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUp
7919	*/
7920	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
7921	{
7922	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
7923	}
7924
7925	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
7926
7927	/**
7928	* @copydoc PDMDEVHLPR3::pfnGetVM
7929	*/
7930	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
7931	{
7932	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
7933	}
7934
7935	/**
7936	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
7937	*/
7938	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
7939	{
7940	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
7941	}
7942
7943	/**
7944	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
7945	*/
7946	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
7947	{
7948	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
7949	}
7950
7951	/**
7952	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
7953	*/
7954	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
7955	{
7956	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
7957	}
7958
7959	/**
7960	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
7961	*/
7962	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
7963	{
7964	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
7965	}
7966
7967	/**
7968	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
7969	*/
7970	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
7971	{
7972	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
7973	}
7974
7975	#ifdef IN_RING3
7976
7977	/**
7978	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
7979	*/
7980	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
7981	{
7982	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
7983	}
7984
7985	/**
7986	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
7987	*/
7988	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
7989	{
7990	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
7991	}
7992
7993	/**
7994	* @copydoc PDMDEVHLPR3::pfnVMReset
7995	*/
7996	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
7997	{
7998	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
7999	}
8000
8001	/**
8002	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8003	*/
8004	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8005	{
8006	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8007	}
8008
8009	/**
8010	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8011	*/
8012	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8013	{
8014	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8015	}
8016
8017	/**
8018	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8019	*/
8020	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8021	{
8022	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8023	}
8024
8025	#endif /* IN_RING3 */
8026
8027	/**
8028	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8029	*/
8030	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8031	{
8032	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8033	}
8034
8035	#ifdef IN_RING3
8036
8037	/**
8038	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8039	*/
8040	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8041	{
8042	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8043	}
8044
8045	/**
8046	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8047	*/
8048	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8049	{
8050	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8051	}
8052
8053	/**
8054	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8055	*/
8056	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8057	{
8058	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8059	}
8060
8061	#endif /* IN_RING3 */
8062
8063	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8064	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8065
8066	/**
8067	* Callbacks for VBoxDeviceRegister().
8068	*/
8069	typedef struct PDMDEVREGCB
8070	{
8071	/** Interface version.
8072	* This is set to PDM_DEVREG_CB_VERSION. */
8073	uint32_t u32Version;
8074
8075	/**
8076	* Registers a device with the current VM instance.
8077	*
8078	* @returns VBox status code.
8079	* @param pCallbacks Pointer to the callback table.
8080	* @param pReg Pointer to the device registration record.
8081	* This data must be permanent and readonly.
8082	*/
8083	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8084	} PDMDEVREGCB;
8085
8086	/** Current version of the PDMDEVREGCB structure. */
8087	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8088
8089
8090	/**
8091	* The VBoxDevicesRegister callback function.
8092	*
8093	* PDM will invoke this function after loading a device module and letting
8094	* the module decide which devices to register and how to handle conflicts.
8095	*
8096	* @returns VBox status code.
8097	* @param pCallbacks Pointer to the callback table.
8098	* @param u32Version VBox version number.
8099	*/
8100	typedef DECLCALLBACK(int) FNPDMVBOXDEVICESREGISTER(PPDMDEVREGCB pCallbacks, uint32_t u32Version);
8101
8102	/** @} */
8103
8104	RT_C_DECLS_END
8105
8106	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 81667

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