hm_vmx.h@ 87385

最後變更在這個檔案從87385是 87385,由 vboxsync 提交於 4 年前
VMM/HMVMXR0: Put VMX_RESTORE_HOST_REQUIRED at the top to simplify check for calling VMXRestoreHostState.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 217.8 KB

行
1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.alldomusa.eu.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
27	#define VBOX_INCLUDED_vmm_hm_vmx_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <iprt/x86.h>
34	#include <iprt/assertcompile.h>
35
36
37	/** @defgroup grp_hm_vmx VMX Types and Definitions
38	* @ingroup grp_hm
39	* @{
40	*/
41
42	/** @name Host-state restoration flags.
43	* @note If you change these values don't forget to update the assembly
44	* defines as well!
45	* @{
46	*/
47	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
48	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
49	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
50	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
51	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
52	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
53	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
54	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
55	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
56	/**
57	* This _must_ be the top most bit, so that we can easily that that it and
58	* something else is set w/o having to do two checks like this:
59	* @code
60	* if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
61	* && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
62	* @endcode
63	* Instead we can then do:
64	* @code
65	* if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
66	* @endcode
67	*/
68	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(9)
69	/** @} */
70
71	/**
72	* Host-state restoration structure.
73	* This holds host-state fields that require manual restoration.
74	* Assembly version found in hm_vmx.mac (should be automatically verified).
75	*/
76	typedef struct VMXRESTOREHOST
77	{
78	RTSEL uHostSelDS; /* 0x00 */
79	RTSEL uHostSelES; /* 0x02 */
80	RTSEL uHostSelFS; /* 0x04 */
81	RTSEL uHostSelGS; /* 0x06 */
82	RTSEL uHostSelTR; /* 0x08 */
83	uint8_t abPadding0[4];
84	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
85	uint8_t abPadding1[6];
86	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
87	uint8_t abPadding2[6];
88	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
89	uint64_t uHostFSBase; /* 0x38 */
90	uint64_t uHostGSBase; /* 0x40 */
91	} VMXRESTOREHOST;
92	/** Pointer to VMXRESTOREHOST. */
93	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
94	AssertCompileSize(X86XDTR64, 10);
95	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
96	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
97	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
98	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
99	AssertCompileSize(VMXRESTOREHOST, 72);
100	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
101
102	/** @name Host-state MSR lazy-restoration flags.
103	* @{
104	*/
105	/** The host MSRs have been saved. */
106	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
107	/** The guest MSRs are loaded and in effect. */
108	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
109	/** @} */
110
111	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
112	* UFC = Unsupported Feature Combination.
113	* @{
114	*/
115	/** Unsupported pin-based VM-execution controls combo. */
116	#define VMX_UFC_CTRL_PIN_EXEC 1
117	/** Unsupported processor-based VM-execution controls combo. */
118	#define VMX_UFC_CTRL_PROC_EXEC 2
119	/** Unsupported move debug register VM-exit combo. */
120	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
121	/** Unsupported VM-entry controls combo. */
122	#define VMX_UFC_CTRL_ENTRY 4
123	/** Unsupported VM-exit controls combo. */
124	#define VMX_UFC_CTRL_EXIT 5
125	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
126	* for storing host MSRs. */
127	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
128	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
129	* for storing guest MSRs. */
130	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
131	/** Invalid VMCS size. */
132	#define VMX_UFC_INVALID_VMCS_SIZE 8
133	/** Unsupported secondary processor-based VM-execution controls combo. */
134	#define VMX_UFC_CTRL_PROC_EXEC2 9
135	/** Invalid unrestricted-guest execution controls combo. */
136	#define VMX_UFC_INVALID_UX_COMBO 10
137	/** EPT flush type not supported. */
138	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
139	/** EPT paging structure memory type is not write-back. */
140	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
141	/** EPT requires INVEPT instr. support but it's not available. */
142	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
143	/** EPT requires page-walk length of 4. */
144	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
145	/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
146	#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
147	/** LBR stack size cannot be determined for the current CPU. */
148	#define VMX_UFC_LBR_STACK_SIZE_UNKNOWN 16
149	/** LBR stack size of the CPU exceeds our buffer size. */
150	#define VMX_UFC_LBR_STACK_SIZE_OVERFLOW 17
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
154	* VCI = VMCS-field Cache Invalid.
155	* @{
156	*/
157	/** Cache of VM-entry controls invalid. */
158	#define VMX_VCI_CTRL_ENTRY 300
159	/** Cache of VM-exit controls invalid. */
160	#define VMX_VCI_CTRL_EXIT 301
161	/** Cache of pin-based VM-execution controls invalid. */
162	#define VMX_VCI_CTRL_PIN_EXEC 302
163	/** Cache of processor-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PROC_EXEC 303
165	/** Cache of secondary processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC2 304
167	/** Cache of exception bitmap invalid. */
168	#define VMX_VCI_CTRL_XCPT_BITMAP 305
169	/** Cache of TSC offset invalid. */
170	#define VMX_VCI_CTRL_TSC_OFFSET 306
171	/** @} */
172
173	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
174	* IGS = Invalid Guest State.
175	* @{
176	*/
177	/** An error occurred while checking invalid-guest-state. */
178	#define VMX_IGS_ERROR 500
179	/** The invalid guest-state checks did not find any reason why. */
180	#define VMX_IGS_REASON_NOT_FOUND 501
181	/** CR0 fixed1 bits invalid. */
182	#define VMX_IGS_CR0_FIXED1 502
183	/** CR0 fixed0 bits invalid. */
184	#define VMX_IGS_CR0_FIXED0 503
185	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
186	#define VMX_IGS_CR0_PG_PE_COMBO 504
187	/** CR4 fixed1 bits invalid. */
188	#define VMX_IGS_CR4_FIXED1 505
189	/** CR4 fixed0 bits invalid. */
190	#define VMX_IGS_CR4_FIXED0 506
191	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
192	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
193	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
194	/** CR0.PG not set for long-mode when not using unrestricted guest. */
195	#define VMX_IGS_CR0_PG_LONGMODE 508
196	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
197	#define VMX_IGS_CR4_PAE_LONGMODE 509
198	/** CR4.PCIDE set for 32-bit guest. */
199	#define VMX_IGS_CR4_PCIDE 510
200	/** VMCS' DR7 reserved bits not set to 0. */
201	#define VMX_IGS_DR7_RESERVED 511
202	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
203	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
204	/** VMCS' EFER MSR reserved bits not set to 0. */
205	#define VMX_IGS_EFER_MSR_RESERVED 513
206	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
207	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
208	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
209	* without unrestricted guest. */
210	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
211	/** CS.Attr.P bit invalid. */
212	#define VMX_IGS_CS_ATTR_P_INVALID 516
213	/** CS.Attr reserved bits not set to 0. */
214	#define VMX_IGS_CS_ATTR_RESERVED 517
215	/** CS.Attr.G bit invalid. */
216	#define VMX_IGS_CS_ATTR_G_INVALID 518
217	/** CS is unusable. */
218	#define VMX_IGS_CS_ATTR_UNUSABLE 519
219	/** CS and SS DPL unequal. */
220	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
221	/** CS and SS DPL mismatch. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
223	/** CS Attr.Type invalid. */
224	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
225	/** CS and SS RPL unequal. */
226	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
227	/** SS.Attr.DPL and SS RPL unequal. */
228	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
229	/** SS.Attr.DPL invalid for segment type. */
230	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
231	/** SS.Attr.Type invalid. */
232	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
233	/** SS.Attr.P bit invalid. */
234	#define VMX_IGS_SS_ATTR_P_INVALID 527
235	/** SS.Attr reserved bits not set to 0. */
236	#define VMX_IGS_SS_ATTR_RESERVED 528
237	/** SS.Attr.G bit invalid. */
238	#define VMX_IGS_SS_ATTR_G_INVALID 529
239	/** DS.Attr.A bit invalid. */
240	#define VMX_IGS_DS_ATTR_A_INVALID 530
241	/** DS.Attr.P bit invalid. */
242	#define VMX_IGS_DS_ATTR_P_INVALID 531
243	/** DS.Attr.DPL and DS RPL unequal. */
244	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
245	/** DS.Attr reserved bits not set to 0. */
246	#define VMX_IGS_DS_ATTR_RESERVED 533
247	/** DS.Attr.G bit invalid. */
248	#define VMX_IGS_DS_ATTR_G_INVALID 534
249	/** DS.Attr.Type invalid. */
250	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
251	/** ES.Attr.A bit invalid. */
252	#define VMX_IGS_ES_ATTR_A_INVALID 536
253	/** ES.Attr.P bit invalid. */
254	#define VMX_IGS_ES_ATTR_P_INVALID 537
255	/** ES.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
257	/** ES.Attr reserved bits not set to 0. */
258	#define VMX_IGS_ES_ATTR_RESERVED 539
259	/** ES.Attr.G bit invalid. */
260	#define VMX_IGS_ES_ATTR_G_INVALID 540
261	/** ES.Attr.Type invalid. */
262	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
263	/** FS.Attr.A bit invalid. */
264	#define VMX_IGS_FS_ATTR_A_INVALID 542
265	/** FS.Attr.P bit invalid. */
266	#define VMX_IGS_FS_ATTR_P_INVALID 543
267	/** FS.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
269	/** FS.Attr reserved bits not set to 0. */
270	#define VMX_IGS_FS_ATTR_RESERVED 545
271	/** FS.Attr.G bit invalid. */
272	#define VMX_IGS_FS_ATTR_G_INVALID 546
273	/** FS.Attr.Type invalid. */
274	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
275	/** GS.Attr.A bit invalid. */
276	#define VMX_IGS_GS_ATTR_A_INVALID 548
277	/** GS.Attr.P bit invalid. */
278	#define VMX_IGS_GS_ATTR_P_INVALID 549
279	/** GS.Attr.DPL and DS RPL unequal. */
280	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
281	/** GS.Attr reserved bits not set to 0. */
282	#define VMX_IGS_GS_ATTR_RESERVED 551
283	/** GS.Attr.G bit invalid. */
284	#define VMX_IGS_GS_ATTR_G_INVALID 552
285	/** GS.Attr.Type invalid. */
286	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
287	/** V86 mode CS.Base invalid. */
288	#define VMX_IGS_V86_CS_BASE_INVALID 554
289	/** V86 mode CS.Limit invalid. */
290	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
291	/** V86 mode CS.Attr invalid. */
292	#define VMX_IGS_V86_CS_ATTR_INVALID 556
293	/** V86 mode SS.Base invalid. */
294	#define VMX_IGS_V86_SS_BASE_INVALID 557
295	/** V86 mode SS.Limit invalid. */
296	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
297	/** V86 mode SS.Attr invalid. */
298	#define VMX_IGS_V86_SS_ATTR_INVALID 559
299	/** V86 mode DS.Base invalid. */
300	#define VMX_IGS_V86_DS_BASE_INVALID 560
301	/** V86 mode DS.Limit invalid. */
302	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
303	/** V86 mode DS.Attr invalid. */
304	#define VMX_IGS_V86_DS_ATTR_INVALID 562
305	/** V86 mode ES.Base invalid. */
306	#define VMX_IGS_V86_ES_BASE_INVALID 563
307	/** V86 mode ES.Limit invalid. */
308	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
309	/** V86 mode ES.Attr invalid. */
310	#define VMX_IGS_V86_ES_ATTR_INVALID 565
311	/** V86 mode FS.Base invalid. */
312	#define VMX_IGS_V86_FS_BASE_INVALID 566
313	/** V86 mode FS.Limit invalid. */
314	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
315	/** V86 mode FS.Attr invalid. */
316	#define VMX_IGS_V86_FS_ATTR_INVALID 568
317	/** V86 mode GS.Base invalid. */
318	#define VMX_IGS_V86_GS_BASE_INVALID 569
319	/** V86 mode GS.Limit invalid. */
320	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
321	/** V86 mode GS.Attr invalid. */
322	#define VMX_IGS_V86_GS_ATTR_INVALID 571
323	/** Longmode CS.Base invalid. */
324	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
325	/** Longmode SS.Base invalid. */
326	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
327	/** Longmode DS.Base invalid. */
328	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
329	/** Longmode ES.Base invalid. */
330	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
331	/** SYSENTER ESP is not canonical. */
332	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
333	/** SYSENTER EIP is not canonical. */
334	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
335	/** PAT MSR invalid. */
336	#define VMX_IGS_PAT_MSR_INVALID 578
337	/** PAT MSR reserved bits not set to 0. */
338	#define VMX_IGS_PAT_MSR_RESERVED 579
339	/** GDTR.Base is not canonical. */
340	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
341	/** IDTR.Base is not canonical. */
342	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
343	/** GDTR.Limit invalid. */
344	#define VMX_IGS_GDTR_LIMIT_INVALID 582
345	/** IDTR.Limit invalid. */
346	#define VMX_IGS_IDTR_LIMIT_INVALID 583
347	/** Longmode RIP is invalid. */
348	#define VMX_IGS_LONGMODE_RIP_INVALID 584
349	/** RFLAGS reserved bits not set to 0. */
350	#define VMX_IGS_RFLAGS_RESERVED 585
351	/** RFLAGS RA1 reserved bits not set to 1. */
352	#define VMX_IGS_RFLAGS_RESERVED1 586
353	/** RFLAGS.VM (V86 mode) invalid. */
354	#define VMX_IGS_RFLAGS_VM_INVALID 587
355	/** RFLAGS.IF invalid. */
356	#define VMX_IGS_RFLAGS_IF_INVALID 588
357	/** Activity state invalid. */
358	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
359	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
360	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
361	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
362	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
363	/** Activity state SIPI WAIT invalid. */
364	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
365	/** Interruptibility state reserved bits not set to 0. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
367	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
369	/** Interruptibility state block-by-STI invalid for EFLAGS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
371	/** Interruptibility state invalid while trying to deliver external
372	* interrupt. */
373	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
374	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
375	* NMI. */
376	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
377	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
379	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
381	/** Interruptibility state block-by-STI (maybe) invalid when trying to
382	* deliver an NMI. */
383	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
384	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
385	* active. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
387	/** Pending debug exceptions reserved bits not set to 0. */
388	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
389	/** Longmode pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
391	/** Pending debug exceptions.BS bit is not set when it should be. */
392	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
393	/** Pending debug exceptions.BS bit is not clear when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
395	/** VMCS link pointer reserved bits not set to 0. */
396	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
397	/** TR cannot index into LDT, TI bit MBZ. */
398	#define VMX_IGS_TR_TI_INVALID 607
399	/** LDTR cannot index into LDT. TI bit MBZ. */
400	#define VMX_IGS_LDTR_TI_INVALID 608
401	/** TR.Base is not canonical. */
402	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
403	/** FS.Base is not canonical. */
404	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
405	/** GS.Base is not canonical. */
406	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
407	/** LDTR.Base is not canonical. */
408	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
409	/** TR is unusable. */
410	#define VMX_IGS_TR_ATTR_UNUSABLE 613
411	/** TR.Attr.S bit invalid. */
412	#define VMX_IGS_TR_ATTR_S_INVALID 614
413	/** TR is not present. */
414	#define VMX_IGS_TR_ATTR_P_INVALID 615
415	/** TR.Attr reserved bits not set to 0. */
416	#define VMX_IGS_TR_ATTR_RESERVED 616
417	/** TR.Attr.G bit invalid. */
418	#define VMX_IGS_TR_ATTR_G_INVALID 617
419	/** Longmode TR.Attr.Type invalid. */
420	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
421	/** TR.Attr.Type invalid. */
422	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
423	/** CS.Attr.S invalid. */
424	#define VMX_IGS_CS_ATTR_S_INVALID 620
425	/** CS.Attr.DPL invalid. */
426	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
427	/** PAE PDPTE reserved bits not set to 0. */
428	#define VMX_IGS_PAE_PDPTE_RESERVED 623
429	/** VMCS link pointer does not point to a shadow VMCS. */
430	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
431	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
432	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
433	/** @} */
434
435	/** @name VMX VMCS-Read cache indices.
436	* @{
437	*/
438	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
439	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
440	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
441	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
442	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
443	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
444	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
445	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
446	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
447	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
448	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
449	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
450	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
451	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
452	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
453	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
454	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
455	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
456	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
457	/** @} */
458
459	/** @name VMX Extended Page Tables (EPT) Common Bits
460	* @{ */
461	/** Bit 0 - Readable (we often think of it as present). */
462	#define EPT_E_BIT_READ 0
463	#define EPT_E_READ RT_BIT_64(EPT_E_BIT_READ) /*< @see EPT_E_BIT_READ /
464	/** Bit 1 - Writable. */
465	#define EPT_E_BIT_WRITE 1
466	#define EPT_E_WRITE RT_BIT_64(EPT_E_BIT_WRITE) /*< @see EPT_E_BIT_WRITE /
467	/** Bit 2 - Executable.
468	* @note This controls supervisor instruction fetching if mode-based
469	* execution control is enabled. */
470	#define EPT_E_BIT_EXECUTE 2
471	#define EPT_E_EXECUTE RT_BIT_64(EPT_E_BIT_EXECUTE) /*< @see EPT_E_BIT_EXECUTE /
472	/** Bits 3-5 - Memory type mask (leaf only, MBZ).
473	* The memory type is only applicable for leaf entries and MBZ for
474	* non-leaf (causes miconfiguration exit). */
475	#define EPT_E_TYPE_MASK UINT64_C(0x0038)
476	/** Bits 3-5 - Memory type shifted mask. */
477	#define EPT_E_TYPE_SMASK UINT64_C(0x0007)
478	/** Bits 3-5 - Memory type shift count. */
479	#define EPT_E_TYPE_SHIFT 3
480	/** Bits 3-5 - Memory type: UC. */
481	#define EPT_E_TYPE_UC (UINT64_C(0) << EPT_E_TYPE_SHIFT)
482	/** Bits 3-5 - Memory type: WC. */
483	#define EPT_E_TYPE_WC (UINT64_C(1) << EPT_E_TYPE_SHIFT)
484	/** Bits 3-5 - Memory type: Invalid (2). */
485	#define EPT_E_TYPE_INVALID_2 (UINT64_C(2) << EPT_E_TYPE_SHIFT)
486	/** Bits 3-5 - Memory type: Invalid (3). */
487	#define EPT_E_TYPE_INVALID_3 (UINT64_C(3) << EPT_E_TYPE_SHIFT)
488	/** Bits 3-5 - Memory type: WT. */
489	#define EPT_E_TYPE_WT (UINT64_C(4) << EPT_E_TYPE_SHIFT)
490	/** Bits 3-5 - Memory type: WP. */
491	#define EPT_E_TYPE_WP (UINT64_C(5) << EPT_E_TYPE_SHIFT)
492	/** Bits 3-5 - Memory type: WB. */
493	#define EPT_E_TYPE_WB (UINT64_C(6) << EPT_E_TYPE_SHIFT)
494	/** Bits 3-5 - Memory type: Invalid (7). */
495	#define EPT_E_TYPE_INVALID_7 (UINT64_C(7) << EPT_E_TYPE_SHIFT)
496
497	/** Bit 6 - Ignore page attribute table (leaf, MBZ). */
498	#define EPT_E_BIT_IGNORE_PAT 6
499	#define EPT_E_IGNORE_PAT RT_BIT_64(EPT_E_BIT_IGNORE_PAT) /*< @see EPT_E_BIT_IGNORE_PAT /
500	/** Bit 7 - Leaf entry (MBZ in PML4, ignored in PT). */
501	#define EPT_E_BIT_LEAF 7
502	#define EPT_E_LEAF RT_BIT_64(EPT_E_BIT_LEAF) /*< @see EPT_E_BIT_LEAF /
503	/** Bit 8 - Accessed (all levels).
504	* @note Ignored and not written when EPTP bit 6 is 0. */
505	#define EPT_E_BIT_ACCESSED 8
506	#define EPT_E_ACCESSED RT_BIT_64(EPT_E_BIT_ACCESSED) /*< @see EPT_E_BIT_ACCESSED /
507	/** Bit 9 - Dirty (leaf only).
508	* @note Ignored and not written when EPTP bit 6 is 0. */
509	#define EPT_E_BIT_DIRTY 9
510	#define EPT_E_DIRTY RT_BIT_64(EPT_E_BIT_DIRTY) /*< @see EPT_E_BIT_DIRTY /
511	/** Bit 10 - Executable for usermode.
512	* @note This ignored if mode-based execution control is disabled. */
513	#define EPT_E_BIT_USER_EXECUTE 10
514	#define EPT_E_USER_EXECUTE RT_BIT_64(EPT_E_BIT_USER_EXECUTE) /*< @see EPT_E_BIT_USER_EXECUTE /
515
516	/* 11 is always ignored (at time of writing) */
517
518	/** Bits 12-51 - Physical Page number of the next level. */
519	#define EPT_E_PG_MASK UINT64_C(0x000ffffffffff000)
520
521	/** Bit 60 - Supervisor shadow stack (leaf only, ignored).
522	* @note Ignored if EPT bit 7 is 0. */
523	#define EPT_E_BIT_SHADOW_STACK 60
524	#define EPT_E_SHADOW_STACK RT_BIT_64(EPT_E_BIT_SHADOW_STACK) /*< @see EPT_E_BIT_SHADOW_STACK/
525	/** Bit 61 - Sub-page write permissions (PT only, ignored).
526	* @note Ignored if sub-page write permissions for EPT is disabled. */
527	#define EPT_E_BIT_SHADOW_STACK 60
528	#define EPT_E_SHADOW_STACK RT_BIT_64(EPT_E_BIT_SHADOW_STACK) /*< @see EPT_E_BIT_SHADOW_STACK/
529
530	/* Bit 62 is always ignored at time of writing. */
531
532	/** Bit 63 - Supress \#VE (leaf only, ignored).
533	* @note Ignored if EPT violation to \#VE conversion is disabled. */
534	#define EPT_E_BIT_IGNORE_VE 63
535	#define EPT_E_IGNORE_VE RT_BIT_64(EPT_E_BIT_IGNORE_VE) /*< @see EPT_E_BIT_IGNORE_VE/
536	/** @} */
537
538
539	/** @name VMX Extended Page Tables (EPT) Structures
540	* @{
541	*/
542
543	/**
544	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
545	*/
546	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
547
548	/**
549	* EPT Page Directory Pointer Entry. Bit view.
550	* In accordance with the VT-x spec.
551	*
552	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
553	* this did cause trouble with one compiler/version).
554	*/
555	typedef struct EPTPML4EBITS
556	{
557	/** Present bit. */
558	RT_GCC_EXTENSION uint64_t u1Present : 1;
559	/** Writable bit. */
560	RT_GCC_EXTENSION uint64_t u1Write : 1;
561	/** Executable bit. */
562	RT_GCC_EXTENSION uint64_t u1Execute : 1;
563	/** Reserved (must be 0). */
564	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
565	/** Available for software. */
566	RT_GCC_EXTENSION uint64_t u4Available : 4;
567	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
568	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
569	/** Available for software. */
570	RT_GCC_EXTENSION uint64_t u12Available : 12;
571	} EPTPML4EBITS;
572	AssertCompileSize(EPTPML4EBITS, 8);
573
574	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
575	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
576	/** The page shift to get the PML4 index. */
577	#define EPT_PML4_SHIFT X86_PML4_SHIFT
578	/** The PML4 index mask (apply to a shifted page address). */
579	#define EPT_PML4_MASK X86_PML4_MASK
580
581	/**
582	* EPT PML4E.
583	* In accordance with the VT-x spec.
584	*/
585	typedef union EPTPML4E
586	{
587	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
588	/** Normal view. */
589	EPTPML4EBITS n;
590	#endif
591	/** Unsigned integer view. */
592	X86PGPAEUINT u;
593	/** 64 bit unsigned integer view. */
594	uint64_t au64[1];
595	/** 32 bit unsigned integer view. */
596	uint32_t au32[2];
597	} EPTPML4E;
598	AssertCompileSize(EPTPML4E, 8);
599	/** Pointer to a PML4 table entry. */
600	typedef EPTPML4E *PEPTPML4E;
601	/** Pointer to a const PML4 table entry. */
602	typedef const EPTPML4E *PCEPTPML4E;
603
604	/**
605	* EPT PML4 Table.
606	* In accordance with the VT-x spec.
607	*/
608	typedef struct EPTPML4
609	{
610	EPTPML4E a[EPT_PG_ENTRIES];
611	} EPTPML4;
612	AssertCompileSize(EPTPML4, 0x1000);
613	/** Pointer to an EPT PML4 Table. */
614	typedef EPTPML4 *PEPTPML4;
615	/** Pointer to a const EPT PML4 Table. */
616	typedef const EPTPML4 *PCEPTPML4;
617
618	/**
619	* EPT Page Directory Pointer Entry. Bit view.
620	* In accordance with the VT-x spec.
621	*/
622	typedef struct EPTPDPTEBITS
623	{
624	/** Present bit. */
625	RT_GCC_EXTENSION uint64_t u1Present : 1;
626	/** Writable bit. */
627	RT_GCC_EXTENSION uint64_t u1Write : 1;
628	/** Executable bit. */
629	RT_GCC_EXTENSION uint64_t u1Execute : 1;
630	/** Reserved (must be 0). */
631	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
632	/** Available for software. */
633	RT_GCC_EXTENSION uint64_t u4Available : 4;
634	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
635	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
636	/** Available for software. */
637	RT_GCC_EXTENSION uint64_t u12Available : 12;
638	} EPTPDPTEBITS;
639	AssertCompileSize(EPTPDPTEBITS, 8);
640
641	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
642	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
643	/** The page shift to get the PDPT index. */
644	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
645	/** The PDPT index mask (apply to a shifted page address). */
646	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
647
648	/**
649	* EPT Page Directory Pointer.
650	* In accordance with the VT-x spec.
651	*/
652	typedef union EPTPDPTE
653	{
654	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
655	/** Normal view. */
656	EPTPDPTEBITS n;
657	#endif
658	/** Unsigned integer view. */
659	X86PGPAEUINT u;
660	/** 64 bit unsigned integer view. */
661	uint64_t au64[1];
662	/** 32 bit unsigned integer view. */
663	uint32_t au32[2];
664	} EPTPDPTE;
665	AssertCompileSize(EPTPDPTE, 8);
666	/** Pointer to an EPT Page Directory Pointer Entry. */
667	typedef EPTPDPTE *PEPTPDPTE;
668	/** Pointer to a const EPT Page Directory Pointer Entry. */
669	typedef const EPTPDPTE *PCEPTPDPTE;
670
671	/**
672	* EPT Page Directory Pointer Table.
673	* In accordance with the VT-x spec.
674	*/
675	typedef struct EPTPDPT
676	{
677	EPTPDPTE a[EPT_PG_ENTRIES];
678	} EPTPDPT;
679	AssertCompileSize(EPTPDPT, 0x1000);
680	/** Pointer to an EPT Page Directory Pointer Table. */
681	typedef EPTPDPT *PEPTPDPT;
682	/** Pointer to a const EPT Page Directory Pointer Table. */
683	typedef const EPTPDPT *PCEPTPDPT;
684
685	/**
686	* EPT Page Directory Table Entry. Bit view.
687	* In accordance with the VT-x spec.
688	*/
689	typedef struct EPTPDEBITS
690	{
691	/** Present bit. */
692	RT_GCC_EXTENSION uint64_t u1Present : 1;
693	/** Writable bit. */
694	RT_GCC_EXTENSION uint64_t u1Write : 1;
695	/** Executable bit. */
696	RT_GCC_EXTENSION uint64_t u1Execute : 1;
697	/** Reserved (must be 0). */
698	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
699	/** Big page (must be 0 here). */
700	RT_GCC_EXTENSION uint64_t u1Size : 1;
701	/** Available for software. */
702	RT_GCC_EXTENSION uint64_t u4Available : 4;
703	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
704	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
705	/** Available for software. */
706	RT_GCC_EXTENSION uint64_t u12Available : 12;
707	} EPTPDEBITS;
708	AssertCompileSize(EPTPDEBITS, 8);
709
710	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
711	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
712	/** The page shift to get the PD index. */
713	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
714	/** The PD index mask (apply to a shifted page address). */
715	#define EPT_PD_MASK X86_PD_PAE_MASK
716
717	/**
718	* EPT 2MB Page Directory Table Entry. Bit view.
719	* In accordance with the VT-x spec.
720	*/
721	typedef struct EPTPDE2MBITS
722	{
723	/** Present bit. */
724	RT_GCC_EXTENSION uint64_t u1Present : 1;
725	/** Writable bit. */
726	RT_GCC_EXTENSION uint64_t u1Write : 1;
727	/** Executable bit. */
728	RT_GCC_EXTENSION uint64_t u1Execute : 1;
729	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
730	RT_GCC_EXTENSION uint64_t u3EMT : 3;
731	/** Ignore PAT memory type */
732	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
733	/** Big page (must be 1 here). */
734	RT_GCC_EXTENSION uint64_t u1Size : 1;
735	/** Available for software. */
736	RT_GCC_EXTENSION uint64_t u4Available : 4;
737	/** Reserved (must be 0). */
738	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
739	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
740	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
741	/** Available for software. */
742	RT_GCC_EXTENSION uint64_t u12Available : 12;
743	} EPTPDE2MBITS;
744	AssertCompileSize(EPTPDE2MBITS, 8);
745
746	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
747	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
748
749	/**
750	* EPT Page Directory Table Entry.
751	* In accordance with the VT-x spec.
752	*/
753	typedef union EPTPDE
754	{
755	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
756	/** Normal view. */
757	EPTPDEBITS n;
758	/** 2MB view (big). */
759	EPTPDE2MBITS b;
760	#endif
761	/** Unsigned integer view. */
762	X86PGPAEUINT u;
763	/** 64 bit unsigned integer view. */
764	uint64_t au64[1];
765	/** 32 bit unsigned integer view. */
766	uint32_t au32[2];
767	} EPTPDE;
768	AssertCompileSize(EPTPDE, 8);
769	/** Pointer to an EPT Page Directory Table Entry. */
770	typedef EPTPDE *PEPTPDE;
771	/** Pointer to a const EPT Page Directory Table Entry. */
772	typedef const EPTPDE *PCEPTPDE;
773
774	/**
775	* EPT Page Directory Table.
776	* In accordance with the VT-x spec.
777	*/
778	typedef struct EPTPD
779	{
780	EPTPDE a[EPT_PG_ENTRIES];
781	} EPTPD;
782	AssertCompileSize(EPTPD, 0x1000);
783	/** Pointer to an EPT Page Directory Table. */
784	typedef EPTPD *PEPTPD;
785	/** Pointer to a const EPT Page Directory Table. */
786	typedef const EPTPD *PCEPTPD;
787
788	/**
789	* EPT Page Table Entry. Bit view.
790	* In accordance with the VT-x spec.
791	*/
792	typedef struct EPTPTEBITS
793	{
794	/** 0 - Present bit.
795	* @remarks This is a convenience "misnomer". The bit actually indicates read access
796	* and the CPU will consider an entry with any of the first three bits set
797	* as present. Since all our valid entries will have this bit set, it can
798	* be used as a present indicator and allow some code sharing. */
799	RT_GCC_EXTENSION uint64_t u1Present : 1;
800	/** 1 - Writable bit. */
801	RT_GCC_EXTENSION uint64_t u1Write : 1;
802	/** 2 - Executable bit. */
803	RT_GCC_EXTENSION uint64_t u1Execute : 1;
804	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
805	RT_GCC_EXTENSION uint64_t u3EMT : 3;
806	/** 6 - Ignore PAT memory type */
807	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
808	/** 11:7 - Available for software. */
809	RT_GCC_EXTENSION uint64_t u5Available : 5;
810	/** 51:12 - Physical address of page. Restricted by maximum physical
811	* address width of the cpu. */
812	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
813	/** 63:52 - Available for software. */
814	RT_GCC_EXTENSION uint64_t u12Available : 12;
815	} EPTPTEBITS;
816	AssertCompileSize(EPTPTEBITS, 8);
817
818	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
819	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
820	/** The page shift to get the EPT PTE index. */
821	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
822	/** The EPT PT index mask (apply to a shifted page address). */
823	#define EPT_PT_MASK X86_PT_PAE_MASK
824
825	/**
826	* EPT Page Table Entry.
827	* In accordance with the VT-x spec.
828	*/
829	typedef union EPTPTE
830	{
831	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
832	/** Normal view. */
833	EPTPTEBITS n;
834	#endif
835	/** Unsigned integer view. */
836	X86PGPAEUINT u;
837	/** 64 bit unsigned integer view. */
838	uint64_t au64[1];
839	/** 32 bit unsigned integer view. */
840	uint32_t au32[2];
841	} EPTPTE;
842	AssertCompileSize(EPTPTE, 8);
843	/** Pointer to an EPT Page Directory Table Entry. */
844	typedef EPTPTE *PEPTPTE;
845	/** Pointer to a const EPT Page Directory Table Entry. */
846	typedef const EPTPTE *PCEPTPTE;
847
848	/**
849	* EPT Page Table.
850	* In accordance with the VT-x spec.
851	*/
852	typedef struct EPTPT
853	{
854	EPTPTE a[EPT_PG_ENTRIES];
855	} EPTPT;
856	AssertCompileSize(EPTPT, 0x1000);
857	/** Pointer to an extended page table. */
858	typedef EPTPT *PEPTPT;
859	/** Pointer to a const extended table. */
860	typedef const EPTPT *PCEPTPT;
861
862	/** @} */
863
864	/**
865	* VMX VPID flush types.
866	* Valid enum members are in accordance with the VT-x spec.
867	*/
868	typedef enum
869	{
870	/** Invalidate a specific page. */
871	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
872	/** Invalidate one context (specific VPID). */
873	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
874	/** Invalidate all contexts (all VPIDs). */
875	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
876	/** Invalidate a single VPID context retaining global mappings. */
877	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
878	/** Unsupported by VirtualBox. */
879	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
880	/** Unsupported by CPU. */
881	VMXTLBFLUSHVPID_NONE = 0xbad1
882	} VMXTLBFLUSHVPID;
883	AssertCompileSize(VMXTLBFLUSHVPID, 4);
884
885	/**
886	* VMX EPT flush types.
887	* @note Valid enums values are in accordance with the VT-x spec.
888	*/
889	typedef enum
890	{
891	/** Invalidate one context (specific EPT). */
892	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
893	/* Invalidate all contexts (all EPTs) */
894	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
895	/** Unsupported by VirtualBox. */
896	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
897	/** Unsupported by CPU. */
898	VMXTLBFLUSHEPT_NONE = 0xbad1
899	} VMXTLBFLUSHEPT;
900	AssertCompileSize(VMXTLBFLUSHEPT, 4);
901
902	/**
903	* VMX Posted Interrupt Descriptor.
904	* In accordance with the VT-x spec.
905	*/
906	typedef struct VMXPOSTEDINTRDESC
907	{
908	uint32_t aVectorBitmap[8];
909	uint32_t fOutstandingNotification : 1;
910	uint32_t uReserved0 : 31;
911	uint8_t au8Reserved0[28];
912	} VMXPOSTEDINTRDESC;
913	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
914	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
915	/** Pointer to a posted interrupt descriptor. */
916	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
917	/** Pointer to a const posted interrupt descriptor. */
918	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
919
920	/**
921	* VMX VMCS revision identifier.
922	* In accordance with the VT-x spec.
923	*/
924	typedef union
925	{
926	struct
927	{
928	/** Revision identifier. */
929	uint32_t u31RevisionId : 31;
930	/** Whether this is a shadow VMCS. */
931	uint32_t fIsShadowVmcs : 1;
932	} n;
933	/* The unsigned integer view. */
934	uint32_t u;
935	} VMXVMCSREVID;
936	AssertCompileSize(VMXVMCSREVID, 4);
937	/** Pointer to the VMXVMCSREVID union. */
938	typedef VMXVMCSREVID *PVMXVMCSREVID;
939	/** Pointer to a const VMXVMCSREVID union. */
940	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
941
942	/**
943	* VMX VM-exit instruction information.
944	* In accordance with the VT-x spec.
945	*/
946	typedef union
947	{
948	/** Plain unsigned int representation. */
949	uint32_t u;
950
951	/** INS and OUTS information. */
952	struct
953	{
954	uint32_t u7Reserved0 : 7;
955	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
956	uint32_t u3AddrSize : 3;
957	uint32_t u5Reserved1 : 5;
958	/** The segment register (X86_SREG_XXX). */
959	uint32_t iSegReg : 3;
960	uint32_t uReserved2 : 14;
961	} StrIo;
962
963	/** INVEPT, INVPCID, INVVPID information. */
964	struct
965	{
966	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
967	uint32_t u2Scaling : 2;
968	uint32_t u5Undef0 : 5;
969	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
970	uint32_t u3AddrSize : 3;
971	/** Cleared to 0. */
972	uint32_t u1Cleared0 : 1;
973	uint32_t u4Undef0 : 4;
974	/** The segment register (X86_SREG_XXX). */
975	uint32_t iSegReg : 3;
976	/** The index register (X86_GREG_XXX). */
977	uint32_t iIdxReg : 4;
978	/** Set if index register is invalid. */
979	uint32_t fIdxRegInvalid : 1;
980	/** The base register (X86_GREG_XXX). */
981	uint32_t iBaseReg : 4;
982	/** Set if base register is invalid. */
983	uint32_t fBaseRegInvalid : 1;
984	/** Register 2 (X86_GREG_XXX). */
985	uint32_t iReg2 : 4;
986	} Inv;
987
988	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
989	struct
990	{
991	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
992	uint32_t u2Scaling : 2;
993	uint32_t u5Reserved0 : 5;
994	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
995	uint32_t u3AddrSize : 3;
996	/** Cleared to 0. */
997	uint32_t u1Cleared0 : 1;
998	uint32_t u4Reserved0 : 4;
999	/** The segment register (X86_SREG_XXX). */
1000	uint32_t iSegReg : 3;
1001	/** The index register (X86_GREG_XXX). */
1002	uint32_t iIdxReg : 4;
1003	/** Set if index register is invalid. */
1004	uint32_t fIdxRegInvalid : 1;
1005	/** The base register (X86_GREG_XXX). */
1006	uint32_t iBaseReg : 4;
1007	/** Set if base register is invalid. */
1008	uint32_t fBaseRegInvalid : 1;
1009	/** Register 2 (X86_GREG_XXX). */
1010	uint32_t iReg2 : 4;
1011	} VmxXsave;
1012
1013	/** LIDT, LGDT, SIDT, SGDT information. */
1014	struct
1015	{
1016	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1017	uint32_t u2Scaling : 2;
1018	uint32_t u5Undef0 : 5;
1019	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1020	uint32_t u3AddrSize : 3;
1021	/** Always cleared to 0. */
1022	uint32_t u1Cleared0 : 1;
1023	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
1024	uint32_t uOperandSize : 1;
1025	uint32_t u3Undef0 : 3;
1026	/** The segment register (X86_SREG_XXX). */
1027	uint32_t iSegReg : 3;
1028	/** The index register (X86_GREG_XXX). */
1029	uint32_t iIdxReg : 4;
1030	/** Set if index register is invalid. */
1031	uint32_t fIdxRegInvalid : 1;
1032	/** The base register (X86_GREG_XXX). */
1033	uint32_t iBaseReg : 4;
1034	/** Set if base register is invalid. */
1035	uint32_t fBaseRegInvalid : 1;
1036	/** Instruction identity (VMX_INSTR_ID_XXX). */
1037	uint32_t u2InstrId : 2;
1038	uint32_t u2Undef0 : 2;
1039	} GdtIdt;
1040
1041	/** LLDT, LTR, SLDT, STR information. */
1042	struct
1043	{
1044	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1045	uint32_t u2Scaling : 2;
1046	uint32_t u1Undef0 : 1;
1047	/** Register 1 (X86_GREG_XXX). */
1048	uint32_t iReg1 : 4;
1049	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1050	uint32_t u3AddrSize : 3;
1051	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1052	uint32_t fIsRegOperand : 1;
1053	uint32_t u4Undef0 : 4;
1054	/** The segment register (X86_SREG_XXX). */
1055	uint32_t iSegReg : 3;
1056	/** The index register (X86_GREG_XXX). */
1057	uint32_t iIdxReg : 4;
1058	/** Set if index register is invalid. */
1059	uint32_t fIdxRegInvalid : 1;
1060	/** The base register (X86_GREG_XXX). */
1061	uint32_t iBaseReg : 4;
1062	/** Set if base register is invalid. */
1063	uint32_t fBaseRegInvalid : 1;
1064	/** Instruction identity (VMX_INSTR_ID_XXX). */
1065	uint32_t u2InstrId : 2;
1066	uint32_t u2Undef0 : 2;
1067	} LdtTr;
1068
1069	/** RDRAND, RDSEED information. */
1070	struct
1071	{
1072	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1073	uint32_t u2Undef0 : 2;
1074	/** Destination register (X86_GREG_XXX). */
1075	uint32_t iReg1 : 4;
1076	uint32_t u4Undef0 : 4;
1077	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1078	uint32_t u2OperandSize : 2;
1079	uint32_t u19Def0 : 20;
1080	} RdrandRdseed;
1081
1082	/** VMREAD, VMWRITE information. */
1083	struct
1084	{
1085	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1086	uint32_t u2Scaling : 2;
1087	uint32_t u1Undef0 : 1;
1088	/** Register 1 (X86_GREG_XXX). */
1089	uint32_t iReg1 : 4;
1090	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1091	uint32_t u3AddrSize : 3;
1092	/** Memory or register operand. */
1093	uint32_t fIsRegOperand : 1;
1094	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1095	uint32_t u4Undef0 : 4;
1096	/** The segment register (X86_SREG_XXX). */
1097	uint32_t iSegReg : 3;
1098	/** The index register (X86_GREG_XXX). */
1099	uint32_t iIdxReg : 4;
1100	/** Set if index register is invalid. */
1101	uint32_t fIdxRegInvalid : 1;
1102	/** The base register (X86_GREG_XXX). */
1103	uint32_t iBaseReg : 4;
1104	/** Set if base register is invalid. */
1105	uint32_t fBaseRegInvalid : 1;
1106	/** Register 2 (X86_GREG_XXX). */
1107	uint32_t iReg2 : 4;
1108	} VmreadVmwrite;
1109
1110	/** This is a combination field of all instruction information. Note! Not all field
1111	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1112	* specialized fields are overwritten by their generic counterparts (e.g. no
1113	* instruction identity field). */
1114	struct
1115	{
1116	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1117	uint32_t u2Scaling : 2;
1118	uint32_t u1Undef0 : 1;
1119	/** Register 1 (X86_GREG_XXX). */
1120	uint32_t iReg1 : 4;
1121	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1122	uint32_t u3AddrSize : 3;
1123	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1124	uint32_t fIsRegOperand : 1;
1125	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1126	uint32_t uOperandSize : 2;
1127	uint32_t u2Undef0 : 2;
1128	/** The segment register (X86_SREG_XXX). */
1129	uint32_t iSegReg : 3;
1130	/** The index register (X86_GREG_XXX). */
1131	uint32_t iIdxReg : 4;
1132	/** Set if index register is invalid. */
1133	uint32_t fIdxRegInvalid : 1;
1134	/** The base register (X86_GREG_XXX). */
1135	uint32_t iBaseReg : 4;
1136	/** Set if base register is invalid. */
1137	uint32_t fBaseRegInvalid : 1;
1138	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1139	uint32_t iReg2 : 4;
1140	} All;
1141	} VMXEXITINSTRINFO;
1142	AssertCompileSize(VMXEXITINSTRINFO, 4);
1143	/** Pointer to a VMX VM-exit instruction info. struct. */
1144	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1145	/** Pointer to a const VMX VM-exit instruction info. struct. */
1146	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1147
1148
1149	/** @name VM-entry failure reported in Exit qualification.
1150	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1151	* @{
1152	*/
1153	/** No errors during VM-entry. */
1154	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1155	/** Not used. */
1156	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1157	/** Error while loading PDPTEs. */
1158	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1159	/** NMI injection when blocking-by-STI is set. */
1160	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1161	/** Invalid VMCS link pointer. */
1162	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1163	/** @} */
1164
1165
1166	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1167	* These are -not- specified by Intel but used internally by VirtualBox.
1168	* @{ */
1169	/** Guest software reads of this MSR must not cause a VM-exit. */
1170	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1171	/** Guest software reads of this MSR must cause a VM-exit. */
1172	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1173	/** Guest software writes to this MSR must not cause a VM-exit. */
1174	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1175	/** Guest software writes to this MSR must cause a VM-exit. */
1176	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1177	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1178	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1179	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1180	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1181	/** Mask of valid MSR read permissions. */
1182	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1183	/** Mask of valid MSR write permissions. */
1184	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1185	/** Mask of valid MSR permissions. */
1186	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1187	/** */
1188	/** Gets whether the MSR permission is valid or not. */
1189	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1190	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1191	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1192	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1193	/** @} */
1194
1195	/**
1196	* VMX MSR autoload/store slot.
1197	* In accordance with the VT-x spec.
1198	*/
1199	typedef struct VMXAUTOMSR
1200	{
1201	/** The MSR Id. */
1202	uint32_t u32Msr;
1203	/** Reserved (MBZ). */
1204	uint32_t u32Reserved;
1205	/** The MSR value. */
1206	uint64_t u64Value;
1207	} VMXAUTOMSR;
1208	AssertCompileSize(VMXAUTOMSR, 16);
1209	/** Pointer to an MSR load/store element. */
1210	typedef VMXAUTOMSR *PVMXAUTOMSR;
1211	/** Pointer to a const MSR load/store element. */
1212	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1213
1214	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1215	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1216
1217	/**
1218	* VMX tagged-TLB flush types.
1219	*/
1220	typedef enum
1221	{
1222	VMXTLBFLUSHTYPE_EPT,
1223	VMXTLBFLUSHTYPE_VPID,
1224	VMXTLBFLUSHTYPE_EPT_VPID,
1225	VMXTLBFLUSHTYPE_NONE
1226	} VMXTLBFLUSHTYPE;
1227	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1228	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1229	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1230	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1231
1232	/**
1233	* VMX controls MSR.
1234	* In accordance with the VT-x spec.
1235	*/
1236	typedef union
1237	{
1238	struct
1239	{
1240	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1241	uint32_t allowed0;
1242	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1243	* controls. */
1244	uint32_t allowed1;
1245	} n;
1246	uint64_t u;
1247	} VMXCTLSMSR;
1248	AssertCompileSize(VMXCTLSMSR, 8);
1249	/** Pointer to a VMXCTLSMSR union. */
1250	typedef VMXCTLSMSR *PVMXCTLSMSR;
1251	/** Pointer to a const VMXCTLSMSR union. */
1252	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1253
1254	/**
1255	* VMX MSRs.
1256	*/
1257	typedef struct VMXMSRS
1258	{
1259	/** VMX/SMX Feature control. */
1260	uint64_t u64FeatCtrl;
1261	/** Basic information. */
1262	uint64_t u64Basic;
1263	/** Pin-based VM-execution controls. */
1264	VMXCTLSMSR PinCtls;
1265	/** Processor-based VM-execution controls. */
1266	VMXCTLSMSR ProcCtls;
1267	/** Secondary processor-based VM-execution controls. */
1268	VMXCTLSMSR ProcCtls2;
1269	/** VM-exit controls. */
1270	VMXCTLSMSR ExitCtls;
1271	/** VM-entry controls. */
1272	VMXCTLSMSR EntryCtls;
1273	/** True pin-based VM-execution controls. */
1274	VMXCTLSMSR TruePinCtls;
1275	/** True processor-based VM-execution controls. */
1276	VMXCTLSMSR TrueProcCtls;
1277	/** True VM-entry controls. */
1278	VMXCTLSMSR TrueEntryCtls;
1279	/** True VM-exit controls. */
1280	VMXCTLSMSR TrueExitCtls;
1281	/** Miscellaneous data. */
1282	uint64_t u64Misc;
1283	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1284	uint64_t u64Cr0Fixed0;
1285	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1286	uint64_t u64Cr0Fixed1;
1287	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1288	uint64_t u64Cr4Fixed0;
1289	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1290	uint64_t u64Cr4Fixed1;
1291	/** VMCS enumeration. */
1292	uint64_t u64VmcsEnum;
1293	/** VM Functions. */
1294	uint64_t u64VmFunc;
1295	/** EPT, VPID capabilities. */
1296	uint64_t u64EptVpidCaps;
1297	/** Reserved for future. */
1298	uint64_t a_u64Reserved[9];
1299	} VMXMSRS;
1300	AssertCompileSizeAlignment(VMXMSRS, 8);
1301	AssertCompileSize(VMXMSRS, 224);
1302	/** Pointer to a VMXMSRS struct. */
1303	typedef VMXMSRS *PVMXMSRS;
1304	/** Pointer to a const VMXMSRS struct. */
1305	typedef const VMXMSRS *PCVMXMSRS;
1306
1307
1308	/**
1309	* LBR MSRs.
1310	*/
1311	typedef struct LBRMSRS
1312	{
1313	/** List of LastBranch-From-IP MSRs. */
1314	uint64_t au64BranchFromIpMsr[32];
1315	/** List of LastBranch-To-IP MSRs. */
1316	uint64_t au64BranchToIpMsr[32];
1317	/** The MSR containing the index to the most recent branch record. */
1318	uint64_t uBranchTosMsr;
1319	} LBRMSRS;
1320	AssertCompileSizeAlignment(LBRMSRS, 8);
1321	/** Pointer to a VMXMSRS struct. */
1322	typedef LBRMSRS *PLBRMSRS;
1323	/** Pointer to a const VMXMSRS struct. */
1324	typedef const LBRMSRS *PCLBRMSRS;
1325
1326
1327	/** @name VMX Basic Exit Reasons.
1328	* @{
1329	*/
1330	/** -1 Invalid exit code */
1331	#define VMX_EXIT_INVALID (-1)
1332	/** 0 Exception or non-maskable interrupt (NMI). */
1333	#define VMX_EXIT_XCPT_OR_NMI 0
1334	/** 1 External interrupt. */
1335	#define VMX_EXIT_EXT_INT 1
1336	/** 2 Triple fault. */
1337	#define VMX_EXIT_TRIPLE_FAULT 2
1338	/** 3 INIT signal. */
1339	#define VMX_EXIT_INIT_SIGNAL 3
1340	/** 4 Start-up IPI (SIPI). */
1341	#define VMX_EXIT_SIPI 4
1342	/** 5 I/O system-management interrupt (SMI). */
1343	#define VMX_EXIT_IO_SMI 5
1344	/** 6 Other SMI. */
1345	#define VMX_EXIT_SMI 6
1346	/** 7 Interrupt window exiting. */
1347	#define VMX_EXIT_INT_WINDOW 7
1348	/** 8 NMI window exiting. */
1349	#define VMX_EXIT_NMI_WINDOW 8
1350	/** 9 Task switch. */
1351	#define VMX_EXIT_TASK_SWITCH 9
1352	/** 10 Guest software attempted to execute CPUID. */
1353	#define VMX_EXIT_CPUID 10
1354	/** 11 Guest software attempted to execute GETSEC. */
1355	#define VMX_EXIT_GETSEC 11
1356	/** 12 Guest software attempted to execute HLT. */
1357	#define VMX_EXIT_HLT 12
1358	/** 13 Guest software attempted to execute INVD. */
1359	#define VMX_EXIT_INVD 13
1360	/** 14 Guest software attempted to execute INVLPG. */
1361	#define VMX_EXIT_INVLPG 14
1362	/** 15 Guest software attempted to execute RDPMC. */
1363	#define VMX_EXIT_RDPMC 15
1364	/** 16 Guest software attempted to execute RDTSC. */
1365	#define VMX_EXIT_RDTSC 16
1366	/** 17 Guest software attempted to execute RSM in SMM. */
1367	#define VMX_EXIT_RSM 17
1368	/** 18 Guest software executed VMCALL. */
1369	#define VMX_EXIT_VMCALL 18
1370	/** 19 Guest software executed VMCLEAR. */
1371	#define VMX_EXIT_VMCLEAR 19
1372	/** 20 Guest software executed VMLAUNCH. */
1373	#define VMX_EXIT_VMLAUNCH 20
1374	/** 21 Guest software executed VMPTRLD. */
1375	#define VMX_EXIT_VMPTRLD 21
1376	/** 22 Guest software executed VMPTRST. */
1377	#define VMX_EXIT_VMPTRST 22
1378	/** 23 Guest software executed VMREAD. */
1379	#define VMX_EXIT_VMREAD 23
1380	/** 24 Guest software executed VMRESUME. */
1381	#define VMX_EXIT_VMRESUME 24
1382	/** 25 Guest software executed VMWRITE. */
1383	#define VMX_EXIT_VMWRITE 25
1384	/** 26 Guest software executed VMXOFF. */
1385	#define VMX_EXIT_VMXOFF 26
1386	/** 27 Guest software executed VMXON. */
1387	#define VMX_EXIT_VMXON 27
1388	/** 28 Control-register accesses. */
1389	#define VMX_EXIT_MOV_CRX 28
1390	/** 29 Debug-register accesses. */
1391	#define VMX_EXIT_MOV_DRX 29
1392	/** 30 I/O instruction. */
1393	#define VMX_EXIT_IO_INSTR 30
1394	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1395	#define VMX_EXIT_RDMSR 31
1396	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1397	#define VMX_EXIT_WRMSR 32
1398	/** 33 VM-entry failure due to invalid guest state. */
1399	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1400	/** 34 VM-entry failure due to MSR loading. */
1401	#define VMX_EXIT_ERR_MSR_LOAD 34
1402	/** 36 Guest software executed MWAIT. */
1403	#define VMX_EXIT_MWAIT 36
1404	/** 37 VM-exit due to monitor trap flag. */
1405	#define VMX_EXIT_MTF 37
1406	/** 39 Guest software attempted to execute MONITOR. */
1407	#define VMX_EXIT_MONITOR 39
1408	/** 40 Guest software attempted to execute PAUSE. */
1409	#define VMX_EXIT_PAUSE 40
1410	/** 41 VM-entry failure due to machine-check. */
1411	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1412	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1413	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1414	/** 44 APIC access. Guest software attempted to access memory at a physical
1415	* address on the APIC-access page. */
1416	#define VMX_EXIT_APIC_ACCESS 44
1417	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1418	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1419	#define VMX_EXIT_VIRTUALIZED_EOI 45
1420	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1421	* SGDT, or SIDT. */
1422	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1423	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1424	* SLDT, or STR. */
1425	#define VMX_EXIT_LDTR_TR_ACCESS 47
1426	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1427	* was disallowed by the configuration of the EPT paging structures. */
1428	#define VMX_EXIT_EPT_VIOLATION 48
1429	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1430	* address encountered a misconfigured EPT paging-structure entry. */
1431	#define VMX_EXIT_EPT_MISCONFIG 49
1432	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1433	#define VMX_EXIT_INVEPT 50
1434	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1435	#define VMX_EXIT_RDTSCP 51
1436	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1437	#define VMX_EXIT_PREEMPT_TIMER 52
1438	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1439	#define VMX_EXIT_INVVPID 53
1440	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1441	#define VMX_EXIT_WBINVD 54
1442	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1443	#define VMX_EXIT_XSETBV 55
1444	/** 56 APIC write. Guest completed write to virtual-APIC. */
1445	#define VMX_EXIT_APIC_WRITE 56
1446	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1447	#define VMX_EXIT_RDRAND 57
1448	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1449	#define VMX_EXIT_INVPCID 58
1450	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1451	#define VMX_EXIT_VMFUNC 59
1452	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1453	#define VMX_EXIT_ENCLS 60
1454	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1455	* enabled. */
1456	#define VMX_EXIT_RDSEED 61
1457	/** 62 - Page-modification log full. */
1458	#define VMX_EXIT_PML_FULL 62
1459	/** 63 - XSAVES. Guest software attempted to execute XSAVES and exiting was
1460	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1461	#define VMX_EXIT_XSAVES 63
1462	/** 64 - XRSTORS. Guest software attempted to execute XRSTORS and exiting
1463	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1464	#define VMX_EXIT_XRSTORS 64
1465	/** 66 - SPP-related event. Attempt to determine an access' sub-page write
1466	* permission encountered an SPP miss or misconfiguration. */
1467	#define VMX_EXIT_SPP_EVENT 66
1468	/* 67 - UMWAIT. Guest software attempted to execute UMWAIT and exiting was enabled. */
1469	#define VMX_EXIT_UMWAIT 67
1470	/** 68 - TPAUSE. Guest software attempted to execute TPAUSE and exiting was
1471	* enabled. */
1472	#define VMX_EXIT_TPAUSE 68
1473	/** The maximum exit value (inclusive). */
1474	#define VMX_EXIT_MAX (VMX_EXIT_TPAUSE)
1475	/** @} */
1476
1477
1478	/** @name VM Instruction Errors.
1479	* In accordance with the VT-x spec.
1480	* See Intel spec. "30.4 VM Instruction Error Numbers"
1481	* @{
1482	*/
1483	typedef enum
1484	{
1485	/** VMCALL executed in VMX root operation. */
1486	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1487	/** VMCLEAR with invalid physical address. */
1488	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1489	/** VMCLEAR with VMXON pointer. */
1490	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1491	/** VMLAUNCH with non-clear VMCS. */
1492	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1493	/** VMRESUME with non-launched VMCS. */
1494	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1495	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1496	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1497	/** VM-entry with invalid control field(s). */
1498	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1499	/** VM-entry with invalid host-state field(s). */
1500	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1501	/** VMPTRLD with invalid physical address. */
1502	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1503	/** VMPTRLD with VMXON pointer. */
1504	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1505	/** VMPTRLD with incorrect VMCS revision identifier. */
1506	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1507	/** VMREAD from unsupported VMCS component. */
1508	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1509	/** VMWRITE to unsupported VMCS component. */
1510	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1511	/** VMWRITE to read-only VMCS component. */
1512	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1513	/** VMXON executed in VMX root operation. */
1514	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1515	/** VM-entry with invalid executive-VMCS pointer. */
1516	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1517	/** VM-entry with non-launched executive VMCS. */
1518	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1519	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1520	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1521	/** VMCALL with non-clear VMCS. */
1522	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1523	/** VMCALL with invalid VM-exit control fields. */
1524	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1525	/** VMCALL with incorrect MSEG revision identifier. */
1526	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1527	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1528	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1529	/** VMCALL with invalid SMM-monitor features. */
1530	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1531	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1532	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1533	/** VM-entry with events blocked by MOV SS. */
1534	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1535	/** Invalid operand to INVEPT/INVVPID. */
1536	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1537	} VMXINSTRERR;
1538	/** @} */
1539
1540
1541	/** @name VMX abort reasons.
1542	* In accordance with the VT-x spec.
1543	* See Intel spec. "27.7 VMX Aborts".
1544	* Update HMGetVmxAbortDesc() if new reasons are added.
1545	* @{
1546	*/
1547	typedef enum
1548	{
1549	/** None - don't use this / uninitialized value. */
1550	VMXABORT_NONE = 0,
1551	/** VMX abort caused during saving of guest MSRs. */
1552	VMXABORT_SAVE_GUEST_MSRS = 1,
1553	/** VMX abort caused during host PDPTE checks. */
1554	VMXBOART_HOST_PDPTE = 2,
1555	/** VMX abort caused due to current VMCS being corrupted. */
1556	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1557	/** VMX abort caused during loading of host MSRs. */
1558	VMXABORT_LOAD_HOST_MSR = 4,
1559	/** VMX abort caused due to a machine-check exception during VM-exit. */
1560	VMXABORT_MACHINE_CHECK_XCPT = 5,
1561	/** VMX abort caused due to invalid return from long mode. */
1562	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1563	/* Type size hack. */
1564	VMXABORT_32BIT_HACK = 0x7fffffff
1565	} VMXABORT;
1566	AssertCompileSize(VMXABORT, 4);
1567	/** @} */
1568
1569
1570	/** @name VMX MSR - Basic VMX information.
1571	* @{
1572	*/
1573	/** VMCS (and related regions) memory type - Uncacheable. */
1574	#define VMX_BASIC_MEM_TYPE_UC 0
1575	/** VMCS (and related regions) memory type - Write back. */
1576	#define VMX_BASIC_MEM_TYPE_WB 6
1577	/** Width of physical addresses used for VMCS and associated memory regions
1578	* (1=32-bit, 0=processor's physical address width). */
1579	#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1580
1581	/** Bit fields for MSR_IA32_VMX_BASIC. */
1582	/** VMCS revision identifier used by the processor. */
1583	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1584	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1585	/** Bit 31 is reserved and RAZ. */
1586	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1587	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1588	/** VMCS size in bytes. */
1589	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1590	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1591	/** Bits 45:47 are reserved. */
1592	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1593	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1594	/** Width of physical addresses used for the VMCS and associated memory regions
1595	* (always 0 on CPUs that support Intel 64 architecture). */
1596	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1597	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1598	/** Dual-monitor treatment of SMI and SMM supported. */
1599	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1600	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1601	/** Memory type that must be used for the VMCS and associated memory regions. */
1602	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1603	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1604	/** VM-exit instruction information for INS/OUTS. */
1605	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1606	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1607	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1608	* bits in VMX control MSRs. */
1609	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1610	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1611	/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1612	#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1613	#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1614	/** Bits 57:63 are reserved and RAZ. */
1615	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1616	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1617	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1618	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1619	VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1620	/** @} */
1621
1622
1623	/** @name VMX MSR - Miscellaneous data.
1624	* @{
1625	*/
1626	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1627	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1628	/** Whether Intel PT is supported in VMX operation. */
1629	#define VMX_MISC_INTEL_PT RT_BIT(14)
1630	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1631	* VMWRITE cannot modify read-only VM-exit information fields. */
1632	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1633	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1634	* instructions. */
1635	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1636	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1637	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1638	/** Maximum CR3-target count supported by the CPU. */
1639	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1640
1641	/** Bit fields for MSR_IA32_VMX_MISC. */
1642	/** Relationship between the preemption timer and tsc. */
1643	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1644	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1645	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1646	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1647	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1648	/** Activity states supported by the implementation. */
1649	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1650	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1651	/** Bits 9:13 is reserved and RAZ. */
1652	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1653	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1654	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1655	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1656	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1657	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1658	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1659	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1660	/** Number of CR3 target values supported by the processor. (0-256) */
1661	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1662	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1663	/** Maximum number of MSRs in the VMCS. */
1664	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1665	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1666	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1667	* SMIs. */
1668	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1669	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1670	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1671	* VMWRITE cannot modify read-only VM-exit information fields. */
1672	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1673	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1674	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1675	* instructions. */
1676	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1677	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1678	/** Bit 31 is reserved and RAZ. */
1679	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1680	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1681	/** 32-bit MSEG revision ID used by the processor. */
1682	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1683	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1684	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1685	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1686	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1687	/** @} */
1688
1689	/** @name VMX MSR - VMCS enumeration.
1690	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1691	* @{
1692	*/
1693	/** Bit 0 is reserved and RAZ. */
1694	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1695	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1696	/** Highest index value used in VMCS field encoding. */
1697	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1698	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1699	/** Bit 10:63 is reserved and RAZ. */
1700	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1701	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1702	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1703	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1704	/** @} */
1705
1706
1707	/** @name VMX MSR - VM Functions.
1708	* Bit fields for MSR_IA32_VMX_VMFUNC.
1709	* @{
1710	*/
1711	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1712	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1713	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1714	/** Bits 1:63 are reserved and RAZ. */
1715	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1716	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1717	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1718	(EPTP_SWITCHING, RSVD_1_63));
1719	/** @} */
1720
1721
1722	/** @name VMX MSR - EPT/VPID capabilities.
1723	* @{
1724	*/
1725	/** Supports execute-only translations by EPT. */
1726	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1727	/** Supports page-walk length of 4. */
1728	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1729	/** Supports page-walk length of 5. */
1730	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1731	/** Supports EPT paging-structure memory type to be uncacheable. */
1732	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1733	/** Supports EPT paging structure memory type to be write-back. */
1734	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1735	/** Supports EPT PDE to map a 2 MB page. */
1736	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1737	/** Supports EPT PDPTE to map a 1 GB page. */
1738	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1739	/** Supports INVEPT instruction. */
1740	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1741	/** Supports accessed and dirty flags for EPT. */
1742	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1743	/** Supports advanced VM-exit info. for EPT violations. */
1744	#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT RT_BIT_64(22)
1745	/** Supports supervisor shadow-stack control. */
1746	#define MSR_IA32_VMX_EPT_VPID_CAP_SSS RT_BIT_64(23)
1747	/** Supports single-context INVEPT type. */
1748	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1749	/** Supports all-context INVEPT type. */
1750	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1751	/** Supports INVVPID instruction. */
1752	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1753	/** Supports individual-address INVVPID type. */
1754	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1755	/** Supports single-context INVVPID type. */
1756	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1757	/** Supports all-context INVVPID type. */
1758	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1759	/** Supports singe-context-retaining-globals INVVPID type. */
1760	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1761
1762	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1763	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_SHIFT 0
1764	#define VMX_BF_EPT_VPID_CAP_RWX_X_ONLY_MASK UINT64_C(0x0000000000000001)
1765	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1766	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1767	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1768	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1769	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1770	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1771	#define VMX_BF_EPT_VPID_CAP_EMT_UC_SHIFT 8
1772	#define VMX_BF_EPT_VPID_CAP_EMT_UC_MASK UINT64_C(0x0000000000000100)
1773	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1774	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1775	#define VMX_BF_EPT_VPID_CAP_EMT_WB_SHIFT 14
1776	#define VMX_BF_EPT_VPID_CAP_EMT_WB_MASK UINT64_C(0x0000000000004000)
1777	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1778	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1779	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1780	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1781	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1782	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1783	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1784	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1785	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1786	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1787	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_SHIFT 21
1788	#define VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1789	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_SHIFT 22
1790	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_MASK UINT64_C(0x0000000000400000)
1791	#define VMX_BF_EPT_VPID_CAP_SSS_SHIFT 23
1792	#define VMX_BF_EPT_VPID_CAP_SSS_MASK UINT64_C(0x0000000000800000)
1793	#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1794	#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1795	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1796	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1797	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1798	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1799	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1800	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1801	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1802	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1803	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1804	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1805	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1806	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1807	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1808	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1809	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1810	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1811	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1812	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1813	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1814	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1815	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1816	(RWX_X_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, EMT_UC, RSVD_9_13, EMT_WB, RSVD_15, PDE_2M,
1817	PDPTE_1G, RSVD_18_19, INVEPT, EPT_ACCESS_DIRTY, ADVEXITINFO_EPT, SSS, RSVD_24, INVEPT_SINGLE_CTX,
1818	INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR, INVVPID_SINGLE_CTX,
1819	INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1820	/** @} */
1821
1822
1823	/** @name Extended Page Table Pointer (EPTP)
1824	* @{
1825	*/
1826	/** Uncachable EPT paging structure memory type. */
1827	#define VMX_EPT_MEMTYPE_UC 0
1828	/** Write-back EPT paging structure memory type. */
1829	#define VMX_EPT_MEMTYPE_WB 6
1830	/** Shift value to get the EPT page walk length (bits 5-3) */
1831	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1832	/** Mask value to get the EPT page walk length (bits 5-3) */
1833	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1834	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1835	* length) */
1836	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1837	/** @} */
1838
1839
1840	/** @name VMCS fields and encoding.
1841	*
1842	* When adding a new field:
1843	* - Always add it to g_aVmcsFields.
1844	* - Consider if it needs to be added to VMXVVMCS.
1845	* @{
1846	*/
1847	/** 16-bit control fields. */
1848	#define VMX_VMCS16_VPID 0x0000
1849	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1850	#define VMX_VMCS16_EPTP_INDEX 0x0004
1851
1852	/** 16-bit guest-state fields. */
1853	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1854	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1855	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1856	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1857	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1858	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1859	#define VMX_VMCS16_GUEST_SEG_SEL(a_iSegReg) (VMX_VMCS16_GUEST_ES_SEL + (a_iSegReg) * 2)
1860	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1861	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1862	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1863	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1864
1865	/** 16-bits host-state fields. */
1866	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1867	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1868	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1869	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1870	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1871	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1872	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1873
1874	/** 64-bit control fields. */
1875	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1876	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1877	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1878	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1879	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1880	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1881	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1882	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1883	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1884	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1885	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1886	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1887	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1888	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1889	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1890	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1891	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1892	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1893	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1894	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1895	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1896	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1897	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1898	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1899	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1900	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1901	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1902	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1903	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1904	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1905	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1906	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1907	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1908	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1909	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1910	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1911	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1912	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1913	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1914	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1915	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1916	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1917	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1918	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1919	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1920	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1921	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1922	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1923	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1924	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1925
1926	/** 64-bit read-only data fields. */
1927	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1928	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1929
1930	/** 64-bit guest-state fields. */
1931	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1932	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1933	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1934	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1935	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1936	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1937	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1938	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1939	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1940	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1941	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1942	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1943	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1944	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1945	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1946	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1947	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1948	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1949	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1950	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1951
1952	/** 64-bit host-state fields. */
1953	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1954	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1955	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1956	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1957	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1958	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1959
1960	/** 32-bit control fields. */
1961	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1962	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1963	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1964	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1965	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1966	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1967	#define VMX_VMCS32_CTRL_EXIT 0x400c
1968	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1969	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1970	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1971	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1972	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1973	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1974	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1975	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1976	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1977	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1978	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1979
1980	/** 32-bits read-only fields. */
1981	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1982	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1983	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1984	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1985	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1986	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1987	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1988	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1989
1990	/** 32-bit guest-state fields. */
1991	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1992	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1993	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1994	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1995	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1996	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1997	#define VMX_VMCS32_GUEST_SEG_LIMIT(a_iSegReg) (VMX_VMCS32_GUEST_ES_LIMIT + (a_iSegReg) * 2)
1998	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1999	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
2000	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
2001	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
2002	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
2003	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
2004	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
2005	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
2006	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
2007	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
2008	#define VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(a_iSegReg) (VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS + (a_iSegReg) * 2)
2009	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
2010	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
2011	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
2012	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
2013	#define VMX_VMCS32_GUEST_SMBASE 0x4828
2014	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
2015	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
2016
2017	/** 32-bit host-state fields. */
2018	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
2019
2020	/** Natural-width control fields. */
2021	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
2022	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
2023	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
2024	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
2025	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
2026	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
2027	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
2028	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
2029
2030	/** Natural-width read-only data fields. */
2031	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
2032	#define VMX_VMCS_RO_IO_RCX 0x6402
2033	#define VMX_VMCS_RO_IO_RSI 0x6404
2034	#define VMX_VMCS_RO_IO_RDI 0x6406
2035	#define VMX_VMCS_RO_IO_RIP 0x6408
2036	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
2037
2038	/** Natural-width guest-state fields. */
2039	#define VMX_VMCS_GUEST_CR0 0x6800
2040	#define VMX_VMCS_GUEST_CR3 0x6802
2041	#define VMX_VMCS_GUEST_CR4 0x6804
2042	#define VMX_VMCS_GUEST_ES_BASE 0x6806
2043	#define VMX_VMCS_GUEST_CS_BASE 0x6808
2044	#define VMX_VMCS_GUEST_SS_BASE 0x680a
2045	#define VMX_VMCS_GUEST_DS_BASE 0x680c
2046	#define VMX_VMCS_GUEST_FS_BASE 0x680e
2047	#define VMX_VMCS_GUEST_GS_BASE 0x6810
2048	#define VMX_VMCS_GUEST_SEG_BASE(a_iSegReg) (VMX_VMCS_GUEST_ES_BASE + (a_iSegReg) * 2)
2049	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
2050	#define VMX_VMCS_GUEST_TR_BASE 0x6814
2051	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
2052	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
2053	#define VMX_VMCS_GUEST_DR7 0x681a
2054	#define VMX_VMCS_GUEST_RSP 0x681c
2055	#define VMX_VMCS_GUEST_RIP 0x681e
2056	#define VMX_VMCS_GUEST_RFLAGS 0x6820
2057	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
2058	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
2059	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
2060
2061	/** Natural-width host-state fields. */
2062	#define VMX_VMCS_HOST_CR0 0x6c00
2063	#define VMX_VMCS_HOST_CR3 0x6c02
2064	#define VMX_VMCS_HOST_CR4 0x6c04
2065	#define VMX_VMCS_HOST_FS_BASE 0x6c06
2066	#define VMX_VMCS_HOST_GS_BASE 0x6c08
2067	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
2068	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
2069	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
2070	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
2071	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
2072	#define VMX_VMCS_HOST_RSP 0x6c14
2073	#define VMX_VMCS_HOST_RIP 0x6c16
2074
2075	/**
2076	* VMCS field.
2077	* In accordance with the VT-x spec.
2078	*/
2079	typedef union
2080	{
2081	struct
2082	{
2083	/** The access type; 0=full, 1=high of 64-bit fields. */
2084	uint32_t fAccessType : 1;
2085	/** The index. */
2086	uint32_t u8Index : 8;
2087	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2088	uint32_t u2Type : 2;
2089	/** Reserved (MBZ). */
2090	uint32_t u1Reserved0 : 1;
2091	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2092	uint32_t u2Width : 2;
2093	/** Reserved (MBZ). */
2094	uint32_t u18Reserved0 : 18;
2095	} n;
2096
2097	/* The unsigned integer view. */
2098	uint32_t u;
2099	} VMXVMCSFIELD;
2100	AssertCompileSize(VMXVMCSFIELD, 4);
2101	/** Pointer to a VMCS field. */
2102	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
2103	/** Pointer to a const VMCS field. */
2104	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
2105
2106	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
2107	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
2108
2109	/** Bits fields for a VMCS field. */
2110	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
2111	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2112	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
2113	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
2114	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
2115	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
2116	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
2117	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
2118	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
2119	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
2120	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
2121	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
2122	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
2123	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2124
2125	/**
2126	* VMCS field encoding: Access type.
2127	* In accordance with the VT-x spec.
2128	*/
2129	typedef enum
2130	{
2131	VMXVMCSFIELDACCESS_FULL = 0,
2132	VMXVMCSFIELDACCESS_HIGH
2133	} VMXVMCSFIELDACCESS;
2134	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2135	/** VMCS field encoding type: Full. */
2136	#define VMX_VMCSFIELD_ACCESS_FULL 0
2137	/** VMCS field encoding type: High. */
2138	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2139
2140	/**
2141	* VMCS field encoding: Type.
2142	* In accordance with the VT-x spec.
2143	*/
2144	typedef enum
2145	{
2146	VMXVMCSFIELDTYPE_CONTROL = 0,
2147	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2148	VMXVMCSFIELDTYPE_GUEST_STATE,
2149	VMXVMCSFIELDTYPE_HOST_STATE
2150	} VMXVMCSFIELDTYPE;
2151	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2152	/** VMCS field encoding type: Control. */
2153	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2154	/** VMCS field encoding type: VM-exit information / read-only fields. */
2155	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2156	/** VMCS field encoding type: Guest-state. */
2157	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2158	/** VMCS field encoding type: Host-state. */
2159	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2160
2161	/**
2162	* VMCS field encoding: Width.
2163	* In accordance with the VT-x spec.
2164	*/
2165	typedef enum
2166	{
2167	VMXVMCSFIELDWIDTH_16BIT = 0,
2168	VMXVMCSFIELDWIDTH_64BIT,
2169	VMXVMCSFIELDWIDTH_32BIT,
2170	VMXVMCSFIELDWIDTH_NATURAL
2171	} VMXVMCSFIELDWIDTH;
2172	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2173	/** VMCS field encoding width: 16-bit. */
2174	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2175	/** VMCS field encoding width: 64-bit. */
2176	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2177	/** VMCS field encoding width: 32-bit. */
2178	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2179	/** VMCS field encoding width: Natural width. */
2180	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2181	/** @} */
2182
2183
2184	/** @name VM-entry instruction length.
2185	* @{ */
2186	/** The maximum valid value for VM-entry instruction length while injecting a
2187	* software interrupt, software exception or privileged software exception. */
2188	#define VMX_ENTRY_INSTR_LEN_MAX 15
2189	/** @} */
2190
2191
2192	/** @name VM-entry register masks.
2193	* @{ */
2194	/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2195	* bit 17 and bits 19:28). */
2196	#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2197	/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2198	* 12, bits 14:15). */
2199	#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2200	/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2201	* 10). */
2202	#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2203	/** @} */
2204
2205
2206	/** @name VM-exit register masks.
2207	* @{ */
2208	/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2209	* bit 17, bits 19:28 and bits 32:63). */
2210	#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2211	/** @} */
2212
2213
2214	/** @name Pin-based VM-execution controls.
2215	* @{
2216	*/
2217	/** External interrupt exiting. */
2218	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2219	/** NMI exiting. */
2220	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2221	/** Virtual NMIs. */
2222	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2223	/** Activate VMX preemption timer. */
2224	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2225	/** Process interrupts with the posted-interrupt notification vector. */
2226	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2227	/** Default1 class when true capability MSRs are not supported. */
2228	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2229
2230	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2231	* controls field in the VMCS. */
2232	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2233	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2234	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
2235	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
2236	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2237	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2238	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
2239	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
2240	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2241	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2242	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2243	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2244	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2245	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2246	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
2247	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
2248	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2249	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
2250	/** @} */
2251
2252
2253	/** @name Processor-based VM-execution controls.
2254	* @{
2255	*/
2256	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2257	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2258	/** Use timestamp counter offset. */
2259	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2260	/** VM-exit when executing the HLT instruction. */
2261	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2262	/** VM-exit when executing the INVLPG instruction. */
2263	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2264	/** VM-exit when executing the MWAIT instruction. */
2265	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2266	/** VM-exit when executing the RDPMC instruction. */
2267	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2268	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2269	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2270	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2271	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2272	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2273	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2274	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2275	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2276	/** VM-exit on CR8 loads. */
2277	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2278	/** VM-exit on CR8 stores. */
2279	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2280	/** Use TPR shadow. */
2281	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2282	/** VM-exit when virtual NMI blocking is disabled. */
2283	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2284	/** VM-exit when executing a MOV DRx instruction. */
2285	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2286	/** VM-exit when executing IO instructions. */
2287	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2288	/** Use IO bitmaps. */
2289	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2290	/** Monitor trap flag. */
2291	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2292	/** Use MSR bitmaps. */
2293	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2294	/** VM-exit when executing the MONITOR instruction. */
2295	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2296	/** VM-exit when executing the PAUSE instruction. */
2297	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2298	/** Whether the secondary processor based VM-execution controls are used. */
2299	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2300	/** Default1 class when true-capability MSRs are not supported. */
2301	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2302
2303	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2304	* controls field in the VMCS. */
2305	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
2306	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2307	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2308	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2309	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2310	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2311	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
2312	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
2313	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2314	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2315	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
2316	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
2317	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2318	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2319	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2320	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2321	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2322	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2323	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2324	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2325	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2326	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2327	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2328	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2329	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2330	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2331	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2332	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2333	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2334	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2335	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2336	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2337	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2338	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2339	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2340	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2341	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2342	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2343	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2344	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2345	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2346	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2347	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2348	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2349	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2350	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2351	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2352	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2353	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2354	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2355	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2356	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2357	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2358	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2359	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2360	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2361	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2362	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2363	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2364	USE_SECONDARY_CTLS));
2365	/** @} */
2366
2367
2368	/** @name Secondary Processor-based VM-execution controls.
2369	* @{
2370	*/
2371	/** Virtualize APIC accesses. */
2372	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2373	/** EPT supported/enabled. */
2374	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2375	/** Descriptor table instructions cause VM-exits. */
2376	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2377	/** RDTSCP supported/enabled. */
2378	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2379	/** Virtualize x2APIC mode. */
2380	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2381	/** VPID supported/enabled. */
2382	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2383	/** VM-exit when executing the WBINVD instruction. */
2384	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2385	/** Unrestricted guest execution. */
2386	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2387	/** APIC register virtualization. */
2388	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2389	/** Virtual-interrupt delivery. */
2390	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2391	/** A specified number of pause loops cause a VM-exit. */
2392	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2393	/** VM-exit when executing RDRAND instructions. */
2394	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2395	/** Enables INVPCID instructions. */
2396	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2397	/** Enables VMFUNC instructions. */
2398	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2399	/** Enables VMCS shadowing. */
2400	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2401	/** Enables ENCLS VM-exits. */
2402	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2403	/** VM-exit when executing RDSEED. */
2404	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2405	/** Enables page-modification logging. */
2406	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2407	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2408	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2409	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2410	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2411	/** Enables XSAVES/XRSTORS instructions. */
2412	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2413	/** Enables supervisor/user mode based EPT execute permission for linear
2414	* addresses. */
2415	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2416	/** Enables EPT permissions to be specified at granularity of 128 bytes. */
2417	#define VMX_PROC_CTLS2_SPPTP_EPT RT_BIT(23)
2418	/** Intel PT output addresses are treated as guest-physical addresses and
2419	* translated using EPT. */
2420	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2421	/** Use TSC scaling. */
2422	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2423	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2424	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2425	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2426	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2427
2428	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2429	* VM-execution controls field in the VMCS. */
2430	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2431	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2432	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2433	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2434	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2435	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2436	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2437	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2438	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2439	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2440	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2441	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2442	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2443	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2444	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2445	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2446	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2447	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2448	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2449	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2450	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2451	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2452	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2453	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2454	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2455	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2456	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2457	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2458	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2459	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2460	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2461	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2462	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2463	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2464	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2465	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2466	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2467	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2468	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2469	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2470	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2471	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2472	#define VMX_BF_PROC_CTLS2_UNDEF_21_SHIFT 21
2473	#define VMX_BF_PROC_CTLS2_UNDEF_21_MASK UINT32_C(0x00200000)
2474	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2475	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2476	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_SHIFT 23
2477	#define VMX_BF_PROC_CTLS2_SPPTP_EPT_MASK UINT32_C(0x00800000)
2478	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2479	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2480	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2481	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2482	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2483	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2484	#define VMX_BF_PROC_CTLS2_UNDEF_27_SHIFT 27
2485	#define VMX_BF_PROC_CTLS2_UNDEF_27_MASK UINT32_C(0x08000000)
2486	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2487	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2488	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_SHIFT 29
2489	#define VMX_BF_PROC_CTLS2_UNDEF_29_31_MASK UINT32_C(0xe0000000)
2490
2491	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2492	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2493	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2494	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, UNDEF_21,
2495	MODE_BASED_EPT_PERM, SPPTP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, UNDEF_27, ENCLV_EXIT,
2496	UNDEF_29_31));
2497	/** @} */
2498
2499
2500	/** @name VM-entry controls.
2501	* @{
2502	*/
2503	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2504	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2505	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2506	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2507	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2508	/** In SMM mode after VM-entry. */
2509	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2510	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2511	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2512	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2513	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2514	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2515	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2516	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2517	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2518	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2519	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2520	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2521	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2522	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2523	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2524	/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2525	#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2526	/** Default1 class when true-capability MSRs are not supported. */
2527	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2528
2529	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2530	* VMCS. */
2531	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2532	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2533	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2534	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2535	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2536	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2537	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2538	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2539	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2540	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2541	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2542	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2543	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2544	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2545	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2546	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2547	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2548	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2549	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2550	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2551	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2552	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2553	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2554	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2555	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2556	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2557	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_SHIFT 19
2558	#define VMX_BF_ENTRY_CTLS_UNDEF_19_31_MASK UINT32_C(0xfff80000)
2559	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2560	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2561	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2562	LOAD_RTIT_CTL_MSR, UNDEF_19_31));
2563	/** @} */
2564
2565
2566	/** @name VM-exit controls.
2567	* @{
2568	*/
2569	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2570	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2571	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2572	/** Return to long mode after a VM-exit. */
2573	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2574	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2575	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2576	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2577	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2578	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2579	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2580	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2581	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2582	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2583	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2584	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2585	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2586	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2587	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2588	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2589	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2590	/** Whether to conceal VMX from Intel PT. */
2591	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2592	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2593	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2594	/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2595	#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2596	/** Default1 class when true-capability MSRs are not supported. */
2597	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2598
2599	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2600	* VMCS. */
2601	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2602	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2603	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2604	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2605	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2606	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2607	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2608	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2609	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2610	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2611	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2612	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2613	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2614	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2615	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2616	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2617	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2618	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2619	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2620	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2621	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2622	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2623	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2624	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2625	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2626	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2627	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2628	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2629	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2630	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2631	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2632	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2633	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2634	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2635	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_SHIFT 26
2636	#define VMX_BF_EXIT_CTLS_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2637	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2638	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2639	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2640	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, UNDEF_26_31));
2641	/** @} */
2642
2643
2644	/** @name VM-exit reason.
2645	* @{
2646	*/
2647	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2648	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2649	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2650
2651	/** Bit fields for VM-exit reason. */
2652	/** The exit reason. */
2653	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2654	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2655	/** Bits 16:26 are reseved and MBZ. */
2656	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2657	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2658	/** Whether the VM-exit was incident to enclave mode. */
2659	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2660	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2661	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2662	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2663	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2664	/** VM-exit from VMX root operation (only possible with SMM). */
2665	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2666	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2667	/** Bit 30 is reserved and MBZ. */
2668	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2669	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2670	/** Whether VM-entry failed (currently only happens during loading guest-state
2671	* or MSRs or machine check exceptions). */
2672	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2673	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2674	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2675	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2676	/** @} */
2677
2678
2679	/** @name VM-entry interruption information.
2680	* @{
2681	*/
2682	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2683	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2684	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2685	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2686	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2687	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2688	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2689	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2690	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2691	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2692	/** Construct an VM-entry interruption information field from a VM-exit interruption
2693	* info value (same except that bit 12 is reserved). */
2694	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2695	/** Construct a VM-entry interruption information field from an IDT-vectoring
2696	* information field (same except that bit 12 is reserved). */
2697	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2698	/** If the VM-entry interruption information field indicates a page-fault. */
2699	#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2700	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2701	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2702	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2703	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2704	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2705	/** If the VM-entry interruption information field indicates an external
2706	* interrupt. */
2707	#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2708	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2709	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2710	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2711	/** If the VM-entry interruption information field indicates an NMI. */
2712	#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2713	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2714	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2715	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2716	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2717	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2718
2719	/** Bit fields for VM-entry interruption information. */
2720	/** The VM-entry interruption vector. */
2721	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2722	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2723	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2724	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2725	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2726	/** Whether this event has an error code. */
2727	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2728	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2729	/** Bits 12:30 are reserved and MBZ. */
2730	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2731	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2732	/** Whether this VM-entry interruption info is valid. */
2733	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2734	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2735	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2736	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2737	/** @} */
2738
2739
2740	/** @name VM-entry exception error code.
2741	* @{ */
2742	/** Error code valid mask. */
2743	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2744	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2745	* stack aligned for doubleword pushes, the upper half of the error code is
2746	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2747	* use below. */
2748	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2749	/** @} */
2750
2751	/** @name VM-entry interruption information types.
2752	* @{
2753	*/
2754	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2755	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2756	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2757	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2758	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2759	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2760	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2761	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2762	/** @} */
2763
2764
2765	/** @name VM-entry interruption information vector types for
2766	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2767	* @{ */
2768	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2769	/** @} */
2770
2771
2772	/** @name VM-exit interruption information.
2773	* @{
2774	*/
2775	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2776	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2777	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2778	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2779	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2780	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2781	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2782	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2783	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2784
2785	/** If the VM-exit interruption information field indicates an page-fault. */
2786	#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2787	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2788	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2789	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2790	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2791	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
2792	/** If the VM-exit interruption information field indicates an double-fault. */
2793	#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2794	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2795	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2796	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2797	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2798	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
2799	/** If the VM-exit interruption information field indicates an NMI. */
2800	#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2801	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2802	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2803	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2804	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
2805	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
2806
2807
2808	/** Bit fields for VM-exit interruption infomration. */
2809	/** The VM-exit interruption vector. */
2810	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2811	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2812	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2813	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2814	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2815	/** Whether this event has an error code. */
2816	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2817	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2818	/** Whether NMI-unblocking due to IRET is active. */
2819	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2820	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2821	/** Bits 13:30 is reserved (MBZ). */
2822	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2823	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2824	/** Whether this VM-exit interruption info is valid. */
2825	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2826	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2827	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2828	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2829	/** @} */
2830
2831
2832	/** @name VM-exit interruption information types.
2833	* @{
2834	*/
2835	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2836	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2837	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2838	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2839	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2840	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2841	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2842	/** @} */
2843
2844
2845	/** @name VM-exit instruction identity.
2846	*
2847	* These are found in VM-exit instruction information fields for certain
2848	* instructions.
2849	* @{ */
2850	typedef uint32_t VMXINSTRID;
2851	/** Whether the instruction ID field is valid. */
2852	#define VMXINSTRID_VALID RT_BIT_32(31)
2853	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2854	* read or write. */
2855	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2856	/** Gets whether the instruction ID is valid or not. */
2857	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2858	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2859	/** Gets the instruction ID. */
2860	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2861	/** No instruction ID info. */
2862	#define VMXINSTRID_NONE 0
2863
2864	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2865	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2866	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2867	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2868	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2869
2870	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2871	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2872	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2873	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2874
2875	/** The following IDs are used internally (some for logging, others for conveying
2876	* the ModR/M primary operand write bit): */
2877	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2878	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2879	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2880	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2881	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2882	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2883	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2884	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2885	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2886	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2887	/** @} */
2888
2889
2890	/** @name IDT-vectoring information.
2891	* @{
2892	*/
2893	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2894	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
2895	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2896	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
2897	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2898	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2899	#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
2900
2901	/** Construct an IDT-vectoring information field from an VM-entry interruption
2902	* information field (same except that bit 12 is reserved). */
2903	#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2904	/** If the IDT-vectoring information field indicates a page-fault. */
2905	#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2906	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2907	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2908	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2909	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
2910	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
2911	/** If the IDT-vectoring information field indicates an NMI. */
2912	#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
2913	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
2914	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
2915	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
2916	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
2917	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
2918
2919
2920	/** Bit fields for IDT-vectoring information. */
2921	/** The IDT-vectoring info vector. */
2922	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2923	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2924	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2925	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2926	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2927	/** Whether the event has an error code. */
2928	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2929	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2930	/** Bit 12 is undefined. */
2931	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2932	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2933	/** Bits 13:30 is reserved (MBZ). */
2934	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2935	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2936	/** Whether this IDT-vectoring info is valid. */
2937	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2938	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2939	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2940	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2941	/** @} */
2942
2943
2944	/** @name IDT-vectoring information vector types.
2945	* @{
2946	*/
2947	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2948	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2949	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2950	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2951	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2952	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2953	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2954	/** @} */
2955
2956
2957	/** @name TPR threshold.
2958	* @{ */
2959	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2960	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2961
2962	/** Bit fields for TPR threshold. */
2963	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2964	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2965	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2966	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2967	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2968	(TPR, RSVD_4_31));
2969	/** @} */
2970
2971
2972	/** @name Guest-activity states.
2973	* @{
2974	*/
2975	/** The logical processor is active. */
2976	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2977	/** The logical processor is inactive, because it executed a HLT instruction. */
2978	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2979	/** The logical processor is inactive, because of a triple fault or other serious error. */
2980	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2981	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2982	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2983	/** @} */
2984
2985
2986	/** @name Guest-interruptibility states.
2987	* @{
2988	*/
2989	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2990	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2991	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2992	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2993	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2994
2995	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2996	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2997	/** @} */
2998
2999
3000	/** @name Exit qualification for debug exceptions.
3001	* @{
3002	*/
3003	/** Hardware breakpoint 0 was met. */
3004	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
3005	/** Hardware breakpoint 1 was met. */
3006	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
3007	/** Hardware breakpoint 2 was met. */
3008	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
3009	/** Hardware breakpoint 3 was met. */
3010	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
3011	/** Debug register access detected. */
3012	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
3013	/** A debug exception would have been triggered by single-step execution mode. */
3014	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
3015	/** Mask of all valid bits. */
3016	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
3017	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
3018	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
3019	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
3020	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
3021	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
3022
3023	/** Bit fields for Exit qualifications due to debug exceptions. */
3024	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
3025	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3026	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
3027	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3028	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
3029	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3030	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
3031	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3032	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
3033	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
3034	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
3035	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
3036	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
3037	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3038	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
3039	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
3040	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
3041	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
3042	/** @} */
3043
3044	/** @name Exit qualification for Mov DRx.
3045	* @{
3046	*/
3047	/** 0-2: Debug register number */
3048	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
3049	/** 3: Reserved; cleared to 0. */
3050	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
3051	/** 4: Direction of move (0 = write, 1 = read) */
3052	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
3053	/** 5-7: Reserved; cleared to 0. */
3054	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
3055	/** 8-11: General purpose register number. */
3056	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
3057
3058	/** Bit fields for Exit qualification due to Mov DRx. */
3059	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
3060	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
3061	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
3062	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
3063	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
3064	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
3065	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
3066	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
3067	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
3068	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3069	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
3070	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
3071	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
3072	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
3073	/** @} */
3074
3075
3076	/** @name Exit qualification for debug exceptions types.
3077	* @{
3078	*/
3079	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
3080	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
3081	/** @} */
3082
3083
3084	/** @name Exit qualification for control-register accesses.
3085	* @{
3086	*/
3087	/** 0-3: Control register number (0 for CLTS & LMSW) */
3088	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
3089	/** 4-5: Access type. */
3090	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
3091	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
3092	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
3093	/** 7: Reserved; cleared to 0. */
3094	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
3095	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
3096	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
3097	/** 12-15: Reserved; cleared to 0. */
3098	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
3099	/** 16-31: LMSW source data (else 0). */
3100	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
3101
3102	/** Bit fields for Exit qualification for control-register accesses. */
3103	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
3104	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
3105	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
3106	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
3107	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
3108	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
3109	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
3110	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
3111	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
3112	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3113	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
3114	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
3115	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
3116	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
3117	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
3118	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3119	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
3120	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
3121	/** @} */
3122
3123
3124	/** @name Exit qualification for control-register access types.
3125	* @{
3126	*/
3127	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3128	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3129	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3130	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3131	/** @} */
3132
3133
3134	/** @name Exit qualification for task switch.
3135	* @{
3136	*/
3137	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3138	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3139	/** Task switch caused by a call instruction. */
3140	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3141	/** Task switch caused by an iret instruction. */
3142	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3143	/** Task switch caused by a jmp instruction. */
3144	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3145	/** Task switch caused by an interrupt gate. */
3146	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3147
3148	/** Bit fields for Exit qualification for task switches. */
3149	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3150	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3151	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3152	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3153	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3154	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3155	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3156	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3157	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3158	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3159	/** @} */
3160
3161
3162	/** @name Exit qualification for EPT violations.
3163	* @{
3164	*/
3165	/** Set if the violation was caused by a data read. */
3166	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
3167	/** Set if the violation was caused by a data write. */
3168	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
3169	/** Set if the violation was caused by an instruction fetch. */
3170	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
3171	/** AND of the present bit of all EPT structures. */
3172	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
3173	/** AND of the write bit of all EPT structures. */
3174	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
3175	/** AND of the execute bit of all EPT structures. */
3176	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
3177	/** Set if the guest linear address field contains the faulting address. */
3178	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
3179	/** If bit 7 is one: (reserved otherwise)
3180	* 1 - violation due to physical address access.
3181	* 0 - violation caused by page walk or access/dirty bit updates
3182	*/
3183	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
3184	/** NMI unblocking due to IRET. */
3185	#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3186	/** @} */
3187
3188
3189	/** @name Exit qualification for I/O instructions.
3190	* @{
3191	*/
3192	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3193	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3194	/** 3: IO operation direction. */
3195	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3196	/** 4: String IO operation (INS / OUTS). */
3197	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3198	/** 5: Repeated IO operation. */
3199	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3200	/** 6: Operand encoding. */
3201	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3202	/** 16-31: IO Port (0-0xffff). */
3203	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3204
3205	/** Bit fields for Exit qualification for I/O instructions. */
3206	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3207	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3208	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3209	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3210	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3211	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3212	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3213	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3214	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3215	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3216	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3217	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3218	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3219	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3220	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3221	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3222	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3223	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3224	/** @} */
3225
3226
3227	/** @name Exit qualification for I/O instruction types.
3228	* @{
3229	*/
3230	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3231	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3232	/** @} */
3233
3234
3235	/** @name Exit qualification for I/O instruction encoding.
3236	* @{
3237	*/
3238	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3239	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3240	/** @} */
3241
3242
3243	/** @name Exit qualification for APIC-access VM-exits from linear and
3244	* guest-physical accesses.
3245	* @{
3246	*/
3247	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3248	* access within the APIC page. */
3249	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3250	/** 12-15: Access type. */
3251	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3252	/* Rest reserved. */
3253
3254	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3255	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3256	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3257	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3258	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3259	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3260	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3261	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3262	(OFFSET, TYPE, RSVD_16_63));
3263	/** @} */
3264
3265
3266	/** @name Exit qualification for linear address APIC-access types.
3267	* @{
3268	*/
3269	/** Linear access for a data read during instruction execution. */
3270	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3271	/** Linear access for a data write during instruction execution. */
3272	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3273	/** Linear access for an instruction fetch. */
3274	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3275	/** Linear read/write access during event delivery. */
3276	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3277	/** Physical read/write access during event delivery. */
3278	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3279	/** Physical access for an instruction fetch or during instruction execution. */
3280	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3281
3282	/**
3283	* APIC-access type.
3284	* In accordance with the VT-x spec.
3285	*/
3286	typedef enum
3287	{
3288	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3289	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3290	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3291	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3292	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3293	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3294	} VMXAPICACCESS;
3295	AssertCompileSize(VMXAPICACCESS, 4);
3296	/** @} */
3297
3298
3299	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3300	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3301	* @{
3302	*/
3303	/** Address calculation scaling field (powers of two). */
3304	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3305	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3306	/** Bits 2 thru 6 are undefined. */
3307	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3308	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3309	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3310	* @remarks anyone's guess why this is a 3 bit field... */
3311	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3312	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3313	/** Bit 10 is defined as zero. */
3314	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3315	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3316	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3317	* for exits from 64-bit code as the operand size there is fixed. */
3318	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3319	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3320	/** Bits 12 thru 14 are undefined. */
3321	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3322	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3323	/** Applicable segment register (X86_SREG_XXX values). */
3324	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3325	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3326	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3327	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3328	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3329	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3330	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3331	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3332	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3333	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3334	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3335	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3336	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3337	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3338	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3339	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3340	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3341	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3342	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3343	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3344	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3345	/** Bits 30 & 31 are undefined. */
3346	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3347	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3348	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3349	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3350	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3351	/** @} */
3352
3353
3354	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3355	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3356	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3357	* @{
3358	*/
3359	/** Address calculation scaling field (powers of two). */
3360	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3361	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3362	/** Bit 2 is undefined. */
3363	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3364	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3365	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3366	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3367	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3368	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3369	* @remarks anyone's guess why this is a 3 bit field... */
3370	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3371	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3372	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3373	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3374	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3375	/** Bits 11 thru 14 are undefined. */
3376	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3377	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3378	/** Applicable segment register (X86_SREG_XXX values). */
3379	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3380	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3381	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3382	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3383	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3384	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3385	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3386	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3387	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3388	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3389	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3390	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3391	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3392	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3393	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3394	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3395	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3396	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3397	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3398	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3399	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3400	/** Bits 30 & 31 are undefined. */
3401	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3402	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3403	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3404	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3405	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3406	/** @} */
3407
3408
3409	/** @name Format of Pending-Debug-Exceptions.
3410	* Bits 4-11, 13, 15 and 17-63 are reserved.
3411	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3412	* possibly valid here but not in DR6.
3413	* @{
3414	*/
3415	/** Hardware breakpoint 0 was met. */
3416	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3417	/** Hardware breakpoint 1 was met. */
3418	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3419	/** Hardware breakpoint 2 was met. */
3420	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3421	/** Hardware breakpoint 3 was met. */
3422	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3423	/** At least one data or IO breakpoint was hit. */
3424	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3425	/** A debug exception would have been triggered by single-step execution mode. */
3426	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3427	/** A debug exception occurred inside an RTM region. */
3428	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3429	/** Mask of valid bits. */
3430	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3431	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3432	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3433	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3434	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3435	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3436	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3437	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3438	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3439	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3440	/** Bit fields for Pending debug exceptions. */
3441	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3442	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3443	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3444	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3445	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3446	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3447	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3448	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3449	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3450	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3451	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3452	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3453	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3454	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3455	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3456	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3457	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3458	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3459	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3460	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3461	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3462	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3463	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3464	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3465	/** @} */
3466
3467
3468	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3469	* @{
3470	*/
3471
3472	/** @name Virtual VMX MSR - Miscellaneous data.
3473	* @{ */
3474	/** Number of CR3-target values supported. */
3475	#define VMX_V_CR3_TARGET_COUNT 4
3476	/** Activity states supported. */
3477	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3478	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3479	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3480	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3481	#define VMX_V_AUTOMSR_COUNT_MAX 0
3482	/** SMM MSEG revision ID. */
3483	#define VMX_V_MSEG_REV_ID 0
3484	/** @} */
3485
3486	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3487	* @{ */
3488	/** VMCS launch state clear. */
3489	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3490	/** VMCS launch state active. */
3491	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3492	/** VMCS launch state current. */
3493	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3494	/** VMCS launch state launched. */
3495	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3496	/** The mask of valid VMCS launch states. */
3497	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3498	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3499	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3500	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3501	/** @} */
3502
3503	/** CR0 bits set here must always be set when in VMX operation. */
3504	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3505	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3506	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3507	/** CR4 bits set here must always be set when in VMX operation. */
3508	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3509
3510	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3511	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3512	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3513	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3514
3515	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3516	* complications when teleporation may be implemented). */
3517	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3518	/** The size of the virtual VMCS region (in pages). */
3519	#define VMX_V_VMCS_PAGES 1
3520
3521	/** The size of the virtual shadow VMCS region. */
3522	#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3523	/** The size of the virtual shadow VMCS region (in pages). */
3524	#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3525
3526	/** The size of the Virtual-APIC page (in bytes). */
3527	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3528	/** The size of the Virtual-APIC page (in pages). */
3529	#define VMX_V_VIRT_APIC_PAGES 1
3530
3531	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3532	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3533	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3534	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3535
3536	/** The size of the MSR bitmap (in bytes). */
3537	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3538	/** The size of the MSR bitmap (in pages). */
3539	#define VMX_V_MSR_BITMAP_PAGES 1
3540
3541	/** The size of I/O bitmap A (in bytes). */
3542	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3543	/** The size of I/O bitmap A (in pages). */
3544	#define VMX_V_IO_BITMAP_A_PAGES 1
3545
3546	/** The size of I/O bitmap B (in bytes). */
3547	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3548	/** The size of I/O bitmap B (in pages). */
3549	#define VMX_V_IO_BITMAP_B_PAGES 1
3550
3551	/** The size of the auto-load/store MSR area (in bytes). */
3552	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3553	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3554	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3555	/** The size of the auto-load/store MSR area (in pages). */
3556	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3557
3558	/** The highest index value used for supported virtual VMCS field encoding. */
3559	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCSFIELD_INDEX)
3560
3561	/**
3562	* Virtual VM-exit information.
3563	*
3564	* This is a convenience structure that bundles some VM-exit information related
3565	* fields together.
3566	*/
3567	typedef struct
3568	{
3569	/** The VM-exit reason. */
3570	uint32_t uReason;
3571	/** The VM-exit instruction length. */
3572	uint32_t cbInstr;
3573	/** The VM-exit instruction information. */
3574	VMXEXITINSTRINFO InstrInfo;
3575	/** The VM-exit instruction ID. */
3576	VMXINSTRID uInstrId;
3577
3578	/** The Exit qualification field. */
3579	uint64_t u64Qual;
3580	/** The Guest-linear address field. */
3581	uint64_t u64GuestLinearAddr;
3582	/** The Guest-physical address field. */
3583	uint64_t u64GuestPhysAddr;
3584	/** The guest pending-debug exceptions. */
3585	uint64_t u64GuestPendingDbgXcpts;
3586	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3587	* instruction VM-exit. */
3588	RTGCPTR GCPtrEffAddr;
3589	} VMXVEXITINFO;
3590	/** Pointer to the VMXVEXITINFO struct. */
3591	typedef VMXVEXITINFO *PVMXVEXITINFO;
3592	/** Pointer to a const VMXVEXITINFO struct. */
3593	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3594	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3595
3596	/**
3597	* Virtual VM-exit information for events.
3598	*
3599	* This is a convenience structure that bundles some event-based VM-exit information
3600	* related fields together that are not included in VMXVEXITINFO.
3601	*
3602	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3603	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3604	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3605	* make it ovbious which fields may get set (or cleared).
3606	*/
3607	typedef struct
3608	{
3609	/** VM-exit interruption information. */
3610	uint32_t uExitIntInfo;
3611	/** VM-exit interruption error code. */
3612	uint32_t uExitIntErrCode;
3613	/** IDT-vectoring information. */
3614	uint32_t uIdtVectoringInfo;
3615	/** IDT-vectoring error code. */
3616	uint32_t uIdtVectoringErrCode;
3617	} VMXVEXITEVENTINFO;
3618	/** Pointer to the VMXVEXITINFO2 struct. */
3619	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3620	/** Pointer to a const VMXVEXITINFO2 struct. */
3621	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3622
3623	/**
3624	* Virtual VMCS.
3625	*
3626	* This is our custom format. Relevant fields from this VMCS will be merged into the
3627	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3628	* VMX.
3629	*
3630	* The first 8 bytes must be in accordance with the Intel VT-x spec.
3631	* See Intel spec. 24.2 "Format of the VMCS Region".
3632	*
3633	* The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
3634	* the Intel spec. but for our own requirements) as we use it to offset into guest
3635	* memory.
3636	*
3637	* Although the guest is supposed to access the VMCS only through the execution of
3638	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3639	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3640	* for teleportation purposes, any newly added fields should be added to the
3641	* appropriate reserved sections or at the end of the structure.
3642	*
3643	* We always treat natural-width fields as 64-bit in our implementation since
3644	* it's easier, allows for teleporation in the future and does not affect guest
3645	* software.
3646	*
3647	* Note! Any fields that are added or modified here, make sure to update the
3648	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3649	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3650	* Also consider updating CPUMIsGuestVmxVmcsFieldValid.
3651	*/
3652	#pragma pack(1)
3653	typedef struct
3654	{
3655	/** @name Header.
3656	* @{
3657	*/
3658	VMXVMCSREVID u32VmcsRevId; /*< 0x000 - VMX VMCS revision identifier. /
3659	VMXABORT enmVmxAbort; /*< 0x004 - VMX-abort indicator. /
3660	uint8_t fVmcsState; /*< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. /
3661	uint8_t au8Padding0[3]; /*< 0x009 - Reserved for future. /
3662	uint32_t au32Reserved0[12]; /*< 0x00c - Reserved for future. /
3663	/** @} */
3664
3665	/** @name Read-only fields.
3666	* @{ */
3667	/** 16-bit fields. */
3668	uint16_t u16Reserved0[14]; /*< 0x03c - Reserved for future. /
3669
3670	/** 32-bit fields. */
3671	uint32_t u32RoVmInstrError; /*< 0x058 - VM-instruction error. /
3672	uint32_t u32RoExitReason; /*< 0x05c - VM-exit reason. /
3673	uint32_t u32RoExitIntInfo; /*< 0x060 - VM-exit interruption information. /
3674	uint32_t u32RoExitIntErrCode; /*< 0x064 - VM-exit interruption error code. /
3675	uint32_t u32RoIdtVectoringInfo; /*< 0x068 - IDT-vectoring information. /
3676	uint32_t u32RoIdtVectoringErrCode; /*< 0x06c - IDT-vectoring error code. /
3677	uint32_t u32RoExitInstrLen; /*< 0x070 - VM-exit instruction length. /
3678	uint32_t u32RoExitInstrInfo; /*< 0x074 - VM-exit instruction information. /
3679	uint32_t au32RoReserved2[16]; /*< 0x078 - Reserved for future. /
3680
3681	/** 64-bit fields. */
3682	RTUINT64U u64RoGuestPhysAddr; /*< 0x0b8 - Guest-physical address. /
3683	RTUINT64U au64Reserved1[8]; /*< 0x0c0 - Reserved for future. /
3684
3685	/** Natural-width fields. */
3686	RTUINT64U u64RoExitQual; /*< 0x100 - Exit qualification. /
3687	RTUINT64U u64RoIoRcx; /*< 0x108 - I/O RCX. /
3688	RTUINT64U u64RoIoRsi; /*< 0x110 - I/O RSI. /
3689	RTUINT64U u64RoIoRdi; /*< 0x118 - I/O RDI. /
3690	RTUINT64U u64RoIoRip; /*< 0x120 - I/O RIP. /
3691	RTUINT64U u64RoGuestLinearAddr; /*< 0x128 - Guest-linear address. /
3692	RTUINT64U au64Reserved5[16]; /*< 0x130 - Reserved for future. /
3693	/** @} */
3694
3695	/** @name Control fields.
3696	* @{ */
3697	/** 16-bit fields. */
3698	uint16_t u16Vpid; /*< 0x1b0 - Virtual processor ID. /
3699	uint16_t u16PostIntNotifyVector; /*< 0x1b2 - Posted interrupt notify vector. /
3700	uint16_t u16EptpIndex; /*< 0x1b4 - EPTP index. /
3701	uint16_t au16Reserved0[13]; /*< 0x1b6 - Reserved for future. /
3702
3703	/** 32-bit fields. */
3704	uint32_t u32PinCtls; /*< 0x1d0 - Pin-based VM-execution controls. /
3705	uint32_t u32ProcCtls; /*< 0x1d4 - Processor-based VM-execution controls. /
3706	uint32_t u32XcptBitmap; /*< 0x1d8 - Exception bitmap. /
3707	uint32_t u32XcptPFMask; /*< 0x1dc - Page-fault exception error mask. /
3708	uint32_t u32XcptPFMatch; /*< 0x1e0 - Page-fault exception error match. /
3709	uint32_t u32Cr3TargetCount; /*< 0x1e4 - CR3-target count. /
3710	uint32_t u32ExitCtls; /*< 0x1e8 - VM-exit controls. /
3711	uint32_t u32ExitMsrStoreCount; /*< 0x1ec - VM-exit MSR store count. /
3712	uint32_t u32ExitMsrLoadCount; /*< 0x1f0 - VM-exit MSR load count. /
3713	uint32_t u32EntryCtls; /*< 0x1f4 - VM-entry controls. /
3714	uint32_t u32EntryMsrLoadCount; /*< 0x1f8 - VM-entry MSR load count. /
3715	uint32_t u32EntryIntInfo; /*< 0x1fc - VM-entry interruption information. /
3716	uint32_t u32EntryXcptErrCode; /*< 0x200 - VM-entry exception error code. /
3717	uint32_t u32EntryInstrLen; /*< 0x204 - VM-entry instruction length. /
3718	uint32_t u32TprThreshold; /*< 0x208 - TPR-threshold. /
3719	uint32_t u32ProcCtls2; /*< 0x20c - Secondary-processor based VM-execution controls. /
3720	uint32_t u32PleGap; /*< 0x210 - Pause-loop exiting Gap. /
3721	uint32_t u32PleWindow; /*< 0x214 - Pause-loop exiting Window. /
3722	uint32_t au32Reserved1[16]; /*< 0x218 - Reserved for future. /
3723
3724	/** 64-bit fields. */
3725	RTUINT64U u64AddrIoBitmapA; /*< 0x258 - I/O bitmap A address. /
3726	RTUINT64U u64AddrIoBitmapB; /*< 0x260 - I/O bitmap B address. /
3727	RTUINT64U u64AddrMsrBitmap; /*< 0x268 - MSR bitmap address. /
3728	RTUINT64U u64AddrExitMsrStore; /*< 0x270 - VM-exit MSR-store area address. /
3729	RTUINT64U u64AddrExitMsrLoad; /*< 0x278 - VM-exit MSR-load area address. /
3730	RTUINT64U u64AddrEntryMsrLoad; /*< 0x280 - VM-entry MSR-load area address. /
3731	RTUINT64U u64ExecVmcsPtr; /*< 0x288 - Executive-VMCS pointer. /
3732	RTUINT64U u64AddrPml; /*< 0x290 - PML address. /
3733	RTUINT64U u64TscOffset; /*< 0x298 - TSC offset. /
3734	RTUINT64U u64AddrVirtApic; /*< 0x2a0 - Virtual-APIC address. /
3735	RTUINT64U u64AddrApicAccess; /*< 0x2a8 - APIC-access address. /
3736	RTUINT64U u64AddrPostedIntDesc; /*< 0x2b0 - Posted-interrupt descriptor address. /
3737	RTUINT64U u64VmFuncCtls; /*< 0x2b8 - VM-functions control. /
3738	RTUINT64U u64EptpPtr; /*< 0x2c0 - EPTP pointer. /
3739	RTUINT64U u64EoiExitBitmap0; /*< 0x2c8 - EOI-exit bitmap 0. /
3740	RTUINT64U u64EoiExitBitmap1; /*< 0x2d0 - EOI-exit bitmap 1. /
3741	RTUINT64U u64EoiExitBitmap2; /*< 0x2d8 - EOI-exit bitmap 2. /
3742	RTUINT64U u64EoiExitBitmap3; /*< 0x2e0 - EOI-exit bitmap 3. /
3743	RTUINT64U u64AddrEptpList; /*< 0x2e8 - EPTP-list address. /
3744	RTUINT64U u64AddrVmreadBitmap; /*< 0x2f0 - VMREAD-bitmap address. /
3745	RTUINT64U u64AddrVmwriteBitmap; /*< 0x2f8 - VMWRITE-bitmap address. /
3746	RTUINT64U u64AddrXcptVeInfo; /*< 0x300 - Virtualization-exception information address. /
3747	RTUINT64U u64XssBitmap; /*< 0x308 - XSS-exiting bitmap. /
3748	RTUINT64U u64EnclsBitmap; /*< 0x310 - ENCLS-exiting bitmap address. /
3749	RTUINT64U u64SpptPtr; /*< 0x318 - Sub-page-permission-table pointer. /
3750	RTUINT64U u64TscMultiplier; /*< 0x320 - TSC multiplier. /
3751	RTUINT64U au64Reserved0[15]; /*< 0x328 - Reserved for future. /
3752
3753	/** Natural-width fields. */
3754	RTUINT64U u64Cr0Mask; /*< 0x3a0 - CR0 guest/host Mask. /
3755	RTUINT64U u64Cr4Mask; /*< 0x3a8 - CR4 guest/host Mask. /
3756	RTUINT64U u64Cr0ReadShadow; /*< 0x3b0 - CR0 read shadow. /
3757	RTUINT64U u64Cr4ReadShadow; /*< 0x3b8 - CR4 read shadow. /
3758	RTUINT64U u64Cr3Target0; /*< 0x3c0 - CR3-target value 0. /
3759	RTUINT64U u64Cr3Target1; /*< 0x3c8 - CR3-target value 1. /
3760	RTUINT64U u64Cr3Target2; /*< 0x3d0 - CR3-target value 2. /
3761	RTUINT64U u64Cr3Target3; /*< 0x3d8 - CR3-target value 3. /
3762	RTUINT64U au64Reserved4[32]; /*< 0x3e0 - Reserved for future. /
3763	/** @} */
3764
3765	/** @name Host-state fields.
3766	* @{ */
3767	/** 16-bit fields. */
3768	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3769	RTSEL HostEs; /*< 0x4e0 - Host ES selector. /
3770	RTSEL HostCs; /*< 0x4e2 - Host CS selector. /
3771	RTSEL HostSs; /*< 0x4e4 - Host SS selector. /
3772	RTSEL HostDs; /*< 0x4e6 - Host DS selector. /
3773	RTSEL HostFs; /*< 0x4e8 - Host FS selector. /
3774	RTSEL HostGs; /*< 0x4ea - Host GS selector. /
3775	RTSEL HostTr; /*< 0x4ec - Host TR selector. /
3776	uint16_t au16Reserved2[13]; /*< 0x4ee - Reserved for future. /
3777
3778	/** 32-bit fields. */
3779	uint32_t u32HostSysenterCs; /*< 0x508 - Host SYSENTER CS. /
3780	uint32_t au32Reserved4[11]; /*< 0x50c - Reserved for future. /
3781
3782	/** 64-bit fields. */
3783	RTUINT64U u64HostPatMsr; /*< 0x538 - Host PAT MSR. /
3784	RTUINT64U u64HostEferMsr; /*< 0x540 - Host EFER MSR. /
3785	RTUINT64U u64HostPerfGlobalCtlMsr; /*< 0x548 - Host global performance-control MSR. /
3786	RTUINT64U au64Reserved3[16]; /*< 0x550 - Reserved for future. /
3787
3788	/** Natural-width fields. */
3789	RTUINT64U u64HostCr0; /*< 0x5d0 - Host CR0. /
3790	RTUINT64U u64HostCr3; /*< 0x5d8 - Host CR3. /
3791	RTUINT64U u64HostCr4; /*< 0x5e0 - Host CR4. /
3792	RTUINT64U u64HostFsBase; /*< 0x5e8 - Host FS base. /
3793	RTUINT64U u64HostGsBase; /*< 0x5f0 - Host GS base. /
3794	RTUINT64U u64HostTrBase; /*< 0x5f8 - Host TR base. /
3795	RTUINT64U u64HostGdtrBase; /*< 0x600 - Host GDTR base. /
3796	RTUINT64U u64HostIdtrBase; /*< 0x608 - Host IDTR base. /
3797	RTUINT64U u64HostSysenterEsp; /*< 0x610 - Host SYSENTER ESP base. /
3798	RTUINT64U u64HostSysenterEip; /*< 0x618 - Host SYSENTER ESP base. /
3799	RTUINT64U u64HostRsp; /*< 0x620 - Host RSP. /
3800	RTUINT64U u64HostRip; /*< 0x628 - Host RIP. /
3801	RTUINT64U au64Reserved7[32]; /*< 0x630 - Reserved for future. /
3802	/** @} */
3803
3804	/** @name Guest-state fields.
3805	* @{ */
3806	/** 16-bit fields. */
3807	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3808	RTSEL GuestEs; /*< 0x730 - Guest ES selector. /
3809	RTSEL GuestCs; /*< 0x732 - Guest ES selector. /
3810	RTSEL GuestSs; /*< 0x734 - Guest ES selector. /
3811	RTSEL GuestDs; /*< 0x736 - Guest ES selector. /
3812	RTSEL GuestFs; /*< 0x738 - Guest ES selector. /
3813	RTSEL GuestGs; /*< 0x73a - Guest ES selector. /
3814	RTSEL GuestLdtr; /*< 0x73c - Guest LDTR selector. /
3815	RTSEL GuestTr; /*< 0x73e - Guest TR selector. /
3816	uint16_t u16GuestIntStatus; /*< 0x740 - Guest interrupt status (virtual-interrupt delivery). /
3817	uint16_t u16PmlIndex; /*< 0x742 - PML index. /
3818	uint16_t au16Reserved1[14]; /*< 0x744 - Reserved for future. /
3819
3820	/** 32-bit fields. */
3821	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
3822	uint32_t u32GuestEsLimit; /*< 0x760 - Guest ES limit. /
3823	uint32_t u32GuestCsLimit; /*< 0x764 - Guest CS limit. /
3824	uint32_t u32GuestSsLimit; /*< 0x768 - Guest SS limit. /
3825	uint32_t u32GuestDsLimit; /*< 0x76c - Guest DS limit. /
3826	uint32_t u32GuestFsLimit; /*< 0x770 - Guest FS limit. /
3827	uint32_t u32GuestGsLimit; /*< 0x774 - Guest GS limit. /
3828	uint32_t u32GuestLdtrLimit; /*< 0x778 - Guest LDTR limit. /
3829	uint32_t u32GuestTrLimit; /*< 0x77c - Guest TR limit. /
3830	uint32_t u32GuestGdtrLimit; /*< 0x780 - Guest GDTR limit. /
3831	uint32_t u32GuestIdtrLimit; /*< 0x784 - Guest IDTR limit. /
3832	uint32_t u32GuestEsAttr; /*< 0x788 - Guest ES attributes. /
3833	uint32_t u32GuestCsAttr; /*< 0x78c - Guest CS attributes. /
3834	uint32_t u32GuestSsAttr; /*< 0x790 - Guest SS attributes. /
3835	uint32_t u32GuestDsAttr; /*< 0x794 - Guest DS attributes. /
3836	uint32_t u32GuestFsAttr; /*< 0x798 - Guest FS attributes. /
3837	uint32_t u32GuestGsAttr; /*< 0x79c - Guest GS attributes. /
3838	uint32_t u32GuestLdtrAttr; /*< 0x7a0 - Guest LDTR attributes. /
3839	uint32_t u32GuestTrAttr; /*< 0x7a4 - Guest TR attributes. /
3840	uint32_t u32GuestIntrState; /*< 0x7a8 - Guest interruptibility state. /
3841	uint32_t u32GuestActivityState; /*< 0x7ac - Guest activity state. /
3842	uint32_t u32GuestSmBase; /*< 0x7b0 - Guest SMBASE. /
3843	uint32_t u32GuestSysenterCS; /*< 0x7b4 - Guest SYSENTER CS. /
3844	uint32_t u32PreemptTimer; /*< 0x7b8 - Preemption timer value. /
3845	uint32_t au32Reserved3[11]; /*< 0x7bc - Reserved for future. /
3846
3847	/** 64-bit fields. */
3848	RTUINT64U u64VmcsLinkPtr; /*< 0x7e8 - VMCS link pointer. /
3849	RTUINT64U u64GuestDebugCtlMsr; /*< 0x7f0 - Guest debug-control MSR. /
3850	RTUINT64U u64GuestPatMsr; /*< 0x7f8 - Guest PAT MSR. /
3851	RTUINT64U u64GuestEferMsr; /*< 0x800 - Guest EFER MSR. /
3852	RTUINT64U u64GuestPerfGlobalCtlMsr; /*< 0x808 - Guest global performance-control MSR. /
3853	RTUINT64U u64GuestPdpte0; /*< 0x810 - Guest PDPTE 0. /
3854	RTUINT64U u64GuestPdpte1; /*< 0x818 - Guest PDPTE 0. /
3855	RTUINT64U u64GuestPdpte2; /*< 0x820 - Guest PDPTE 1. /
3856	RTUINT64U u64GuestPdpte3; /*< 0x828 - Guest PDPTE 2. /
3857	RTUINT64U u64GuestBndcfgsMsr; /*< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). /
3858	RTUINT64U u64GuestRtitCtlMsr; /*< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). /
3859	RTUINT64U au64Reserved2[32]; /*< 0x840 - Reserved for future. /
3860
3861	/** Natural-width fields. */
3862	RTUINT64U u64GuestCr0; /*< 0x940 - Guest CR0. /
3863	RTUINT64U u64GuestCr3; /*< 0x948 - Guest CR3. /
3864	RTUINT64U u64GuestCr4; /*< 0x950 - Guest CR4. /
3865	RTUINT64U u64GuestEsBase; /*< 0x958 - Guest ES base. /
3866	RTUINT64U u64GuestCsBase; /*< 0x960 - Guest CS base. /
3867	RTUINT64U u64GuestSsBase; /*< 0x968 - Guest SS base. /
3868	RTUINT64U u64GuestDsBase; /*< 0x970 - Guest DS base. /
3869	RTUINT64U u64GuestFsBase; /*< 0x978 - Guest FS base. /
3870	RTUINT64U u64GuestGsBase; /*< 0x980 - Guest GS base. /
3871	RTUINT64U u64GuestLdtrBase; /*< 0x988 - Guest LDTR base. /
3872	RTUINT64U u64GuestTrBase; /*< 0x990 - Guest TR base. /
3873	RTUINT64U u64GuestGdtrBase; /*< 0x998 - Guest GDTR base. /
3874	RTUINT64U u64GuestIdtrBase; /*< 0x9a0 - Guest IDTR base. /
3875	RTUINT64U u64GuestDr7; /*< 0x9a8 - Guest DR7. /
3876	RTUINT64U u64GuestRsp; /*< 0x9b0 - Guest RSP. /
3877	RTUINT64U u64GuestRip; /*< 0x9b8 - Guest RIP. /
3878	RTUINT64U u64GuestRFlags; /*< 0x9c0 - Guest RFLAGS. /
3879	RTUINT64U u64GuestPendingDbgXcpts; /*< 0x9c8 - Guest pending debug exceptions. /
3880	RTUINT64U u64GuestSysenterEsp; /*< 0x9d0 - Guest SYSENTER ESP. /
3881	RTUINT64U u64GuestSysenterEip; /*< 0x9d8 - Guest SYSENTER EIP. /
3882	RTUINT64U au64Reserved6[32]; /*< 0x9e0 - Reserved for future. /
3883	/** @} */
3884
3885	/** 0xae0 - Padding / reserved for future use. */
3886	uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
3887	} VMXVVMCS;
3888	#pragma pack()
3889	/** Pointer to the VMXVVMCS struct. */
3890	typedef VMXVVMCS *PVMXVVMCS;
3891	/** Pointer to a const VMXVVMCS struct. */
3892	typedef const VMXVVMCS *PCVMXVVMCS;
3893	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3894	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3895	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
3896	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3897	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
3898	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
3899	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
3900	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
3901	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
3902	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
3903	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
3904	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
3905	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
3906	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
3907	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
3908	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
3909	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
3910	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
3911	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
3912
3913	/**
3914	* Virtual VMX-instruction and VM-exit diagnostics.
3915	*
3916	* These are not the same as VM instruction errors that are enumerated in the Intel
3917	* spec. These are purely internal, fine-grained definitions used for diagnostic
3918	* purposes and are not reported to guest software under the VM-instruction error
3919	* field in its VMCS.
3920	*
3921	* @note Members of this enum are used as array indices, so no gaps are allowed.
3922	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
3923	*/
3924	typedef enum
3925	{
3926	/* Internal processing errors. */
3927	kVmxVDiag_None = 0,
3928	kVmxVDiag_Ipe_1,
3929	kVmxVDiag_Ipe_2,
3930	kVmxVDiag_Ipe_3,
3931	kVmxVDiag_Ipe_4,
3932	kVmxVDiag_Ipe_5,
3933	kVmxVDiag_Ipe_6,
3934	kVmxVDiag_Ipe_7,
3935	kVmxVDiag_Ipe_8,
3936	kVmxVDiag_Ipe_9,
3937	kVmxVDiag_Ipe_10,
3938	kVmxVDiag_Ipe_11,
3939	kVmxVDiag_Ipe_12,
3940	kVmxVDiag_Ipe_13,
3941	kVmxVDiag_Ipe_14,
3942	kVmxVDiag_Ipe_15,
3943	kVmxVDiag_Ipe_16,
3944	/* VMXON. */
3945	kVmxVDiag_Vmxon_A20M,
3946	kVmxVDiag_Vmxon_Cpl,
3947	kVmxVDiag_Vmxon_Cr0Fixed0,
3948	kVmxVDiag_Vmxon_Cr0Fixed1,
3949	kVmxVDiag_Vmxon_Cr4Fixed0,
3950	kVmxVDiag_Vmxon_Cr4Fixed1,
3951	kVmxVDiag_Vmxon_Intercept,
3952	kVmxVDiag_Vmxon_LongModeCS,
3953	kVmxVDiag_Vmxon_MsrFeatCtl,
3954	kVmxVDiag_Vmxon_PtrAbnormal,
3955	kVmxVDiag_Vmxon_PtrAlign,
3956	kVmxVDiag_Vmxon_PtrMap,
3957	kVmxVDiag_Vmxon_PtrReadPhys,
3958	kVmxVDiag_Vmxon_PtrWidth,
3959	kVmxVDiag_Vmxon_RealOrV86Mode,
3960	kVmxVDiag_Vmxon_ShadowVmcs,
3961	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3962	kVmxVDiag_Vmxon_Vmxe,
3963	kVmxVDiag_Vmxon_VmcsRevId,
3964	kVmxVDiag_Vmxon_VmxRootCpl,
3965	/* VMXOFF. */
3966	kVmxVDiag_Vmxoff_Cpl,
3967	kVmxVDiag_Vmxoff_Intercept,
3968	kVmxVDiag_Vmxoff_LongModeCS,
3969	kVmxVDiag_Vmxoff_RealOrV86Mode,
3970	kVmxVDiag_Vmxoff_Vmxe,
3971	kVmxVDiag_Vmxoff_VmxRoot,
3972	/* VMPTRLD. */
3973	kVmxVDiag_Vmptrld_Cpl,
3974	kVmxVDiag_Vmptrld_LongModeCS,
3975	kVmxVDiag_Vmptrld_PtrAbnormal,
3976	kVmxVDiag_Vmptrld_PtrAlign,
3977	kVmxVDiag_Vmptrld_PtrMap,
3978	kVmxVDiag_Vmptrld_PtrReadPhys,
3979	kVmxVDiag_Vmptrld_PtrVmxon,
3980	kVmxVDiag_Vmptrld_PtrWidth,
3981	kVmxVDiag_Vmptrld_RealOrV86Mode,
3982	kVmxVDiag_Vmptrld_RevPtrReadPhys,
3983	kVmxVDiag_Vmptrld_ShadowVmcs,
3984	kVmxVDiag_Vmptrld_VmcsRevId,
3985	kVmxVDiag_Vmptrld_VmxRoot,
3986	/* VMPTRST. */
3987	kVmxVDiag_Vmptrst_Cpl,
3988	kVmxVDiag_Vmptrst_LongModeCS,
3989	kVmxVDiag_Vmptrst_PtrMap,
3990	kVmxVDiag_Vmptrst_RealOrV86Mode,
3991	kVmxVDiag_Vmptrst_VmxRoot,
3992	/* VMCLEAR. */
3993	kVmxVDiag_Vmclear_Cpl,
3994	kVmxVDiag_Vmclear_LongModeCS,
3995	kVmxVDiag_Vmclear_PtrAbnormal,
3996	kVmxVDiag_Vmclear_PtrAlign,
3997	kVmxVDiag_Vmclear_PtrMap,
3998	kVmxVDiag_Vmclear_PtrReadPhys,
3999	kVmxVDiag_Vmclear_PtrVmxon,
4000	kVmxVDiag_Vmclear_PtrWidth,
4001	kVmxVDiag_Vmclear_RealOrV86Mode,
4002	kVmxVDiag_Vmclear_VmxRoot,
4003	/* VMWRITE. */
4004	kVmxVDiag_Vmwrite_Cpl,
4005	kVmxVDiag_Vmwrite_FieldInvalid,
4006	kVmxVDiag_Vmwrite_FieldRo,
4007	kVmxVDiag_Vmwrite_LinkPtrInvalid,
4008	kVmxVDiag_Vmwrite_LongModeCS,
4009	kVmxVDiag_Vmwrite_PtrInvalid,
4010	kVmxVDiag_Vmwrite_PtrMap,
4011	kVmxVDiag_Vmwrite_RealOrV86Mode,
4012	kVmxVDiag_Vmwrite_VmxRoot,
4013	/* VMREAD. */
4014	kVmxVDiag_Vmread_Cpl,
4015	kVmxVDiag_Vmread_FieldInvalid,
4016	kVmxVDiag_Vmread_LinkPtrInvalid,
4017	kVmxVDiag_Vmread_LongModeCS,
4018	kVmxVDiag_Vmread_PtrInvalid,
4019	kVmxVDiag_Vmread_PtrMap,
4020	kVmxVDiag_Vmread_RealOrV86Mode,
4021	kVmxVDiag_Vmread_VmxRoot,
4022	/* INVVPID. */
4023	kVmxVDiag_Invvpid_Cpl,
4024	kVmxVDiag_Invvpid_DescRsvd,
4025	kVmxVDiag_Invvpid_LongModeCS,
4026	kVmxVDiag_Invvpid_RealOrV86Mode,
4027	kVmxVDiag_Invvpid_TypeInvalid,
4028	kVmxVDiag_Invvpid_Type0InvalidAddr,
4029	kVmxVDiag_Invvpid_Type0InvalidVpid,
4030	kVmxVDiag_Invvpid_Type1InvalidVpid,
4031	kVmxVDiag_Invvpid_Type3InvalidVpid,
4032	kVmxVDiag_Invvpid_VmxRoot,
4033	/* VMLAUNCH/VMRESUME. */
4034	kVmxVDiag_Vmentry_AddrApicAccess,
4035	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
4036	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
4037	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
4038	kVmxVDiag_Vmentry_AddrExitMsrLoad,
4039	kVmxVDiag_Vmentry_AddrExitMsrStore,
4040	kVmxVDiag_Vmentry_AddrIoBitmapA,
4041	kVmxVDiag_Vmentry_AddrIoBitmapB,
4042	kVmxVDiag_Vmentry_AddrMsrBitmap,
4043	kVmxVDiag_Vmentry_AddrVirtApicPage,
4044	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4045	kVmxVDiag_Vmentry_AddrVmreadBitmap,
4046	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4047	kVmxVDiag_Vmentry_ApicRegVirt,
4048	kVmxVDiag_Vmentry_BlocKMovSS,
4049	kVmxVDiag_Vmentry_Cpl,
4050	kVmxVDiag_Vmentry_Cr3TargetCount,
4051	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4052	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4053	kVmxVDiag_Vmentry_EntryInstrLen,
4054	kVmxVDiag_Vmentry_EntryInstrLenZero,
4055	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4056	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4057	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4058	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4059	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4060	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4061	kVmxVDiag_Vmentry_GuestActStateHlt,
4062	kVmxVDiag_Vmentry_GuestActStateRsvd,
4063	kVmxVDiag_Vmentry_GuestActStateShutdown,
4064	kVmxVDiag_Vmentry_GuestActStateSsDpl,
4065	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4066	kVmxVDiag_Vmentry_GuestCr0Fixed0,
4067	kVmxVDiag_Vmentry_GuestCr0Fixed1,
4068	kVmxVDiag_Vmentry_GuestCr0PgPe,
4069	kVmxVDiag_Vmentry_GuestCr3,
4070	kVmxVDiag_Vmentry_GuestCr4Fixed0,
4071	kVmxVDiag_Vmentry_GuestCr4Fixed1,
4072	kVmxVDiag_Vmentry_GuestDebugCtl,
4073	kVmxVDiag_Vmentry_GuestDr7,
4074	kVmxVDiag_Vmentry_GuestEferMsr,
4075	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4076	kVmxVDiag_Vmentry_GuestGdtrBase,
4077	kVmxVDiag_Vmentry_GuestGdtrLimit,
4078	kVmxVDiag_Vmentry_GuestIdtrBase,
4079	kVmxVDiag_Vmentry_GuestIdtrLimit,
4080	kVmxVDiag_Vmentry_GuestIntStateEnclave,
4081	kVmxVDiag_Vmentry_GuestIntStateExtInt,
4082	kVmxVDiag_Vmentry_GuestIntStateNmi,
4083	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4084	kVmxVDiag_Vmentry_GuestIntStateRsvd,
4085	kVmxVDiag_Vmentry_GuestIntStateSmi,
4086	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4087	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4088	kVmxVDiag_Vmentry_GuestPae,
4089	kVmxVDiag_Vmentry_GuestPatMsr,
4090	kVmxVDiag_Vmentry_GuestPcide,
4091	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
4092	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
4093	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
4094	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
4095	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
4096	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4097	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4098	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4099	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4100	kVmxVDiag_Vmentry_GuestRip,
4101	kVmxVDiag_Vmentry_GuestRipRsvd,
4102	kVmxVDiag_Vmentry_GuestRFlagsIf,
4103	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4104	kVmxVDiag_Vmentry_GuestRFlagsVm,
4105	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4106	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4107	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4108	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4109	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4110	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4111	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4112	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4113	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4114	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4115	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4116	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4117	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4118	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4119	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4120	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4121	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4122	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4123	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4124	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4125	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4126	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4127	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4128	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4129	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4130	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4131	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4132	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4133	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4134	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4135	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4136	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4137	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4138	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4139	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4140	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4141	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4142	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4143	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4144	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4145	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4146	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4147	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4148	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4149	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4150	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4151	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4152	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4153	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4154	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4155	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4156	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4157	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4158	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4159	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4160	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4161	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4162	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4163	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4164	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4165	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4166	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4167	kVmxVDiag_Vmentry_GuestSegBaseCs,
4168	kVmxVDiag_Vmentry_GuestSegBaseDs,
4169	kVmxVDiag_Vmentry_GuestSegBaseEs,
4170	kVmxVDiag_Vmentry_GuestSegBaseFs,
4171	kVmxVDiag_Vmentry_GuestSegBaseGs,
4172	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4173	kVmxVDiag_Vmentry_GuestSegBaseSs,
4174	kVmxVDiag_Vmentry_GuestSegBaseTr,
4175	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4176	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4177	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4178	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4179	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4180	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4181	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4182	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4183	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4184	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4185	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4186	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4187	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4188	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4189	kVmxVDiag_Vmentry_GuestSegSelTr,
4190	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4191	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4192	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4193	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4194	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4195	kVmxVDiag_Vmentry_HostCr0Fixed0,
4196	kVmxVDiag_Vmentry_HostCr0Fixed1,
4197	kVmxVDiag_Vmentry_HostCr3,
4198	kVmxVDiag_Vmentry_HostCr4Fixed0,
4199	kVmxVDiag_Vmentry_HostCr4Fixed1,
4200	kVmxVDiag_Vmentry_HostCr4Pae,
4201	kVmxVDiag_Vmentry_HostCr4Pcide,
4202	kVmxVDiag_Vmentry_HostCsTr,
4203	kVmxVDiag_Vmentry_HostEferMsr,
4204	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4205	kVmxVDiag_Vmentry_HostGuestLongMode,
4206	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4207	kVmxVDiag_Vmentry_HostLongMode,
4208	kVmxVDiag_Vmentry_HostPatMsr,
4209	kVmxVDiag_Vmentry_HostRip,
4210	kVmxVDiag_Vmentry_HostRipRsvd,
4211	kVmxVDiag_Vmentry_HostSel,
4212	kVmxVDiag_Vmentry_HostSegBase,
4213	kVmxVDiag_Vmentry_HostSs,
4214	kVmxVDiag_Vmentry_HostSysenterEspEip,
4215	kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4216	kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4217	kVmxVDiag_Vmentry_LongModeCS,
4218	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4219	kVmxVDiag_Vmentry_MsrLoad,
4220	kVmxVDiag_Vmentry_MsrLoadCount,
4221	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4222	kVmxVDiag_Vmentry_MsrLoadRing3,
4223	kVmxVDiag_Vmentry_MsrLoadRsvd,
4224	kVmxVDiag_Vmentry_NmiWindowExit,
4225	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4226	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4227	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4228	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4229	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4230	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4231	kVmxVDiag_Vmentry_PtrInvalid,
4232	kVmxVDiag_Vmentry_PtrShadowVmcs,
4233	kVmxVDiag_Vmentry_RealOrV86Mode,
4234	kVmxVDiag_Vmentry_SavePreemptTimer,
4235	kVmxVDiag_Vmentry_TprThresholdRsvd,
4236	kVmxVDiag_Vmentry_TprThresholdVTpr,
4237	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4238	kVmxVDiag_Vmentry_VirtIntDelivery,
4239	kVmxVDiag_Vmentry_VirtNmi,
4240	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4241	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4242	kVmxVDiag_Vmentry_VmcsClear,
4243	kVmxVDiag_Vmentry_VmcsLaunch,
4244	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4245	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4246	kVmxVDiag_Vmentry_VmxRoot,
4247	kVmxVDiag_Vmentry_Vpid,
4248	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
4249	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
4250	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
4251	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
4252	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
4253	kVmxVDiag_Vmexit_MsrLoad,
4254	kVmxVDiag_Vmexit_MsrLoadCount,
4255	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4256	kVmxVDiag_Vmexit_MsrLoadRing3,
4257	kVmxVDiag_Vmexit_MsrLoadRsvd,
4258	kVmxVDiag_Vmexit_MsrStore,
4259	kVmxVDiag_Vmexit_MsrStoreCount,
4260	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4261	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4262	kVmxVDiag_Vmexit_MsrStoreRing3,
4263	kVmxVDiag_Vmexit_MsrStoreRsvd,
4264	kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4265	/* Last member for determining array index limit. */
4266	kVmxVDiag_End
4267	} VMXVDIAG;
4268	AssertCompileSize(VMXVDIAG, 4);
4269
4270	/** @} */
4271
4272	/** @} */
4273
4274	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4275

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 87385

以其他格式下載: