hm_vmx.h@ 60177

最後變更在這個檔案從60177是 59614,由 vboxsync 提交於 9 年前
hm_vmx.h: added posted-interrupt pin-based ctrl value.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.alldomusa.eu.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# include <intrin.h>
38	/* We always want them as intrinsics, no functions. */
39	# pragma intrinsic(__vmx_on)
40	# pragma intrinsic(__vmx_off)
41	# pragma intrinsic(__vmx_vmclear)
42	# pragma intrinsic(__vmx_vmptrld)
43	# pragma intrinsic(__vmx_vmread)
44	# pragma intrinsic(__vmx_vmwrite)
45	# define VMX_USE_MSC_INTRINSICS 1
46	#else
47	# define VMX_USE_MSC_INTRINSICS 0
48	#endif
49
50
51	/** @defgroup grp_hm_vmx VMX Types and Definitions
52	* @ingroup grp_hm
53	* @{
54	*/
55
56	/** @def HMVMXCPU_GST_SET_UPDATED
57	* Sets a guest-state-updated flag.
58	*
59	* @param pVCpu The cross context virtual CPU structure.
60	* @param fFlag The flag to set.
61	*/
62	#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
63
64	/** @def HMVMXCPU_GST_IS_SET
65	* Checks if all the flags in the specified guest-state-updated set is pending.
66	*
67	* @param pVCpu The cross context virtual CPU structure.
68	* @param fFlag The flag to check.
69	*/
70	#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
71
72	/** @def HMVMXCPU_GST_IS_UPDATED
73	* Checks if one or more of the flags in the specified guest-state-updated set
74	* is updated.
75	*
76	* @param pVCpu The cross context virtual CPU structure.
77	* @param fFlags The flags to check for.
78	*/
79	#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
80
81	/** @def HMVMXCPU_GST_RESET_TO
82	* Resets the guest-state-updated flags to the specified value.
83	*
84	* @param pVCpu The cross context virtual CPU structure.
85	* @param fFlags The new value.
86	*/
87	#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
88
89	/** @def HMVMXCPU_GST_VALUE
90	* Returns the current guest-state-updated flags value.
91	*
92	* @param pVCpu The cross context virtual CPU structure.
93	*/
94	#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
95
96	/** @name Host-state restoration flags.
97	* @note If you change these values don't forget to update the assembly
98	* defines as well!
99	* @{
100	*/
101	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
102	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
103	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
104	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
105	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
106	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
107	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
108	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
109	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
110	/** @} */
111
112	/**
113	* Host-state restoration structure.
114	* This holds host-state fields that require manual restoration.
115	* Assembly version found in hm_vmx.mac (should be automatically verified).
116	*/
117	typedef struct VMXRESTOREHOST
118	{
119	RTSEL uHostSelDS; /* 0x00 */
120	RTSEL uHostSelES; /* 0x02 */
121	RTSEL uHostSelFS; /* 0x04 */
122	RTSEL uHostSelGS; /* 0x06 */
123	RTSEL uHostSelTR; /* 0x08 */
124	uint8_t abPadding0[4];
125	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
126	uint8_t abPadding1[6];
127	X86XDTR64 HostIdtr; /*< 0x1e - should be aligned by it's 64-bit member. /
128	uint64_t uHostFSBase; /* 0x28 */
129	uint64_t uHostGSBase; /* 0x30 */
130	} VMXRESTOREHOST;
131	/** Pointer to VMXRESTOREHOST. */
132	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
133	AssertCompileSize(X86XDTR64, 10);
134	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
135	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
136	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
137	AssertCompileSize(VMXRESTOREHOST, 56);
138	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
139
140	/** @name Host-state MSR lazy-restoration flags.
141	* @{
142	*/
143	/** The host MSRs have been saved. */
144	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
145	/** The guest MSRs are loaded and in effect. */
146	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
147	/** @} */
148
149	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
150	* UFC = Unsupported Feature Combination.
151	* @{
152	*/
153	/** Unsupported pin-based VM-execution controls combo. */
154	#define VMX_UFC_CTRL_PIN_EXEC 0
155	/** Unsupported processor-based VM-execution controls combo. */
156	#define VMX_UFC_CTRL_PROC_EXEC 1
157	/** Unsupported move debug register VM-exit combo. */
158	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
159	/** Unsupported VM-entry controls combo. */
160	#define VMX_UFC_CTRL_ENTRY 3
161	/** Unsupported VM-exit controls combo. */
162	#define VMX_UFC_CTRL_EXIT 4
163	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
164	* for storing host MSRs. */
165	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
166	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
167	* for storing guest MSRs. */
168	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
169	/** Invalid VMCS size. */
170	#define VMX_UFC_INVALID_VMCS_SIZE 7
171	/** Unsupported secondary processor-based VM-execution controls combo. */
172	#define VMX_UFC_CTRL_PROC_EXEC2 8
173	/** Invalid unrestricted-guest execution controls combo. */
174	#define VMX_UFC_INVALID_UX_COMBO 9
175	/** EPT flush type not supported. */
176	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 10
177	/** EPT paging structure memory type is not write-back. */
178	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 11
179	/** EPT requires INVEPT instr. support but it's not available. */
180	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 12
181	/** EPT requires page-walk length of 4. */
182	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 13
183	/** @} */
184
185	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
186	* IGS = Invalid Guest State.
187	* @{
188	*/
189	/** An error occurred while checking invalid-guest-state. */
190	#define VMX_IGS_ERROR 0
191	/** The invalid guest-state checks did not find any reason why. */
192	#define VMX_IGS_REASON_NOT_FOUND 1
193	/** CR0 fixed1 bits invalid. */
194	#define VMX_IGS_CR0_FIXED1 2
195	/** CR0 fixed0 bits invalid. */
196	#define VMX_IGS_CR0_FIXED0 3
197	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
198	#define VMX_IGS_CR0_PG_PE_COMBO 4
199	/** CR4 fixed1 bits invalid. */
200	#define VMX_IGS_CR4_FIXED1 5
201	/** CR4 fixed0 bits invalid. */
202	#define VMX_IGS_CR4_FIXED0 6
203	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
204	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
205	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
206	/** CR0.PG not set for long-mode when not using unrestricted guest. */
207	#define VMX_IGS_CR0_PG_LONGMODE 8
208	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
209	#define VMX_IGS_CR4_PAE_LONGMODE 9
210	/** CR4.PCIDE set for 32-bit guest. */
211	#define VMX_IGS_CR4_PCIDE 10
212	/** VMCS' DR7 reserved bits not set to 0. */
213	#define VMX_IGS_DR7_RESERVED 11
214	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
215	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
216	/** VMCS' EFER MSR reserved bits not set to 0. */
217	#define VMX_IGS_EFER_MSR_RESERVED 13
218	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
219	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
220	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
221	* without unrestricted guest. */
222	#define VMX_IGS_EFER_LMA_LME_MISMATCH 15
223	/** CS.Attr.P bit invalid. */
224	#define VMX_IGS_CS_ATTR_P_INVALID 16
225	/** CS.Attr reserved bits not set to 0. */
226	#define VMX_IGS_CS_ATTR_RESERVED 17
227	/** CS.Attr.G bit invalid. */
228	#define VMX_IGS_CS_ATTR_G_INVALID 18
229	/** CS is unusable. */
230	#define VMX_IGS_CS_ATTR_UNUSABLE 19
231	/** CS and SS DPL unequal. */
232	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
233	/** CS and SS DPL mismatch. */
234	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
235	/** CS Attr.Type invalid. */
236	#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
237	/** CS and SS RPL unequal. */
238	#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
239	/** SS.Attr.DPL and SS RPL unequal. */
240	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
241	/** SS.Attr.DPL invalid for segment type. */
242	#define VMX_IGS_SS_ATTR_DPL_INVALID 25
243	/** SS.Attr.Type invalid. */
244	#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
245	/** SS.Attr.P bit invalid. */
246	#define VMX_IGS_SS_ATTR_P_INVALID 27
247	/** SS.Attr reserved bits not set to 0. */
248	#define VMX_IGS_SS_ATTR_RESERVED 28
249	/** SS.Attr.G bit invalid. */
250	#define VMX_IGS_SS_ATTR_G_INVALID 29
251	/** DS.Attr.A bit invalid. */
252	#define VMX_IGS_DS_ATTR_A_INVALID 30
253	/** DS.Attr.P bit invalid. */
254	#define VMX_IGS_DS_ATTR_P_INVALID 31
255	/** DS.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
257	/** DS.Attr reserved bits not set to 0. */
258	#define VMX_IGS_DS_ATTR_RESERVED 33
259	/** DS.Attr.G bit invalid. */
260	#define VMX_IGS_DS_ATTR_G_INVALID 34
261	/** DS.Attr.Type invalid. */
262	#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
263	/** ES.Attr.A bit invalid. */
264	#define VMX_IGS_ES_ATTR_A_INVALID 36
265	/** ES.Attr.P bit invalid. */
266	#define VMX_IGS_ES_ATTR_P_INVALID 37
267	/** ES.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
269	/** ES.Attr reserved bits not set to 0. */
270	#define VMX_IGS_ES_ATTR_RESERVED 39
271	/** ES.Attr.G bit invalid. */
272	#define VMX_IGS_ES_ATTR_G_INVALID 40
273	/** ES.Attr.Type invalid. */
274	#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
275	/** FS.Attr.A bit invalid. */
276	#define VMX_IGS_FS_ATTR_A_INVALID 42
277	/** FS.Attr.P bit invalid. */
278	#define VMX_IGS_FS_ATTR_P_INVALID 43
279	/** FS.Attr.DPL and DS RPL unequal. */
280	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
281	/** FS.Attr reserved bits not set to 0. */
282	#define VMX_IGS_FS_ATTR_RESERVED 45
283	/** FS.Attr.G bit invalid. */
284	#define VMX_IGS_FS_ATTR_G_INVALID 46
285	/** FS.Attr.Type invalid. */
286	#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
287	/** GS.Attr.A bit invalid. */
288	#define VMX_IGS_GS_ATTR_A_INVALID 48
289	/** GS.Attr.P bit invalid. */
290	#define VMX_IGS_GS_ATTR_P_INVALID 49
291	/** GS.Attr.DPL and DS RPL unequal. */
292	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
293	/** GS.Attr reserved bits not set to 0. */
294	#define VMX_IGS_GS_ATTR_RESERVED 51
295	/** GS.Attr.G bit invalid. */
296	#define VMX_IGS_GS_ATTR_G_INVALID 52
297	/** GS.Attr.Type invalid. */
298	#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
299	/** V86 mode CS.Base invalid. */
300	#define VMX_IGS_V86_CS_BASE_INVALID 54
301	/** V86 mode CS.Limit invalid. */
302	#define VMX_IGS_V86_CS_LIMIT_INVALID 55
303	/** V86 mode CS.Attr invalid. */
304	#define VMX_IGS_V86_CS_ATTR_INVALID 56
305	/** V86 mode SS.Base invalid. */
306	#define VMX_IGS_V86_SS_BASE_INVALID 57
307	/** V86 mode SS.Limit invalid. */
308	#define VMX_IGS_V86_SS_LIMIT_INVALID 58
309	/** V86 mode SS.Attr invalid. */
310	#define VMX_IGS_V86_SS_ATTR_INVALID 59
311	/** V86 mode DS.Base invalid. */
312	#define VMX_IGS_V86_DS_BASE_INVALID 60
313	/** V86 mode DS.Limit invalid. */
314	#define VMX_IGS_V86_DS_LIMIT_INVALID 61
315	/** V86 mode DS.Attr invalid. */
316	#define VMX_IGS_V86_DS_ATTR_INVALID 62
317	/** V86 mode ES.Base invalid. */
318	#define VMX_IGS_V86_ES_BASE_INVALID 63
319	/** V86 mode ES.Limit invalid. */
320	#define VMX_IGS_V86_ES_LIMIT_INVALID 64
321	/** V86 mode ES.Attr invalid. */
322	#define VMX_IGS_V86_ES_ATTR_INVALID 65
323	/** V86 mode FS.Base invalid. */
324	#define VMX_IGS_V86_FS_BASE_INVALID 66
325	/** V86 mode FS.Limit invalid. */
326	#define VMX_IGS_V86_FS_LIMIT_INVALID 67
327	/** V86 mode FS.Attr invalid. */
328	#define VMX_IGS_V86_FS_ATTR_INVALID 68
329	/** V86 mode GS.Base invalid. */
330	#define VMX_IGS_V86_GS_BASE_INVALID 69
331	/** V86 mode GS.Limit invalid. */
332	#define VMX_IGS_V86_GS_LIMIT_INVALID 70
333	/** V86 mode GS.Attr invalid. */
334	#define VMX_IGS_V86_GS_ATTR_INVALID 71
335	/** Longmode CS.Base invalid. */
336	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
337	/** Longmode SS.Base invalid. */
338	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
339	/** Longmode DS.Base invalid. */
340	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
341	/** Longmode ES.Base invalid. */
342	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
343	/** SYSENTER ESP is not canonical. */
344	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
345	/** SYSENTER EIP is not canonical. */
346	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
347	/** PAT MSR invalid. */
348	#define VMX_IGS_PAT_MSR_INVALID 78
349	/** PAT MSR reserved bits not set to 0. */
350	#define VMX_IGS_PAT_MSR_RESERVED 79
351	/** GDTR.Base is not canonical. */
352	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
353	/** IDTR.Base is not canonical. */
354	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
355	/** GDTR.Limit invalid. */
356	#define VMX_IGS_GDTR_LIMIT_INVALID 82
357	/** IDTR.Limit invalid. */
358	#define VMX_IGS_IDTR_LIMIT_INVALID 83
359	/** Longmode RIP is invalid. */
360	#define VMX_IGS_LONGMODE_RIP_INVALID 84
361	/** RFLAGS reserved bits not set to 0. */
362	#define VMX_IGS_RFLAGS_RESERVED 85
363	/** RFLAGS RA1 reserved bits not set to 1. */
364	#define VMX_IGS_RFLAGS_RESERVED1 86
365	/** RFLAGS.VM (V86 mode) invalid. */
366	#define VMX_IGS_RFLAGS_VM_INVALID 87
367	/** RFLAGS.IF invalid. */
368	#define VMX_IGS_RFLAGS_IF_INVALID 88
369	/** Activity state invalid. */
370	#define VMX_IGS_ACTIVITY_STATE_INVALID 89
371	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
372	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
373	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
374	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
375	/** Activity state SIPI WAIT invalid. */
376	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
377	/** Interruptibility state reserved bits not set to 0. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
379	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
381	/** Interruptibility state block-by-STI invalid for EFLAGS. */
382	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
383	/** Interruptibility state invalid while trying to deliver external
384	* interrupt. */
385	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
386	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
387	* NMI. */
388	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
389	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
390	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
391	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
392	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
393	/** Interruptibility state block-by-STI (maybe) invalid when trying to
394	* deliver an NMI. */
395	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
396	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
397	* active. */
398	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
399	/** Pending debug exceptions reserved bits not set to 0. */
400	#define VMX_IGS_PENDING_DEBUG_RESERVED 102
401	/** Longmode pending debug exceptions reserved bits not set to 0. */
402	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
403	/** Pending debug exceptions.BS bit is not set when it should be. */
404	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
405	/** Pending debug exceptions.BS bit is not clear when it should be. */
406	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
407	/** VMCS link pointer reserved bits not set to 0. */
408	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
409	/** TR cannot index into LDT, TI bit MBZ. */
410	#define VMX_IGS_TR_TI_INVALID 107
411	/** LDTR cannot index into LDT. TI bit MBZ. */
412	#define VMX_IGS_LDTR_TI_INVALID 108
413	/** TR.Base is not canonical. */
414	#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
415	/** FS.Base is not canonical. */
416	#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
417	/** GS.Base is not canonical. */
418	#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
419	/** LDTR.Base is not canonical. */
420	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
421	/** TR is unusable. */
422	#define VMX_IGS_TR_ATTR_UNUSABLE 113
423	/** TR.Attr.S bit invalid. */
424	#define VMX_IGS_TR_ATTR_S_INVALID 114
425	/** TR is not present. */
426	#define VMX_IGS_TR_ATTR_P_INVALID 115
427	/** TR.Attr reserved bits not set to 0. */
428	#define VMX_IGS_TR_ATTR_RESERVED 116
429	/** TR.Attr.G bit invalid. */
430	#define VMX_IGS_TR_ATTR_G_INVALID 117
431	/** Longmode TR.Attr.Type invalid. */
432	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
433	/** TR.Attr.Type invalid. */
434	#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
435	/** CS.Attr.S invalid. */
436	#define VMX_IGS_CS_ATTR_S_INVALID 120
437	/** CS.Attr.DPL invalid. */
438	#define VMX_IGS_CS_ATTR_DPL_INVALID 121
439	/** PAE PDPTE reserved bits not set to 0. */
440	#define VMX_IGS_PAE_PDPTE_RESERVED 123
441	/** @} */
442
443	/** @name VMX VMCS-Read cache indices.
444	* @{
445	*/
446	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
447	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
448	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
449	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
450	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
451	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
452	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
453	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
454	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
455	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
456	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
457	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
458	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
459	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
460	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
461	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
462	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
463	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
464	/** @} */
465
466	/** @name VMX EPT paging structures
467	* @{
468	*/
469
470	/**
471	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
472	*/
473	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
474
475	/**
476	* EPT Page Directory Pointer Entry. Bit view.
477	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
478	* this did cause trouble with one compiler/version).
479	*/
480	typedef struct EPTPML4EBITS
481	{
482	/** Present bit. */
483	uint64_t u1Present : 1;
484	/** Writable bit. */
485	uint64_t u1Write : 1;
486	/** Executable bit. */
487	uint64_t u1Execute : 1;
488	/** Reserved (must be 0). */
489	uint64_t u5Reserved : 5;
490	/** Available for software. */
491	uint64_t u4Available : 4;
492	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
493	uint64_t u40PhysAddr : 40;
494	/** Available for software. */
495	uint64_t u12Available : 12;
496	} EPTPML4EBITS;
497	AssertCompileSize(EPTPML4EBITS, 8);
498
499	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
500	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
501	/** The page shift to get the PML4 index. */
502	#define EPT_PML4_SHIFT X86_PML4_SHIFT
503	/** The PML4 index mask (apply to a shifted page address). */
504	#define EPT_PML4_MASK X86_PML4_MASK
505
506	/**
507	* EPT PML4E.
508	*/
509	typedef union EPTPML4E
510	{
511	/** Normal view. */
512	EPTPML4EBITS n;
513	/** Unsigned integer view. */
514	X86PGPAEUINT u;
515	/** 64 bit unsigned integer view. */
516	uint64_t au64[1];
517	/** 32 bit unsigned integer view. */
518	uint32_t au32[2];
519	} EPTPML4E;
520	AssertCompileSize(EPTPML4E, 8);
521	/** Pointer to a PML4 table entry. */
522	typedef EPTPML4E *PEPTPML4E;
523	/** Pointer to a const PML4 table entry. */
524	typedef const EPTPML4E *PCEPTPML4E;
525
526	/**
527	* EPT PML4 Table.
528	*/
529	typedef struct EPTPML4
530	{
531	EPTPML4E a[EPT_PG_ENTRIES];
532	} EPTPML4;
533	AssertCompileSize(EPTPML4, 0x1000);
534	/** Pointer to an EPT PML4 Table. */
535	typedef EPTPML4 *PEPTPML4;
536	/** Pointer to a const EPT PML4 Table. */
537	typedef const EPTPML4 *PCEPTPML4;
538
539	/**
540	* EPT Page Directory Pointer Entry. Bit view.
541	*/
542	typedef struct EPTPDPTEBITS
543	{
544	/** Present bit. */
545	uint64_t u1Present : 1;
546	/** Writable bit. */
547	uint64_t u1Write : 1;
548	/** Executable bit. */
549	uint64_t u1Execute : 1;
550	/** Reserved (must be 0). */
551	uint64_t u5Reserved : 5;
552	/** Available for software. */
553	uint64_t u4Available : 4;
554	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
555	uint64_t u40PhysAddr : 40;
556	/** Available for software. */
557	uint64_t u12Available : 12;
558	} EPTPDPTEBITS;
559	AssertCompileSize(EPTPDPTEBITS, 8);
560
561	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
562	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
563	/** The page shift to get the PDPT index. */
564	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
565	/** The PDPT index mask (apply to a shifted page address). */
566	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
567
568	/**
569	* EPT Page Directory Pointer.
570	*/
571	typedef union EPTPDPTE
572	{
573	/** Normal view. */
574	EPTPDPTEBITS n;
575	/** Unsigned integer view. */
576	X86PGPAEUINT u;
577	/** 64 bit unsigned integer view. */
578	uint64_t au64[1];
579	/** 32 bit unsigned integer view. */
580	uint32_t au32[2];
581	} EPTPDPTE;
582	AssertCompileSize(EPTPDPTE, 8);
583	/** Pointer to an EPT Page Directory Pointer Entry. */
584	typedef EPTPDPTE *PEPTPDPTE;
585	/** Pointer to a const EPT Page Directory Pointer Entry. */
586	typedef const EPTPDPTE *PCEPTPDPTE;
587
588	/**
589	* EPT Page Directory Pointer Table.
590	*/
591	typedef struct EPTPDPT
592	{
593	EPTPDPTE a[EPT_PG_ENTRIES];
594	} EPTPDPT;
595	AssertCompileSize(EPTPDPT, 0x1000);
596	/** Pointer to an EPT Page Directory Pointer Table. */
597	typedef EPTPDPT *PEPTPDPT;
598	/** Pointer to a const EPT Page Directory Pointer Table. */
599	typedef const EPTPDPT *PCEPTPDPT;
600
601
602	/**
603	* EPT Page Directory Table Entry. Bit view.
604	*/
605	typedef struct EPTPDEBITS
606	{
607	/** Present bit. */
608	uint64_t u1Present : 1;
609	/** Writable bit. */
610	uint64_t u1Write : 1;
611	/** Executable bit. */
612	uint64_t u1Execute : 1;
613	/** Reserved (must be 0). */
614	uint64_t u4Reserved : 4;
615	/** Big page (must be 0 here). */
616	uint64_t u1Size : 1;
617	/** Available for software. */
618	uint64_t u4Available : 4;
619	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
620	uint64_t u40PhysAddr : 40;
621	/** Available for software. */
622	uint64_t u12Available : 12;
623	} EPTPDEBITS;
624	AssertCompileSize(EPTPDEBITS, 8);
625
626	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
627	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
628	/** The page shift to get the PD index. */
629	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
630	/** The PD index mask (apply to a shifted page address). */
631	#define EPT_PD_MASK X86_PD_PAE_MASK
632
633	/**
634	* EPT 2MB Page Directory Table Entry. Bit view.
635	*/
636	typedef struct EPTPDE2MBITS
637	{
638	/** Present bit. */
639	uint64_t u1Present : 1;
640	/** Writable bit. */
641	uint64_t u1Write : 1;
642	/** Executable bit. */
643	uint64_t u1Execute : 1;
644	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
645	uint64_t u3EMT : 3;
646	/** Ignore PAT memory type */
647	uint64_t u1IgnorePAT : 1;
648	/** Big page (must be 1 here). */
649	uint64_t u1Size : 1;
650	/** Available for software. */
651	uint64_t u4Available : 4;
652	/** Reserved (must be 0). */
653	uint64_t u9Reserved : 9;
654	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
655	uint64_t u31PhysAddr : 31;
656	/** Available for software. */
657	uint64_t u12Available : 12;
658	} EPTPDE2MBITS;
659	AssertCompileSize(EPTPDE2MBITS, 8);
660
661	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
662	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
663
664	/**
665	* EPT Page Directory Table Entry.
666	*/
667	typedef union EPTPDE
668	{
669	/** Normal view. */
670	EPTPDEBITS n;
671	/** 2MB view (big). */
672	EPTPDE2MBITS b;
673	/** Unsigned integer view. */
674	X86PGPAEUINT u;
675	/** 64 bit unsigned integer view. */
676	uint64_t au64[1];
677	/** 32 bit unsigned integer view. */
678	uint32_t au32[2];
679	} EPTPDE;
680	AssertCompileSize(EPTPDE, 8);
681	/** Pointer to an EPT Page Directory Table Entry. */
682	typedef EPTPDE *PEPTPDE;
683	/** Pointer to a const EPT Page Directory Table Entry. */
684	typedef const EPTPDE *PCEPTPDE;
685
686	/**
687	* EPT Page Directory Table.
688	*/
689	typedef struct EPTPD
690	{
691	EPTPDE a[EPT_PG_ENTRIES];
692	} EPTPD;
693	AssertCompileSize(EPTPD, 0x1000);
694	/** Pointer to an EPT Page Directory Table. */
695	typedef EPTPD *PEPTPD;
696	/** Pointer to a const EPT Page Directory Table. */
697	typedef const EPTPD *PCEPTPD;
698
699
700	/**
701	* EPT Page Table Entry. Bit view.
702	*/
703	typedef struct EPTPTEBITS
704	{
705	/** 0 - Present bit.
706	* @remark This is a convenience "misnomer". The bit actually indicates
707	* read access and the CPU will consider an entry with any of the
708	* first three bits set as present. Since all our valid entries
709	* will have this bit set, it can be used as a present indicator
710	* and allow some code sharing. */
711	uint64_t u1Present : 1;
712	/** 1 - Writable bit. */
713	uint64_t u1Write : 1;
714	/** 2 - Executable bit. */
715	uint64_t u1Execute : 1;
716	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
717	uint64_t u3EMT : 3;
718	/** 6 - Ignore PAT memory type */
719	uint64_t u1IgnorePAT : 1;
720	/** 11:7 - Available for software. */
721	uint64_t u5Available : 5;
722	/** 51:12 - Physical address of page. Restricted by maximum physical
723	* address width of the cpu. */
724	uint64_t u40PhysAddr : 40;
725	/** 63:52 - Available for software. */
726	uint64_t u12Available : 12;
727	} EPTPTEBITS;
728	AssertCompileSize(EPTPTEBITS, 8);
729
730	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
731	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
732	/** The page shift to get the EPT PTE index. */
733	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
734	/** The EPT PT index mask (apply to a shifted page address). */
735	#define EPT_PT_MASK X86_PT_PAE_MASK
736
737	/**
738	* EPT Page Table Entry.
739	*/
740	typedef union EPTPTE
741	{
742	/** Normal view. */
743	EPTPTEBITS n;
744	/** Unsigned integer view. */
745	X86PGPAEUINT u;
746	/** 64 bit unsigned integer view. */
747	uint64_t au64[1];
748	/** 32 bit unsigned integer view. */
749	uint32_t au32[2];
750	} EPTPTE;
751	AssertCompileSize(EPTPTE, 8);
752	/** Pointer to an EPT Page Directory Table Entry. */
753	typedef EPTPTE *PEPTPTE;
754	/** Pointer to a const EPT Page Directory Table Entry. */
755	typedef const EPTPTE *PCEPTPTE;
756
757	/**
758	* EPT Page Table.
759	*/
760	typedef struct EPTPT
761	{
762	EPTPTE a[EPT_PG_ENTRIES];
763	} EPTPT;
764	AssertCompileSize(EPTPT, 0x1000);
765	/** Pointer to an extended page table. */
766	typedef EPTPT *PEPTPT;
767	/** Pointer to a const extended table. */
768	typedef const EPTPT *PCEPTPT;
769
770	/** @} */
771
772	/** VMX VPID flush types.
773	* Warning!! Valid enum members are in accordance to the VT-x spec.
774	*/
775	typedef enum
776	{
777	/** Invalidate a specific page. */
778	VMXFLUSHVPID_INDIV_ADDR = 0,
779	/** Invalidate one context (specific VPID). */
780	VMXFLUSHVPID_SINGLE_CONTEXT = 1,
781	/** Invalidate all contexts (all VPIDs). */
782	VMXFLUSHVPID_ALL_CONTEXTS = 2,
783	/** Invalidate a single VPID context retaining global mappings. */
784	VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
785	/** Unsupported by VirtualBox. */
786	VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
787	/** Unsupported by CPU. */
788	VMXFLUSHVPID_NONE = 0xbad1
789	} VMXFLUSHVPID;
790	AssertCompileSize(VMXFLUSHVPID, 4);
791
792	/** VMX EPT flush types.
793	* @note Warning!! Valid enums values below are in accordance to the VT-x spec.
794	*/
795	typedef enum
796	{
797	/** Invalidate one context (specific EPT). */
798	VMXFLUSHEPT_SINGLE_CONTEXT = 1,
799	/* Invalidate all contexts (all EPTs) */
800	VMXFLUSHEPT_ALL_CONTEXTS = 2,
801	/** Unsupported by VirtualBox. */
802	VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
803	/** Unsupported by CPU. */
804	VMXFLUSHEPT_NONE = 0xbad1
805	} VMXFLUSHEPT;
806	AssertCompileSize(VMXFLUSHEPT, 4);
807
808	/** VMX MSR autoload/store element.
809	* In accordance to VT-x spec.
810	*/
811	typedef struct
812	{
813	/** The MSR Id. */
814	uint32_t u32Msr;
815	/** Reserved (MBZ). */
816	uint32_t u32Reserved;
817	/** The MSR value. */
818	uint64_t u64Value;
819	} VMXAUTOMSR;
820	AssertCompileSize(VMXAUTOMSR, 16);
821	/** Pointer to an MSR load/store element. */
822	typedef VMXAUTOMSR *PVMXAUTOMSR;
823	/** Pointer to a const MSR load/store element. */
824	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
825
826	/**
827	* VMX-capability qword
828	*/
829	typedef union
830	{
831	struct
832	{
833	/** Bits set here -must- be set in the corresponding VM-execution controls. */
834	uint32_t disallowed0;
835	/** Bits cleared here -must- be cleared in the corresponding VM-execution
836	* controls. */
837	uint32_t allowed1;
838	} n;
839	uint64_t u;
840	} VMXCAPABILITY;
841	AssertCompileSize(VMXCAPABILITY, 8);
842
843	/**
844	* VMX MSRs.
845	*/
846	typedef struct VMXMSRS
847	{
848	uint64_t u64FeatureCtrl;
849	uint64_t u64BasicInfo;
850	VMXCAPABILITY VmxPinCtls;
851	VMXCAPABILITY VmxProcCtls;
852	VMXCAPABILITY VmxProcCtls2;
853	VMXCAPABILITY VmxExit;
854	VMXCAPABILITY VmxEntry;
855	uint64_t u64Misc;
856	uint64_t u64Cr0Fixed0;
857	uint64_t u64Cr0Fixed1;
858	uint64_t u64Cr4Fixed0;
859	uint64_t u64Cr4Fixed1;
860	uint64_t u64VmcsEnum;
861	uint64_t u64Vmfunc;
862	uint64_t u64EptVpidCaps;
863	} VMXMSRS;
864	AssertCompileSizeAlignment(VMXMSRS, 8);
865	/** Pointer to a VMXMSRS struct. */
866	typedef VMXMSRS *PVMXMSRS;
867
868	/** @name VMX EFLAGS reserved bits.
869	* @{
870	*/
871	/** And-mask for setting reserved bits to zero */
872	#define VMX_EFLAGS_RESERVED_0 (X86_EFL_1 \| X86_EFL_LIVE_MASK)
873	/** Or-mask for setting reserved bits to 1 */
874	#define VMX_EFLAGS_RESERVED_1 X86_EFL_1
875	/** @} */
876
877	/** @name VMX Basic Exit Reasons.
878	* @{
879	*/
880	/** -1 Invalid exit code */
881	#define VMX_EXIT_INVALID -1
882	/** 0 Exception or non-maskable interrupt (NMI). */
883	#define VMX_EXIT_XCPT_OR_NMI 0
884	/** 1 External interrupt. */
885	#define VMX_EXIT_EXT_INT 1
886	/** 2 Triple fault. */
887	#define VMX_EXIT_TRIPLE_FAULT 2
888	/** 3 INIT signal. */
889	#define VMX_EXIT_INIT_SIGNAL 3
890	/** 4 Start-up IPI (SIPI). */
891	#define VMX_EXIT_SIPI 4
892	/** 5 I/O system-management interrupt (SMI). */
893	#define VMX_EXIT_IO_SMI 5
894	/** 6 Other SMI. */
895	#define VMX_EXIT_SMI 6
896	/** 7 Interrupt window exiting. */
897	#define VMX_EXIT_INT_WINDOW 7
898	/** 8 NMI window exiting. */
899	#define VMX_EXIT_NMI_WINDOW 8
900	/** 9 Task switch. */
901	#define VMX_EXIT_TASK_SWITCH 9
902	/** 10 Guest software attempted to execute CPUID. */
903	#define VMX_EXIT_CPUID 10
904	/** 11 Guest software attempted to execute GETSEC. */
905	#define VMX_EXIT_GETSEC 11
906	/** 12 Guest software attempted to execute HLT. */
907	#define VMX_EXIT_HLT 12
908	/** 13 Guest software attempted to execute INVD. */
909	#define VMX_EXIT_INVD 13
910	/** 14 Guest software attempted to execute INVLPG. */
911	#define VMX_EXIT_INVLPG 14
912	/** 15 Guest software attempted to execute RDPMC. */
913	#define VMX_EXIT_RDPMC 15
914	/** 16 Guest software attempted to execute RDTSC. */
915	#define VMX_EXIT_RDTSC 16
916	/** 17 Guest software attempted to execute RSM in SMM. */
917	#define VMX_EXIT_RSM 17
918	/** 18 Guest software executed VMCALL. */
919	#define VMX_EXIT_VMCALL 18
920	/** 19 Guest software executed VMCLEAR. */
921	#define VMX_EXIT_VMCLEAR 19
922	/** 20 Guest software executed VMLAUNCH. */
923	#define VMX_EXIT_VMLAUNCH 20
924	/** 21 Guest software executed VMPTRLD. */
925	#define VMX_EXIT_VMPTRLD 21
926	/** 22 Guest software executed VMPTRST. */
927	#define VMX_EXIT_VMPTRST 22
928	/** 23 Guest software executed VMREAD. */
929	#define VMX_EXIT_VMREAD 23
930	/** 24 Guest software executed VMRESUME. */
931	#define VMX_EXIT_VMRESUME 24
932	/** 25 Guest software executed VMWRITE. */
933	#define VMX_EXIT_VMWRITE 25
934	/** 26 Guest software executed VMXOFF. */
935	#define VMX_EXIT_VMXOFF 26
936	/** 27 Guest software executed VMXON. */
937	#define VMX_EXIT_VMXON 27
938	/** 28 Control-register accesses. */
939	#define VMX_EXIT_MOV_CRX 28
940	/** 29 Debug-register accesses. */
941	#define VMX_EXIT_MOV_DRX 29
942	/** 30 I/O instruction. */
943	#define VMX_EXIT_IO_INSTR 30
944	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
945	#define VMX_EXIT_RDMSR 31
946	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
947	#define VMX_EXIT_WRMSR 32
948	/** 33 VM-entry failure due to invalid guest state. */
949	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
950	/** 34 VM-entry failure due to MSR loading. */
951	#define VMX_EXIT_ERR_MSR_LOAD 34
952	/** 36 Guest software executed MWAIT. */
953	#define VMX_EXIT_MWAIT 36
954	/** 37 VM-exit due to monitor trap flag. */
955	#define VMX_EXIT_MTF 37
956	/** 39 Guest software attempted to execute MONITOR. */
957	#define VMX_EXIT_MONITOR 39
958	/** 40 Guest software attempted to execute PAUSE. */
959	#define VMX_EXIT_PAUSE 40
960	/** 41 VM-entry failure due to machine-check. */
961	#define VMX_EXIT_ERR_MACHINE_CHECK 41
962	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
963	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
964	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
965	#define VMX_EXIT_APIC_ACCESS 44
966	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
967	#define VMX_EXIT_XDTR_ACCESS 46
968	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
969	#define VMX_EXIT_TR_ACCESS 47
970	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
971	#define VMX_EXIT_EPT_VIOLATION 48
972	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
973	#define VMX_EXIT_EPT_MISCONFIG 49
974	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
975	#define VMX_EXIT_INVEPT 50
976	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
977	#define VMX_EXIT_RDTSCP 51
978	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
979	#define VMX_EXIT_PREEMPT_TIMER 52
980	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
981	#define VMX_EXIT_INVVPID 53
982	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
983	#define VMX_EXIT_WBINVD 54
984	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
985	#define VMX_EXIT_XSETBV 55
986	/** 56 APIC write. Guest completed write to virtual-APIC. */
987	#define VMX_EXIT_APIC_WRITE 56
988	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
989	#define VMX_EXIT_RDRAND 57
990	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
991	#define VMX_EXIT_INVPCID 58
992	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
993	#define VMX_EXIT_VMFUNC 59
994	/** 60 ??? */
995	#define VMX_EXIT_RESERVED_60 60
996	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
997	* enabled. */
998	#define VMX_EXIT_RDSEED 61
999	/** 62 ??? */
1000	#define VMX_EXIT_RESERVED_62 62
1001	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1002	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1003	#define VMX_EXIT_XSAVES 63
1004	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1005	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1006	#define VMX_EXIT_XRSTORS 64
1007	/** The maximum exit value (inclusive). */
1008	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1009	/** @} */
1010
1011
1012	/** @name VM Instruction Errors
1013	* @{
1014	*/
1015	/** VMCALL executed in VMX root operation. */
1016	#define VMX_ERROR_VMCALL 1
1017	/** VMCLEAR with invalid physical address. */
1018	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1019	/** VMCLEAR with VMXON pointer. */
1020	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1021	/** VMLAUNCH with non-clear VMCS. */
1022	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1023	/** VMRESUME with non-launched VMCS. */
1024	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1025	/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1026	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1027	/** VM-entry with invalid control field(s). */
1028	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1029	/** VM-entry with invalid host-state field(s). */
1030	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1031	/** VMPTRLD with invalid physical address. */
1032	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1033	/** VMPTRLD with VMXON pointer. */
1034	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1035	/** VMPTRLD with incorrect VMCS revision identifier. */
1036	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1037	/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1038	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1039	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1040	/** VMWRITE to read-only VMCS component. */
1041	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1042	/** VMXON executed in VMX root operation. */
1043	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1044	/** VM-entry with invalid executive-VMCS pointer. */
1045	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1046	/** VM-entry with non-launched executive VMCS. */
1047	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1048	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1049	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1050	/** VMCALL with non-clear VMCS. */
1051	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1052	/** VMCALL with invalid VM-exit control fields. */
1053	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1054	/** VMCALL with incorrect MSEG revision identifier. */
1055	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1056	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1057	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1058	/** VMCALL with invalid SMM-monitor features. */
1059	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1060	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1061	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1062	/** VM-entry with events blocked by MOV SS. */
1063	#define VMX_ERROR_VMENTRY_MOV_SS 26
1064	/** Invalid operand to INVEPT/INVVPID. */
1065	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1066	/** @} */
1067
1068
1069	/** @name VMX MSRs - Basic VMX information.
1070	* @{
1071	*/
1072	/** VMCS revision identifier used by the processor. */
1073	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1074	/** Size of the VMCS. */
1075	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1076	/** Width of physical address used for the VMCS.
1077	* 0 -> limited to the available amount of physical ram
1078	* 1 -> within the first 4 GB
1079	*/
1080	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1081	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1082	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1083	/** Memory type that must be used for the VMCS. */
1084	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1085	/** Whether the processor provides additional information for exits due to INS/OUTS. */
1086	#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1087	/** @} */
1088
1089
1090	/** @name VMX MSRs - Misc VMX info.
1091	* @{
1092	*/
1093	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1094	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1095	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1096	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1097	/** Activity states supported by the implementation. */
1098	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1099	/** Number of CR3 target values supported by the processor. (0-256) */
1100	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1101	/** Maximum number of MSRs in the VMCS. (N+1)512. /
1102	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1103	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1104	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1105	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1106	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1107	/** Whether VMWRITE can be used to write VM-exit information fields. */
1108	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1109	/** MSEG revision identifier used by the processor. */
1110	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1111	/** @} */
1112
1113
1114	/** @name VMX MSRs - VMCS enumeration field info
1115	* @{
1116	*/
1117	/** Highest field index. */
1118	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1119	/** @} */
1120
1121
1122	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1123	* @{
1124	*/
1125	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1126	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1127	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1128	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1129	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1130	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1131	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1132	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1133	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1134	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1135	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1136	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1137	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1138	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1139	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1140	/** @} */
1141
1142	/** @name Extended Page Table Pointer (EPTP)
1143	* @{
1144	*/
1145	/** Uncachable EPT paging structure memory type. */
1146	#define VMX_EPT_MEMTYPE_UC 0
1147	/** Write-back EPT paging structure memory type. */
1148	#define VMX_EPT_MEMTYPE_WB 6
1149	/** Shift value to get the EPT page walk length (bits 5-3) */
1150	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1151	/** Mask value to get the EPT page walk length (bits 5-3) */
1152	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1153	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1154	* length) */
1155	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1156	/** @} */
1157
1158
1159	/** @name VMCS field encoding - 16 bits guest fields
1160	* @{
1161	*/
1162	#define VMX_VMCS16_VPID 0x000
1163	#define VMX_VMCS16_POSTED_INTR_NOTIFY_VECTOR 0x002
1164	#define VMX_VMCS16_EPTP_INDEX 0x004
1165	#define VMX_VMCS16_GUEST_ES_SEL 0x800
1166	#define VMX_VMCS16_GUEST_CS_SEL 0x802
1167	#define VMX_VMCS16_GUEST_SS_SEL 0x804
1168	#define VMX_VMCS16_GUEST_DS_SEL 0x806
1169	#define VMX_VMCS16_GUEST_FS_SEL 0x808
1170	#define VMX_VMCS16_GUEST_GS_SEL 0x80A
1171	#define VMX_VMCS16_GUEST_LDTR_SEL 0x80C
1172	#define VMX_VMCS16_GUEST_TR_SEL 0x80E
1173	#define VMX_VMCS16_GUEST_INTR_STATUS 0x810
1174	/** @} */
1175
1176	/** @name VMCS field encoding - 16 bits host fields
1177	* @{
1178	*/
1179	#define VMX_VMCS16_HOST_ES_SEL 0xC00
1180	#define VMX_VMCS16_HOST_CS_SEL 0xC02
1181	#define VMX_VMCS16_HOST_SS_SEL 0xC04
1182	#define VMX_VMCS16_HOST_DS_SEL 0xC06
1183	#define VMX_VMCS16_HOST_FS_SEL 0xC08
1184	#define VMX_VMCS16_HOST_GS_SEL 0xC0A
1185	#define VMX_VMCS16_HOST_TR_SEL 0xC0C
1186	/** @} */
1187
1188	/** @name VMCS field encoding - 64 bits host fields
1189	* @{
1190	*/
1191	#define VMX_VMCS64_HOST_PAT_FULL 0x2C00
1192	#define VMX_VMCS64_HOST_PAT_HIGH 0x2C01
1193	#define VMX_VMCS64_HOST_EFER_FULL 0x2C02
1194	#define VMX_VMCS64_HOST_EFER_HIGH 0x2C03
1195	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
1196	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
1197	/** @} */
1198
1199
1200	/** @name VMCS field encoding - 64 Bits control fields
1201	* @{
1202	*/
1203	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1204	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1205	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1206	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1207
1208	/* Optional */
1209	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1210	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1211
1212	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1213	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1214	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1215	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1216
1217	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1218	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1219
1220	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1221	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1222
1223	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1224	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1225
1226	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1227	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1228	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1229
1230	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1231	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1232	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1233
1234	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1235	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1236	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1237
1238	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1239	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1240	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1241
1242	/** Extended page table pointer. */
1243	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201A
1244	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201B
1245
1246	/** EOI-exit bitmap 0. */
1247	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201C
1248	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201D
1249
1250	/** EOI-exit bitmap 1. */
1251	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201E
1252	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201F
1253
1254	/** EOI-exit bitmap 2. */
1255	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1256	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1257
1258	/** EOI-exit bitmap 3. */
1259	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1260	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1261
1262	/** Extended page table pointer lists. */
1263	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1264	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1265
1266	/** VM-read bitmap. */
1267	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1268	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1269
1270	/** VM-write bitmap. */
1271	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1272	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1273
1274	/** Virtualization-exception information address. */
1275	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202A
1276	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202B
1277
1278	/** XSS-exiting bitmap. */
1279	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202C
1280	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202D
1281
1282	/** TSC multiplier. */
1283	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1284	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1285
1286	/** VM-exit guest physical address. */
1287	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1288	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1289	/** @} */
1290
1291
1292	/** @name VMCS field encoding - 64 Bits guest fields
1293	* @{
1294	*/
1295	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1296	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1297	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
1298	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
1299	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1300	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1301	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1302	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1303	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
1304	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
1305	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1306	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1307	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1308	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1309	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1310	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1311	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1312	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1313	/** @} */
1314
1315
1316	/** @name VMCS field encoding - 32 Bits control fields
1317	* @{
1318	*/
1319	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1320	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1321	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1322	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1323	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1324	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1325	#define VMX_VMCS32_CTRL_EXIT 0x400C
1326	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1327	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1328	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1329	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1330	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1331	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1332	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1333	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1334	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1335	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1336	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1337	/** @} */
1338
1339
1340	/** @name VMX_VMCS_CTRL_PIN_EXEC
1341	* @{
1342	*/
1343	/** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1344	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1345	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1346	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1347	/** Virtual NMIs. */
1348	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1349	/** Activate VMX preemption timer. */
1350	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1351	/** Process interrupts with the posted-interrupt notification vector. */
1352	#define VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR RT_BIT(7)
1353	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1354	/** @} */
1355
1356	/** @name VMX_VMCS_CTRL_PROC_EXEC
1357	* @{
1358	*/
1359	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1360	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1361	/** Use timestamp counter offset. */
1362	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1363	/** VM-exit when executing the HLT instruction. */
1364	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1365	/** VM-exit when executing the INVLPG instruction. */
1366	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1367	/** VM-exit when executing the MWAIT instruction. */
1368	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1369	/** VM-exit when executing the RDPMC instruction. */
1370	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1371	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1372	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1373	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1374	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1375	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1376	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1377	/** VM-exit on CR8 loads. */
1378	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1379	/** VM-exit on CR8 stores. */
1380	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1381	/** Use TPR shadow. */
1382	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1383	/** VM-exit when virtual NMI blocking is disabled. */
1384	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1385	/** VM-exit when executing a MOV DRx instruction. */
1386	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1387	/** VM-exit when executing IO instructions. */
1388	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1389	/** Use IO bitmaps. */
1390	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1391	/** Monitor trap flag. */
1392	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1393	/** Use MSR bitmaps. */
1394	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1395	/** VM-exit when executing the MONITOR instruction. */
1396	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1397	/** VM-exit when executing the PAUSE instruction. */
1398	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1399	/** Determines whether the secondary processor based VM-execution controls are used. */
1400	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1401	/** @} */
1402
1403	/** @name VMX_VMCS_CTRL_PROC_EXEC2
1404	* @{
1405	*/
1406	/** Virtualize APIC access. */
1407	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1408	/** EPT supported/enabled. */
1409	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1410	/** Descriptor table instructions cause VM-exits. */
1411	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1412	/** RDTSCP supported/enabled. */
1413	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1414	/** Virtualize x2APIC mode. */
1415	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1416	/** VPID supported/enabled. */
1417	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1418	/** VM-exit when executing the WBINVD instruction. */
1419	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1420	/** Unrestricted guest execution. */
1421	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1422	/** A specified number of pause loops cause a VM-exit. */
1423	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1424	/** VM-exit when executing RDRAND instructions. */
1425	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1426	/** Enables INVPCID instructions. */
1427	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1428	/** Enables VMFUNC instructions. */
1429	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1430	/** Enables VMCS shadowing. */
1431	#define VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING RT_BIT_64(14)
1432	/** VM-exit when executing RDSEED. */
1433	#define VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT RT_BIT_64(16)
1434	/** Controls whether EPT-violations may cause \#VE instead of exits. */
1435	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE RT_BIT_64(18)
1436	/** Enables XSAVES/XRSTORS instructions. */
1437	#define VMX_VMCS_CTRL_PROC_EXEC2_XSAVES RT_BIT_64(20)
1438
1439	/** @} */
1440
1441
1442	/** @name VMX_VMCS_CTRL_ENTRY
1443	* @{
1444	*/
1445	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1446	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1447	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1448	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1449	/** In SMM mode after VM-entry. */
1450	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1451	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1452	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1453	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1454	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1455	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1456	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1457	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1458	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1459	/** @} */
1460
1461
1462	/** @name VMX_VMCS_CTRL_EXIT
1463	* @{
1464	*/
1465	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1466	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1467	/** Return to long mode after a VM-exit. */
1468	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1469	/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1470	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1471	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1472	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1473	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1474	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1475	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1476	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1477	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1478	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1479	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1480	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1481	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1482	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1483	/** @} */
1484
1485
1486	/** @name VMX_VMCS_CTRL_VMFUNC
1487	* @{
1488	*/
1489	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1490	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1491	/** @} */
1492
1493
1494	/** @name VMCS field encoding - 32 Bits read-only fields
1495	* @{
1496	*/
1497	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1498	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1499	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1500	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1501	#define VMX_VMCS32_RO_IDT_INFO 0x4408
1502	#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1503	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1504	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1505	/** @} */
1506
1507	/** @name VMX_VMCS32_RO_EXIT_REASON
1508	* @{
1509	*/
1510	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1511	/** @} */
1512
1513	/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1514	* @{
1515	*/
1516	#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1517	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1518	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1519	/** @} */
1520
1521
1522	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1523	* @{
1524	*/
1525	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1526	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1527	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1528	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1529	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1530	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(a) ((a) & RT_BIT(12))
1531	#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1532	#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1533	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1534	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1535	/** @} */
1536
1537	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1538	* @{
1539	*/
1540	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1541	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1542	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1543	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1544	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1545	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1546	/** @} */
1547
1548	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1549	* @{
1550	*/
1551	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1552	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1553	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1554	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1555	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1556	#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1557	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1558	/** @} */
1559
1560	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1561	* @{
1562	*/
1563	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1564	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1565	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1566	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1567	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1568	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1569	/** @} */
1570
1571
1572	/** @name VMCS field encoding - 32 Bits guest state fields
1573	* @{
1574	*/
1575	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1576	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1577	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1578	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1579	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1580	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1581	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1582	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1583	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1584	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1585	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1586	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1587	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1588	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1589	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1590	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1591	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1592	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1593	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1594	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1595	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1596	#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1597	/** @} */
1598
1599
1600	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1601	* @{
1602	*/
1603	/** The logical processor is active. */
1604	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1605	/** The logical processor is inactive, because executed a HLT instruction. */
1606	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1607	/** The logical processor is inactive, because of a triple fault or other serious error. */
1608	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1609	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1610	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1611	/** @} */
1612
1613
1614	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1615	* @{
1616	*/
1617	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1618	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1619	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1620	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1621	/** @} */
1622
1623
1624	/** @name VMCS field encoding - 32 Bits host state fields
1625	* @{
1626	*/
1627	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1628	/** @} */
1629
1630	/** @name Natural width control fields
1631	* @{
1632	*/
1633	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1634	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1635	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1636	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1637	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1638	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1639	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1640	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1641	/** @} */
1642
1643
1644	/** @name Natural width read-only data fields
1645	* @{
1646	*/
1647	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1648	#define VMX_VMCS_RO_IO_RCX 0x6402
1649	#define VMX_VMCS_RO_IO_RSX 0x6404
1650	#define VMX_VMCS_RO_IO_RDI 0x6406
1651	#define VMX_VMCS_RO_IO_RIP 0x6408
1652	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1653	/** @} */
1654
1655
1656	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1657	* @{
1658	*/
1659	/** 0-2: Debug register number */
1660	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1661	/** 3: Reserved; cleared to 0. */
1662	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1663	/** 4: Direction of move (0 = write, 1 = read) */
1664	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1665	/** 5-7: Reserved; cleared to 0. */
1666	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1667	/** 8-11: General purpose register number. */
1668	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1669	/** Rest: reserved. */
1670	/** @} */
1671
1672	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1673	* @{
1674	*/
1675	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1676	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1677	/** @} */
1678
1679
1680
1681	/** @name CRx accesses
1682	* @{
1683	*/
1684	/** 0-3: Control register number (0 for CLTS & LMSW) */
1685	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1686	/** 4-5: Access type. */
1687	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1688	/** 6: LMSW operand type */
1689	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1690	/** 7: Reserved; cleared to 0. */
1691	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1692	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1693	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1694	/** 12-15: Reserved; cleared to 0. */
1695	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1696	/** 16-31: LMSW source data (else 0). */
1697	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1698	/* Rest: reserved. */
1699	/** @} */
1700
1701	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1702	* @{
1703	*/
1704	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1705	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1706	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1707	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1708	/** @} */
1709
1710	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1711	* @{
1712	*/
1713	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1714	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1715	/** Task switch caused by a call instruction. */
1716	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1717	/** Task switch caused by an iret instruction. */
1718	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1719	/** Task switch caused by a jmp instruction. */
1720	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1721	/** Task switch caused by an interrupt gate. */
1722	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1723	/** @} */
1724
1725
1726	/** @name VMX_EXIT_EPT_VIOLATION
1727	* @{
1728	*/
1729	/** Set if the violation was caused by a data read. */
1730	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1731	/** Set if the violation was caused by a data write. */
1732	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1733	/** Set if the violation was caused by an instruction fetch. */
1734	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1735	/** AND of the present bit of all EPT structures. */
1736	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1737	/** AND of the write bit of all EPT structures. */
1738	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1739	/** AND of the execute bit of all EPT structures. */
1740	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1741	/** Set if the guest linear address field contains the faulting address. */
1742	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1743	/** If bit 7 is one: (reserved otherwise)
1744	* 1 - violation due to physical address access.
1745	* 0 - violation caused by page walk or access/dirty bit updates
1746	*/
1747	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1748	/** @} */
1749
1750
1751	/** @name VMX_EXIT_PORT_IO
1752	* @{
1753	*/
1754	/** 0-2: IO operation width. */
1755	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1756	/** 3: IO operation direction. */
1757	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1758	/** 4: String IO operation (INS / OUTS). */
1759	#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1760	/** 5: Repeated IO operation. */
1761	#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1762	/** 6: Operand encoding. */
1763	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1764	/** 16-31: IO Port (0-0xffff). */
1765	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1766	/* Rest reserved. */
1767	/** @} */
1768
1769	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1770	* @{
1771	*/
1772	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1773	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1774	/** @} */
1775
1776
1777	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1778	* @{
1779	*/
1780	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1781	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1782	/** @} */
1783
1784	/** @name VMX_EXIT_APIC_ACCESS
1785	* @{
1786	*/
1787	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
1788	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1789	/** 12-15: Access type. */
1790	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
1791	/* Rest reserved. */
1792	/** @} */
1793
1794
1795	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE return values
1796	* @{
1797	*/
1798	/** Linear read access. */
1799	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1800	/** Linear write access. */
1801	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1802	/** Linear instruction fetch access. */
1803	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1804	/** Linear read/write access during event delivery. */
1805	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1806	/** Physical read/write access during event delivery. */
1807	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1808	/** Physical access for an instruction fetch or during instruction execution. */
1809	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1810	/** @} */
1811
1812	/** @name VMX_XDTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information
1813	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1814	* @{
1815	*/
1816	/** Address calculation scaling field (powers of two). */
1817	#define VMX_XDTR_INSINFO_SCALE_SHIFT 0
1818	#define VMX_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1819	/** Bits 2 thru 6 are undefined. */
1820	#define VMX_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
1821	#define VMX_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
1822	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1823	* @remarks anyone's guess why this is a 3 bit field... */
1824	#define VMX_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
1825	#define VMX_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1826	/** Bit 10 is defined as zero. */
1827	#define VMX_XDTR_INSINFO_ZERO_10_SHIFT 10
1828	#define VMX_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
1829	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
1830	* for exits from 64-bit code as the operand size there is fixed. */
1831	#define VMX_XDTR_INSINFO_OP_SIZE_SHIFT 11
1832	#define VMX_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
1833	/** Bits 12 thru 14 are undefined. */
1834	#define VMX_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
1835	#define VMX_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
1836	/** Applicable segment register (X86_SREG_XXX values). */
1837	#define VMX_XDTR_INSINFO_SREG_SHIFT 15
1838	#define VMX_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1839	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1840	#define VMX_XDTR_INSINFO_INDEX_REG_SHIFT 18
1841	#define VMX_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1842	/** Is VMX_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1843	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1844	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1845	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1846	#define VMX_XDTR_INSINFO_BASE_REG_SHIFT 23
1847	#define VMX_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1848	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1849	#define VMX_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
1850	#define VMX_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1851	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values) */
1852	#define VMX_XDTR_INSINFO_INSTR_ID_SHIFT 28
1853	#define VMX_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1854	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
1855	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
1856	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
1857	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
1858	/** Bits 30 & 31 are undefined. */
1859	#define VMX_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
1860	#define VMX_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1861	RT_BF_ASSERT_COMPILE_CHECKS(VMX_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1862	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
1863	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1864	/** @} */
1865
1866
1867	/** @name VMX_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information
1868	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1869	* This is similar to VMX_XDTR_INSINFO_XXX.
1870	* @{
1871	*/
1872	/** Address calculation scaling field (powers of two). */
1873	#define VMX_YYTR_INSINFO_SCALE_SHIFT 0
1874	#define VMX_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1875	/** Bit 2 is undefined. */
1876	#define VMX_YYTR_INSINFO_UNDEF_2_SHIFT 2
1877	#define VMX_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
1878	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
1879	#define VMX_YYTR_INSINFO_REG1_SHIFT 3
1880	#define VMX_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
1881	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1882	* @remarks anyone's guess why this is a 3 bit field... */
1883	#define VMX_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
1884	#define VMX_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1885	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
1886	#define VMX_YYTR_INSINFO_HAS_REG1_SHIFT 10
1887	#define VMX_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
1888	/** Bits 11 thru 14 are undefined. */
1889	#define VMX_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
1890	#define VMX_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
1891	/** Applicable segment register (X86_SREG_XXX values). */
1892	#define VMX_YYTR_INSINFO_SREG_SHIFT 15
1893	#define VMX_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1894	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1895	#define VMX_YYTR_INSINFO_INDEX_REG_SHIFT 18
1896	#define VMX_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1897	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1898	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1899	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1900	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1901	#define VMX_YYTR_INSINFO_BASE_REG_SHIFT 23
1902	#define VMX_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1903	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1904	#define VMX_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
1905	#define VMX_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1906	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
1907	#define VMX_YYTR_INSINFO_INSTR_ID_SHIFT 28
1908	#define VMX_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1909	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
1910	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
1911	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
1912	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
1913	/** Bits 30 & 31 are undefined. */
1914	#define VMX_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
1915	#define VMX_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1916	RT_BF_ASSERT_COMPILE_CHECKS(VMX_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1917	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
1918	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1919	/** @} */
1920
1921
1922	/** @name VMCS field encoding - Natural width guest state fields
1923	* @{
1924	*/
1925	#define VMX_VMCS_GUEST_CR0 0x6800
1926	#define VMX_VMCS_GUEST_CR3 0x6802
1927	#define VMX_VMCS_GUEST_CR4 0x6804
1928	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1929	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1930	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1931	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1932	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1933	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1934	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1935	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1936	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1937	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1938	#define VMX_VMCS_GUEST_DR7 0x681A
1939	#define VMX_VMCS_GUEST_RSP 0x681C
1940	#define VMX_VMCS_GUEST_RIP 0x681E
1941	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1942	#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1943	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1944	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1945	/** @} */
1946
1947
1948	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1949	* Bits 4-11, 13 and 15-63 are reserved.
1950	* @{
1951	*/
1952	/** Hardware breakpoint 0 was met. */
1953	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1954	/** Hardware breakpoint 1 was met. */
1955	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1956	/** Hardware breakpoint 2 was met. */
1957	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1958	/** Hardware breakpoint 3 was met. */
1959	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1960	/** At least one data or IO breakpoint was hit. */
1961	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1962	/** A debug exception would have been triggered by single-step execution mode. */
1963	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1964	/** @} */
1965
1966	/** @name VMCS field encoding - Natural width host state fields
1967	* @{
1968	*/
1969	#define VMX_VMCS_HOST_CR0 0x6C00
1970	#define VMX_VMCS_HOST_CR3 0x6C02
1971	#define VMX_VMCS_HOST_CR4 0x6C04
1972	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1973	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1974	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1975	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1976	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1977	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1978	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1979	#define VMX_VMCS_HOST_RSP 0x6C14
1980	#define VMX_VMCS_HOST_RIP 0x6C16
1981	/** @} */
1982
1983
1984	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
1985	* @{
1986	*/
1987
1988	/**
1989	* Restores some host-state fields that need not be done on every VM-exit.
1990	*
1991	* @returns VBox status code.
1992	* @param fRestoreHostFlags Flags of which host registers needs to be
1993	* restored.
1994	* @param pRestoreHost Pointer to the host-restore structure.
1995	*/
1996	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1997
1998
1999	/**
2000	* Dispatches an NMI to the host.
2001	*/
2002	DECLASM(int) VMXDispatchHostNmi(void);
2003
2004
2005	/**
2006	* Executes VMXON.
2007	*
2008	* @returns VBox status code.
2009	* @param HCPhysVmxOn Physical address of VMXON structure.
2010	*/
2011	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2012	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
2013	#else
2014	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
2015	{
2016	# if RT_INLINE_ASM_GNU_STYLE
2017	int rc = VINF_SUCCESS;
2018	__asm__ __volatile__ (
2019	"push %3 \n\t"
2020	"push %2 \n\t"
2021	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
2022	"ja 2f \n\t"
2023	"je 1f \n\t"
2024	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
2025	"jmp 2f \n\t"
2026	"1: \n\t"
2027	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
2028	"2: \n\t"
2029	"add $8, %%esp \n\t"
2030	:"=rm"(rc)
2031	:"0"(VINF_SUCCESS),
2032	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
2033	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
2034	:"memory"
2035	);
2036	return rc;
2037
2038	# elif VMX_USE_MSC_INTRINSICS
2039	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
2040	if (RT_LIKELY(rcMsc == 0))
2041	return VINF_SUCCESS;
2042	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
2043
2044	# else
2045	int rc = VINF_SUCCESS;
2046	__asm
2047	{
2048	push dword ptr [HCPhysVmxOn + 4]
2049	push dword ptr [HCPhysVmxOn]
2050	_emit 0xF3
2051	_emit 0x0F
2052	_emit 0xC7
2053	_emit 0x34
2054	_emit 0x24 /* VMXON [esp] */
2055	jnc vmxon_good
2056	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
2057	jmp the_end
2058
2059	vmxon_good:
2060	jnz the_end
2061	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
2062	the_end:
2063	add esp, 8
2064	}
2065	return rc;
2066	# endif
2067	}
2068	#endif
2069
2070
2071	/**
2072	* Executes VMXOFF.
2073	*/
2074	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2075	DECLASM(void) VMXDisable(void);
2076	#else
2077	DECLINLINE(void) VMXDisable(void)
2078	{
2079	# if RT_INLINE_ASM_GNU_STYLE
2080	__asm__ __volatile__ (
2081	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
2082	);
2083
2084	# elif VMX_USE_MSC_INTRINSICS
2085	__vmx_off();
2086
2087	# else
2088	__asm
2089	{
2090	_emit 0x0F
2091	_emit 0x01
2092	_emit 0xC4 /* VMXOFF */
2093	}
2094	# endif
2095	}
2096	#endif
2097
2098
2099	/**
2100	* Executes VMCLEAR.
2101	*
2102	* @returns VBox status code.
2103	* @param HCPhysVmcs Physical address of VM control structure.
2104	*/
2105	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2106	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
2107	#else
2108	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
2109	{
2110	# if RT_INLINE_ASM_GNU_STYLE
2111	int rc = VINF_SUCCESS;
2112	__asm__ __volatile__ (
2113	"push %3 \n\t"
2114	"push %2 \n\t"
2115	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
2116	"jnc 1f \n\t"
2117	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2118	"1: \n\t"
2119	"add $8, %%esp \n\t"
2120	:"=rm"(rc)
2121	:"0"(VINF_SUCCESS),
2122	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2123	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
2124	:"memory"
2125	);
2126	return rc;
2127
2128	# elif VMX_USE_MSC_INTRINSICS
2129	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
2130	if (RT_LIKELY(rcMsc == 0))
2131	return VINF_SUCCESS;
2132	return VERR_VMX_INVALID_VMCS_PTR;
2133
2134	# else
2135	int rc = VINF_SUCCESS;
2136	__asm
2137	{
2138	push dword ptr [HCPhysVmcs + 4]
2139	push dword ptr [HCPhysVmcs]
2140	_emit 0x66
2141	_emit 0x0F
2142	_emit 0xC7
2143	_emit 0x34
2144	_emit 0x24 /* VMCLEAR [esp] */
2145	jnc success
2146	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2147	success:
2148	add esp, 8
2149	}
2150	return rc;
2151	# endif
2152	}
2153	#endif
2154
2155
2156	/**
2157	* Executes VMPTRLD.
2158	*
2159	* @returns VBox status code.
2160	* @param HCPhysVmcs Physical address of VMCS structure.
2161	*/
2162	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2163	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
2164	#else
2165	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
2166	{
2167	# if RT_INLINE_ASM_GNU_STYLE
2168	int rc = VINF_SUCCESS;
2169	__asm__ __volatile__ (
2170	"push %3 \n\t"
2171	"push %2 \n\t"
2172	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2173	"jnc 1f \n\t"
2174	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2175	"1: \n\t"
2176	"add $8, %%esp \n\t"
2177	:"=rm"(rc)
2178	:"0"(VINF_SUCCESS),
2179	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2180	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
2181	);
2182	return rc;
2183
2184	# elif VMX_USE_MSC_INTRINSICS
2185	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
2186	if (RT_LIKELY(rcMsc == 0))
2187	return VINF_SUCCESS;
2188	return VERR_VMX_INVALID_VMCS_PTR;
2189
2190	# else
2191	int rc = VINF_SUCCESS;
2192	__asm
2193	{
2194	push dword ptr [HCPhysVmcs + 4]
2195	push dword ptr [HCPhysVmcs]
2196	_emit 0x0F
2197	_emit 0xC7
2198	_emit 0x34
2199	_emit 0x24 /* VMPTRLD [esp] */
2200	jnc success
2201	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2202
2203	success:
2204	add esp, 8
2205	}
2206	return rc;
2207	# endif
2208	}
2209	#endif
2210
2211	/**
2212	* Executes VMPTRST.
2213	*
2214	* @returns VBox status code.
2215	* @param pHCPhysVmcs Where to store the physical address of the current
2216	* VMCS.
2217	*/
2218	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
2219
2220	/**
2221	* Executes VMWRITE.
2222	*
2223	* @returns VBox status code.
2224	* @retval VINF_SUCCESS.
2225	* @retval VERR_VMX_INVALID_VMCS_PTR.
2226	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2227	*
2228	* @param idxField VMCS index.
2229	* @param u32Val 32-bit value.
2230	*
2231	* @remarks The values of the two status codes can be OR'ed together, the result
2232	* will be VERR_VMX_INVALID_VMCS_PTR.
2233	*/
2234	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2235	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2236	#else
2237	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2238	{
2239	# if RT_INLINE_ASM_GNU_STYLE
2240	int rc = VINF_SUCCESS;
2241	__asm__ __volatile__ (
2242	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2243	"ja 2f \n\t"
2244	"je 1f \n\t"
2245	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2246	"jmp 2f \n\t"
2247	"1: \n\t"
2248	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2249	"2: \n\t"
2250	:"=rm"(rc)
2251	:"0"(VINF_SUCCESS),
2252	"a"(idxField),
2253	"d"(u32Val)
2254	);
2255	return rc;
2256
2257	# elif VMX_USE_MSC_INTRINSICS
2258	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2259	if (RT_LIKELY(rcMsc == 0))
2260	return VINF_SUCCESS;
2261	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2262
2263	#else
2264	int rc = VINF_SUCCESS;
2265	__asm
2266	{
2267	push dword ptr [u32Val]
2268	mov eax, [idxField]
2269	_emit 0x0F
2270	_emit 0x79
2271	_emit 0x04
2272	_emit 0x24 /* VMWRITE eax, [esp] */
2273	jnc valid_vmcs
2274	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2275	jmp the_end
2276
2277	valid_vmcs:
2278	jnz the_end
2279	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2280	the_end:
2281	add esp, 4
2282	}
2283	return rc;
2284	# endif
2285	}
2286	#endif
2287
2288	/**
2289	* Executes VMWRITE.
2290	*
2291	* @returns VBox status code.
2292	* @retval VINF_SUCCESS.
2293	* @retval VERR_VMX_INVALID_VMCS_PTR.
2294	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2295	*
2296	* @param idxField VMCS index.
2297	* @param u64Val 16, 32 or 64-bit value.
2298	*
2299	* @remarks The values of the two status codes can be OR'ed together, the result
2300	* will be VERR_VMX_INVALID_VMCS_PTR.
2301	*/
2302	#if !defined(RT_ARCH_X86)
2303	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
2304	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2305	# else /* VMX_USE_MSC_INTRINSICS */
2306	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2307	{
2308	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2309	if (RT_LIKELY(rcMsc == 0))
2310	return VINF_SUCCESS;
2311	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2312	}
2313	# endif /* VMX_USE_MSC_INTRINSICS */
2314	#else
2315	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2316	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2317	#endif
2318
2319	#if ARCH_BITS == 32
2320	# define VMXWriteVmcsHstN VMXWriteVmcs32
2321	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2322	#else /* ARCH_BITS == 64 */
2323	# define VMXWriteVmcsHstN VMXWriteVmcs64
2324	# define VMXWriteVmcsGstN VMXWriteVmcs64
2325	#endif
2326
2327
2328	/**
2329	* Invalidate a page using INVEPT.
2330	*
2331	* @returns VBox status code.
2332	* @param enmFlush Type of flush.
2333	* @param pDescriptor Pointer to the descriptor.
2334	*/
2335	DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2336
2337	/**
2338	* Invalidate a page using INVVPID.
2339	*
2340	* @returns VBox status code.
2341	* @param enmFlush Type of flush.
2342	* @param pDescriptor Pointer to the descriptor.
2343	*/
2344	DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2345
2346	/**
2347	* Executes VMREAD.
2348	*
2349	* @returns VBox status code.
2350	* @retval VINF_SUCCESS.
2351	* @retval VERR_VMX_INVALID_VMCS_PTR.
2352	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2353	*
2354	* @param idxField VMCS index.
2355	* @param pData Where to store VM field value.
2356	*
2357	* @remarks The values of the two status codes can be OR'ed together, the result
2358	* will be VERR_VMX_INVALID_VMCS_PTR.
2359	*/
2360	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2361	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2362	#else
2363	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2364	{
2365	# if RT_INLINE_ASM_GNU_STYLE
2366	int rc = VINF_SUCCESS;
2367	__asm__ __volatile__ (
2368	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2369	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2370	"ja 2f \n\t"
2371	"je 1f \n\t"
2372	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2373	"jmp 2f \n\t"
2374	"1: \n\t"
2375	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2376	"2: \n\t"
2377	:"=&r"(rc),
2378	"=d"(*pData)
2379	:"a"(idxField),
2380	"d"(0)
2381	);
2382	return rc;
2383
2384	# elif VMX_USE_MSC_INTRINSICS
2385	unsigned char rcMsc;
2386	# if ARCH_BITS == 32
2387	rcMsc = __vmx_vmread(idxField, pData);
2388	# else
2389	uint64_t u64Tmp;
2390	rcMsc = __vmx_vmread(idxField, &u64Tmp);
2391	*pData = (uint32_t)u64Tmp;
2392	# endif
2393	if (RT_LIKELY(rcMsc == 0))
2394	return VINF_SUCCESS;
2395	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2396
2397	#else
2398	int rc = VINF_SUCCESS;
2399	__asm
2400	{
2401	sub esp, 4
2402	mov dword ptr [esp], 0
2403	mov eax, [idxField]
2404	_emit 0x0F
2405	_emit 0x78
2406	_emit 0x04
2407	_emit 0x24 /* VMREAD eax, [esp] */
2408	mov edx, pData
2409	pop dword ptr [edx]
2410	jnc valid_vmcs
2411	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2412	jmp the_end
2413
2414	valid_vmcs:
2415	jnz the_end
2416	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2417	the_end:
2418	}
2419	return rc;
2420	# endif
2421	}
2422	#endif
2423
2424	/**
2425	* Executes VMREAD.
2426	*
2427	* @returns VBox status code.
2428	* @retval VINF_SUCCESS.
2429	* @retval VERR_VMX_INVALID_VMCS_PTR.
2430	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2431	*
2432	* @param idxField VMCS index.
2433	* @param pData Where to store VM field value.
2434	*
2435	* @remarks The values of the two status codes can be OR'ed together, the result
2436	* will be VERR_VMX_INVALID_VMCS_PTR.
2437	*/
2438	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
2439	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2440	#else
2441	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2442	{
2443	# if VMX_USE_MSC_INTRINSICS
2444	unsigned char rcMsc;
2445	# if ARCH_BITS == 32
2446	size_t uLow;
2447	size_t uHigh;
2448	rcMsc = __vmx_vmread(idxField, &uLow);
2449	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
2450	*pData = RT_MAKE_U64(uLow, uHigh);
2451	# else
2452	rcMsc = __vmx_vmread(idxField, pData);
2453	# endif
2454	if (RT_LIKELY(rcMsc == 0))
2455	return VINF_SUCCESS;
2456	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2457
2458	# elif ARCH_BITS == 32
2459	int rc;
2460	uint32_t val_hi, val;
2461	rc = VMXReadVmcs32(idxField, &val);
2462	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
2463	AssertRC(rc);
2464	*pData = RT_MAKE_U64(val, val_hi);
2465	return rc;
2466
2467	# else
2468	# error "Shouldn't be here..."
2469	# endif
2470	}
2471	#endif
2472
2473	/**
2474	* Gets the last instruction error value from the current VMCS.
2475	*
2476	* @returns VBox status code.
2477	*/
2478	DECLINLINE(uint32_t) VMXGetLastError(void)
2479	{
2480	#if ARCH_BITS == 64
2481	uint64_t uLastError = 0;
2482	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2483	AssertRC(rc);
2484	return (uint32_t)uLastError;
2485
2486	#else /* 32-bit host: */
2487	uint32_t uLastError = 0;
2488	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2489	AssertRC(rc);
2490	return uLastError;
2491	#endif
2492	}
2493
2494	#ifdef IN_RING0
2495	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2496	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2497	#endif /* IN_RING0 */
2498
2499	/** @} */
2500
2501	/** @} */
2502
2503	#endif
2504

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 60177

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