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source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 81242

最後變更 在這個檔案從81242是 81242,由 vboxsync 提交於 5 年 前

VMM: Log RDPRU feature bit, VMCB intercept bit and VMEXIT code.
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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.alldomusa.eu.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_hm_svm_h
27#define VBOX_INCLUDED_vmm_hm_svm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35
36#ifdef RT_OS_SOLARIS
37# undef ES
38# undef CS
39# undef DS
40# undef SS
41# undef FS
42# undef GS
43#endif
44
45/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
46 * @ingroup grp_hm
47 * @{
48 */
49
50/** @name SVM generic / convenient defines.
51 * @{
52 */
53/** Number of pages required for the VMCB. */
54#define SVM_VMCB_PAGES 1
55/** Number of pages required for the MSR permission bitmap. */
56#define SVM_MSRPM_PAGES 2
57/** Number of pages required for the IO permission bitmap. */
58#define SVM_IOPM_PAGES 3
59/** @} */
60
61/*
62 * Ugly!
63 * When compiling the recompiler, its own svm.h defines clash with
64 * the following defines. Avoid just the duplicates here as we still
65 * require other definitions and structures in this header.
66 */
67#ifndef IN_REM_R3
68/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
69 * @{
70 */
71/** Invalid guest state in VMCB. */
72# define SVM_EXIT_INVALID (uint64_t)(-1)
73/** Read from CR0-CR15. */
74# define SVM_EXIT_READ_CR0 0x0
75# define SVM_EXIT_READ_CR1 0x1
76# define SVM_EXIT_READ_CR2 0x2
77# define SVM_EXIT_READ_CR3 0x3
78# define SVM_EXIT_READ_CR4 0x4
79# define SVM_EXIT_READ_CR5 0x5
80# define SVM_EXIT_READ_CR6 0x6
81# define SVM_EXIT_READ_CR7 0x7
82# define SVM_EXIT_READ_CR8 0x8
83# define SVM_EXIT_READ_CR9 0x9
84# define SVM_EXIT_READ_CR10 0xa
85# define SVM_EXIT_READ_CR11 0xb
86# define SVM_EXIT_READ_CR12 0xc
87# define SVM_EXIT_READ_CR13 0xd
88# define SVM_EXIT_READ_CR14 0xe
89# define SVM_EXIT_READ_CR15 0xf
90/** Writes to CR0-CR15. */
91# define SVM_EXIT_WRITE_CR0 0x10
92# define SVM_EXIT_WRITE_CR1 0x11
93# define SVM_EXIT_WRITE_CR2 0x12
94# define SVM_EXIT_WRITE_CR3 0x13
95# define SVM_EXIT_WRITE_CR4 0x14
96# define SVM_EXIT_WRITE_CR5 0x15
97# define SVM_EXIT_WRITE_CR6 0x16
98# define SVM_EXIT_WRITE_CR7 0x17
99# define SVM_EXIT_WRITE_CR8 0x18
100# define SVM_EXIT_WRITE_CR9 0x19
101# define SVM_EXIT_WRITE_CR10 0x1a
102# define SVM_EXIT_WRITE_CR11 0x1b
103# define SVM_EXIT_WRITE_CR12 0x1c
104# define SVM_EXIT_WRITE_CR13 0x1d
105# define SVM_EXIT_WRITE_CR14 0x1e
106# define SVM_EXIT_WRITE_CR15 0x1f
107/** Read from DR0-DR15. */
108# define SVM_EXIT_READ_DR0 0x20
109# define SVM_EXIT_READ_DR1 0x21
110# define SVM_EXIT_READ_DR2 0x22
111# define SVM_EXIT_READ_DR3 0x23
112# define SVM_EXIT_READ_DR4 0x24
113# define SVM_EXIT_READ_DR5 0x25
114# define SVM_EXIT_READ_DR6 0x26
115# define SVM_EXIT_READ_DR7 0x27
116# define SVM_EXIT_READ_DR8 0x28
117# define SVM_EXIT_READ_DR9 0x29
118# define SVM_EXIT_READ_DR10 0x2a
119# define SVM_EXIT_READ_DR11 0x2b
120# define SVM_EXIT_READ_DR12 0x2c
121# define SVM_EXIT_READ_DR13 0x2d
122# define SVM_EXIT_READ_DR14 0x2e
123# define SVM_EXIT_READ_DR15 0x2f
124/** Writes to DR0-DR15. */
125# define SVM_EXIT_WRITE_DR0 0x30
126# define SVM_EXIT_WRITE_DR1 0x31
127# define SVM_EXIT_WRITE_DR2 0x32
128# define SVM_EXIT_WRITE_DR3 0x33
129# define SVM_EXIT_WRITE_DR4 0x34
130# define SVM_EXIT_WRITE_DR5 0x35
131# define SVM_EXIT_WRITE_DR6 0x36
132# define SVM_EXIT_WRITE_DR7 0x37
133# define SVM_EXIT_WRITE_DR8 0x38
134# define SVM_EXIT_WRITE_DR9 0x39
135# define SVM_EXIT_WRITE_DR10 0x3a
136# define SVM_EXIT_WRITE_DR11 0x3b
137# define SVM_EXIT_WRITE_DR12 0x3c
138# define SVM_EXIT_WRITE_DR13 0x3d
139# define SVM_EXIT_WRITE_DR14 0x3e
140# define SVM_EXIT_WRITE_DR15 0x3f
141/* Exception 0-31. */
142# define SVM_EXIT_XCPT_0 0x40
143# define SVM_EXIT_XCPT_1 0x41
144# define SVM_EXIT_XCPT_2 0x42
145# define SVM_EXIT_XCPT_3 0x43
146# define SVM_EXIT_XCPT_4 0x44
147# define SVM_EXIT_XCPT_5 0x45
148# define SVM_EXIT_XCPT_6 0x46
149# define SVM_EXIT_XCPT_7 0x47
150# define SVM_EXIT_XCPT_8 0x48
151# define SVM_EXIT_XCPT_9 0x49
152# define SVM_EXIT_XCPT_10 0x4a
153# define SVM_EXIT_XCPT_11 0x4b
154# define SVM_EXIT_XCPT_12 0x4c
155# define SVM_EXIT_XCPT_13 0x4d
156# define SVM_EXIT_XCPT_14 0x4e
157# define SVM_EXIT_XCPT_15 0x4f
158# define SVM_EXIT_XCPT_16 0x50
159# define SVM_EXIT_XCPT_17 0x51
160# define SVM_EXIT_XCPT_18 0x52
161# define SVM_EXIT_XCPT_19 0x53
162# define SVM_EXIT_XCPT_20 0x54
163# define SVM_EXIT_XCPT_21 0x55
164# define SVM_EXIT_XCPT_22 0x56
165# define SVM_EXIT_XCPT_23 0x57
166# define SVM_EXIT_XCPT_24 0x58
167# define SVM_EXIT_XCPT_25 0x59
168# define SVM_EXIT_XCPT_26 0x5a
169# define SVM_EXIT_XCPT_27 0x5b
170# define SVM_EXIT_XCPT_28 0x5c
171# define SVM_EXIT_XCPT_29 0x5d
172# define SVM_EXIT_XCPT_30 0x5e
173# define SVM_EXIT_XCPT_31 0x5f
174/* Exception (more readable) */
175# define SVM_EXIT_XCPT_DE SVM_EXIT_XCPT_0
176# define SVM_EXIT_XCPT_DB SVM_EXIT_XCPT_1
177# define SVM_EXIT_XCPT_NMI SVM_EXIT_XCPT_2
178# define SVM_EXIT_XCPT_BP SVM_EXIT_XCPT_3
179# define SVM_EXIT_XCPT_OF SVM_EXIT_XCPT_4
180# define SVM_EXIT_XCPT_BR SVM_EXIT_XCPT_5
181# define SVM_EXIT_XCPT_UD SVM_EXIT_XCPT_6
182# define SVM_EXIT_XCPT_NM SVM_EXIT_XCPT_7
183# define SVM_EXIT_XCPT_DF SVM_EXIT_XCPT_8
184# define SVM_EXIT_XCPT_CO_SEG_OVERRUN SVM_EXIT_XCPT_9
185# define SVM_EXIT_XCPT_TS SVM_EXIT_XCPT_10
186# define SVM_EXIT_XCPT_NP SVM_EXIT_XCPT_11
187# define SVM_EXIT_XCPT_SS SVM_EXIT_XCPT_12
188# define SVM_EXIT_XCPT_GP SVM_EXIT_XCPT_13
189# define SVM_EXIT_XCPT_PF SVM_EXIT_XCPT_14
190# define SVM_EXIT_XCPT_MF SVM_EXIT_XCPT_16
191# define SVM_EXIT_XCPT_AC SVM_EXIT_XCPT_17
192# define SVM_EXIT_XCPT_MC SVM_EXIT_XCPT_18
193# define SVM_EXIT_XCPT_XF SVM_EXIT_XCPT_19
194# define SVM_EXIT_XCPT_VE SVM_EXIT_XCPT_20
195# define SVM_EXIT_XCPT_SX SVM_EXIT_XCPT_30
196/** Physical maskable interrupt. */
197# define SVM_EXIT_INTR 0x60
198/** Non-maskable interrupt. */
199# define SVM_EXIT_NMI 0x61
200/** System Management interrupt. */
201# define SVM_EXIT_SMI 0x62
202/** Physical INIT signal. */
203# define SVM_EXIT_INIT 0x63
204/** Virtual interrupt. */
205# define SVM_EXIT_VINTR 0x64
206/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
207# define SVM_EXIT_CR0_SEL_WRITE 0x65
208/** IDTR read. */
209# define SVM_EXIT_IDTR_READ 0x66
210/** GDTR read. */
211# define SVM_EXIT_GDTR_READ 0x67
212/** LDTR read. */
213# define SVM_EXIT_LDTR_READ 0x68
214/** TR read. */
215# define SVM_EXIT_TR_READ 0x69
216/** IDTR write. */
217# define SVM_EXIT_IDTR_WRITE 0x6a
218/** GDTR write. */
219# define SVM_EXIT_GDTR_WRITE 0x6b
220/** LDTR write. */
221# define SVM_EXIT_LDTR_WRITE 0x6c
222/** TR write. */
223# define SVM_EXIT_TR_WRITE 0x6d
224/** RDTSC instruction. */
225# define SVM_EXIT_RDTSC 0x6e
226/** RDPMC instruction. */
227# define SVM_EXIT_RDPMC 0x6f
228/** PUSHF instruction. */
229# define SVM_EXIT_PUSHF 0x70
230/** POPF instruction. */
231# define SVM_EXIT_POPF 0x71
232/** CPUID instruction. */
233# define SVM_EXIT_CPUID 0x72
234/** RSM instruction. */
235# define SVM_EXIT_RSM 0x73
236/** IRET instruction. */
237# define SVM_EXIT_IRET 0x74
238/** software interrupt (INTn instructions). */
239# define SVM_EXIT_SWINT 0x75
240/** INVD instruction. */
241# define SVM_EXIT_INVD 0x76
242/** PAUSE instruction. */
243# define SVM_EXIT_PAUSE 0x77
244/** HLT instruction. */
245# define SVM_EXIT_HLT 0x78
246/** INVLPG instructions. */
247# define SVM_EXIT_INVLPG 0x79
248/** INVLPGA instruction. */
249# define SVM_EXIT_INVLPGA 0x7a
250/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
251# define SVM_EXIT_IOIO 0x7b
252/** RDMSR or WRMSR access to protected MSR. */
253# define SVM_EXIT_MSR 0x7c
254/** task switch. */
255# define SVM_EXIT_TASK_SWITCH 0x7d
256/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
257# define SVM_EXIT_FERR_FREEZE 0x7e
258/** Shutdown. */
259# define SVM_EXIT_SHUTDOWN 0x7f
260/** VMRUN instruction. */
261# define SVM_EXIT_VMRUN 0x80
262/** VMMCALL instruction. */
263# define SVM_EXIT_VMMCALL 0x81
264/** VMLOAD instruction. */
265# define SVM_EXIT_VMLOAD 0x82
266/** VMSAVE instruction. */
267# define SVM_EXIT_VMSAVE 0x83
268/** STGI instruction. */
269# define SVM_EXIT_STGI 0x84
270/** CLGI instruction. */
271# define SVM_EXIT_CLGI 0x85
272/** SKINIT instruction. */
273# define SVM_EXIT_SKINIT 0x86
274/** RDTSCP instruction. */
275# define SVM_EXIT_RDTSCP 0x87
276/** ICEBP instruction. */
277# define SVM_EXIT_ICEBP 0x88
278/** WBINVD instruction. */
279# define SVM_EXIT_WBINVD 0x89
280/** MONITOR instruction. */
281# define SVM_EXIT_MONITOR 0x8a
282/** MWAIT instruction. */
283# define SVM_EXIT_MWAIT 0x8b
284/** MWAIT instruction, when armed. */
285# define SVM_EXIT_MWAIT_ARMED 0x8c
286/** XSETBV instruction. */
287# define SVM_EXIT_XSETBV 0x8d
288/** RDPRU instruction. */
289# define SVM_EXIT_RDPRU 0x8e
290/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
291# define SVM_EXIT_NPF 0x400
292/** AVIC: Virtual IPI delivery not completed. */
293# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
294/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
295 * hardware. */
296# define SVM_EXIT_AVIC_NOACCEL 0x402
297/** The maximum possible exit value. */
298# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
299/** @} */
300#endif /* !IN_REM_R3*/
301
302
303/** @name SVMVMCB.u64ExitInfo2 for task switches
304 * @{
305 */
306/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
307#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
308/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
309#define SVM_EXIT2_TASK_SWITCH_JUMP RT_BIT_64(38)
310/** Set to 1 if the task switch has an error code; else cleared to 0. */
311#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
312/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
313#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
314/** @} */
315
316/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
317 * @{
318 */
319/** The access was a read MSR. */
320#define SVM_EXIT1_MSR_READ 0x0
321/** The access was a write MSR. */
322#define SVM_EXIT1_MSR_WRITE 0x1
323/** @} */
324
325/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
326 * @{
327 */
328/** The mask of whether the access was via a Mov CRx instruction. */
329#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
330/** The mask for the GPR number of the Mov CRx instruction. */
331#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
332/** @} */
333
334/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
335 * @{
336 */
337/** The mask for the GPR number of the Mov DRx instruction. */
338#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
339/** @} */
340
341/** @name SVMVMCB.ctrl.u64InterceptCtrl
342 * @{
343 */
344/** Intercept INTR (physical maskable interrupt). */
345#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
346/** Intercept NMI. */
347#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
348/** Intercept SMI. */
349#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
350/** Intercept INIT. */
351#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
352/** Intercept VINTR (virtual maskable interrupt). */
353#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
354/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
355#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITE RT_BIT_64(5)
356/** Intercept reads of IDTR. */
357#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
358/** Intercept reads of GDTR. */
359#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
360/** Intercept reads of LDTR. */
361#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
362/** Intercept reads of TR. */
363#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
364/** Intercept writes of IDTR. */
365#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
366/** Intercept writes of GDTR. */
367#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
368/** Intercept writes of LDTR. */
369#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
370/** Intercept writes of TR. */
371#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
372/** Intercept RDTSC instruction. */
373#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
374/** Intercept RDPMC instruction. */
375#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
376/** Intercept PUSHF instruction. */
377#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
378/** Intercept POPF instruction. */
379#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
380/** Intercept CPUID instruction. */
381#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
382/** Intercept RSM instruction. */
383#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
384/** Intercept IRET instruction. */
385#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
386/** Intercept INTn instruction. */
387#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
388/** Intercept INVD instruction. */
389#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
390/** Intercept PAUSE instruction. */
391#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
392/** Intercept HLT instruction. */
393#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
394/** Intercept INVLPG instruction. */
395#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
396/** Intercept INVLPGA instruction. */
397#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
398/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
399#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
400/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
401#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
402/** Intercept task switches. */
403#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
404/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
405#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
406/** Intercept shutdown events. */
407#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
408/** Intercept VMRUN instruction. */
409#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
410/** Intercept VMMCALL instruction. */
411#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
412/** Intercept VMLOAD instruction. */
413#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
414/** Intercept VMSAVE instruction. */
415#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
416/** Intercept STGI instruction. */
417#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
418/** Intercept CLGI instruction. */
419#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
420/** Intercept SKINIT instruction. */
421#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
422/** Intercept RDTSCP instruction. */
423#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
424/** Intercept ICEBP instruction. */
425#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
426/** Intercept WBINVD instruction. */
427#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
428/** Intercept MONITOR instruction. */
429#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
430/** Intercept MWAIT instruction unconditionally. */
431#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
432/** Intercept MWAIT instruction when armed. */
433#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
434/** Intercept XSETBV instruction. */
435#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
436/** Intercept RDPRU instruction. */
437#define SVM_CTRL_INTERCEPT_RDPRU RT_BIT_64(32 + 14)
438/* Bit 14 - Reserved, SBZ. */
439/** Intercept EFER writes after guest instruction finishes. */
440#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
441/** Intercept CR0 writes after guest instruction finishes. */
442#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
443/** Intercept CR0 writes after guest instruction finishes. */
444#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
445/** Intercept CR0 writes after guest instruction finishes. */
446#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
447/** Intercept CR0 writes after guest instruction finishes. */
448#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
449/** Intercept CR0 writes after guest instruction finishes. */
450#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
451/** Intercept CR0 writes after guest instruction finishes. */
452#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
453/** Intercept CR0 writes after guest instruction finishes. */
454#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
455/** Intercept CR0 writes after guest instruction finishes. */
456#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
457/** Intercept CR0 writes after guest instruction finishes. */
458#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
459/** Intercept CR0 writes after guest instruction finishes. */
460#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
461/** Intercept CR0 writes after guest instruction finishes. */
462#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
463/** Intercept CR0 writes after guest instruction finishes. */
464#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
465/** Intercept CR0 writes after guest instruction finishes. */
466#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
467/** Intercept CR0 writes after guest instruction finishes. */
468#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
469/** Intercept CR0 writes after guest instruction finishes. */
470#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
471/** Intercept CR0 writes after guest instruction finishes. */
472#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
473/** @} */
474
475/** @name SVMINTCTRL.u3Type
476 * @{
477 */
478/** External or virtual interrupt. */
479#define SVM_EVENT_EXTERNAL_IRQ 0
480/** Non-maskable interrupt. */
481#define SVM_EVENT_NMI 2
482/** Exception; fault or trap. */
483#define SVM_EVENT_EXCEPTION 3
484/** Software interrupt. */
485#define SVM_EVENT_SOFTWARE_INT 4
486/** @} */
487
488/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
489 * @{
490 */
491/** Flush nothing. */
492#define SVM_TLB_FLUSH_NOTHING 0
493/** Flush entire TLB (host+guest entries) */
494#define SVM_TLB_FLUSH_ENTIRE 1
495/** Flush this guest's TLB entries (by ASID) */
496#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
497/** Flush this guest's non-global TLB entries (by ASID) */
498#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
499/** @} */
500
501/**
502 * SVM selector/segment register type.
503 */
504typedef struct
505{
506 uint16_t u16Sel;
507 uint16_t u16Attr;
508 uint32_t u32Limit;
509 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
510} SVMSELREG;
511AssertCompileSize(SVMSELREG, 16);
512/** Pointer to the SVMSELREG struct. */
513typedef SVMSELREG *PSVMSELREG;
514/** Pointer to a const SVMSELREG struct. */
515typedef const SVMSELREG *PCSVMSELREG;
516
517/**
518 * SVM GDTR/IDTR type.
519 */
520typedef struct
521{
522 uint16_t u16Reserved0;
523 uint16_t u16Reserved1;
524 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
525 uint64_t u64Base;
526} SVMXDTR;
527AssertCompileSize(SVMXDTR, 16);
528typedef SVMXDTR SVMIDTR;
529typedef SVMXDTR SVMGDTR;
530/** Pointer to the SVMXDTR struct. */
531typedef SVMXDTR *PSVMXDTR;
532/** Pointer to a const SVMXDTR struct. */
533typedef const SVMXDTR *PCSVMXDTR;
534
535/**
536 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
537 */
538typedef union
539{
540 struct
541 {
542 uint32_t u8Vector : 8;
543 uint32_t u3Type : 3;
544 uint32_t u1ErrorCodeValid : 1;
545 uint32_t u19Reserved : 19;
546 uint32_t u1Valid : 1;
547 uint32_t u32ErrorCode : 32;
548 } n;
549 uint64_t u;
550} SVMEVENT;
551/** Pointer to the SVMEVENT union. */
552typedef SVMEVENT *PSVMEVENT;
553/** Pointer to a const SVMEVENT union. */
554typedef const SVMEVENT *PCSVMEVENT;
555
556/** Gets the event type given an SVMEVENT parameter. */
557#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
558
559/**
560 * SVM Interrupt control structure (Virtual Interrupt Control).
561 */
562typedef union
563{
564 struct
565 {
566 uint32_t u8VTPR : 8; /* V_TPR */
567 uint32_t u1VIrqPending : 1; /* V_IRQ */
568 uint32_t u1VGif : 1; /* VGIF */
569 uint32_t u6Reserved : 6;
570 uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
571 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
572 uint32_t u3Reserved : 3;
573 uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
574 uint32_t u1VGifEnable : 1; /* VGIF enable */
575 uint32_t u5Reserved : 5;
576 uint32_t u1AvicEnable : 1; /* AVIC enable */
577 uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
578 uint32_t u24Reserved : 24;
579 } n;
580 uint64_t u;
581} SVMINTCTRL;
582/** Pointer to an SVMINTCTRL structure. */
583typedef SVMINTCTRL *PSVMINTCTRL;
584/** Pointer to a const SVMINTCTRL structure. */
585typedef const SVMINTCTRL *PCSVMINTCTRL;
586
587/**
588 * SVM TLB control structure.
589 */
590typedef union
591{
592 struct
593 {
594 uint32_t u32ASID : 32;
595 uint32_t u8TLBFlush : 8;
596 uint32_t u24Reserved : 24;
597 } n;
598 uint64_t u;
599} SVMTLBCTRL;
600
601/**
602 * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
603 */
604typedef union
605{
606 struct
607 {
608 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
609 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
610 uint32_t u1Str : 1; /**< Bit 2: String I/O (1) or not (0). */
611 uint32_t u1Rep : 1; /**< Bit 3: Repeat prefixed string I/O. */
612 uint32_t u1Op8 : 1; /**< Bit 4: 8-bit operand. */
613 uint32_t u1Op16 : 1; /**< Bit 5: 16-bit operand. */
614 uint32_t u1Op32 : 1; /**< Bit 6: 32-bit operand. */
615 uint32_t u1Addr16 : 1; /**< Bit 7: 16-bit address size. */
616 uint32_t u1Addr32 : 1; /**< Bit 8: 32-bit address size. */
617 uint32_t u1Addr64 : 1; /**< Bit 9: 64-bit address size. */
618 uint32_t u3Seg : 3; /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
619 uint32_t u3Reserved : 3;
620 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
621 } n;
622 uint32_t u;
623} SVMIOIOEXITINFO;
624/** Pointer to an SVM IOIO exit info. structure. */
625typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
626/** Pointer to a const SVM IOIO exit info. structure. */
627typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
628
629/** 8-bit IO transfer. */
630#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
631/** 16-bit IO transfer. */
632#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
633/** 32-bit IO transfer. */
634#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
635/** Number of bits to shift right to get the operand sizes. */
636#define SVM_IOIO_OP_SIZE_SHIFT 4
637/** Mask of all possible IO transfer sizes. */
638#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
639/** 16-bit address for the IO buffer. */
640#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
641/** 32-bit address for the IO buffer. */
642#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
643/** 64-bit address for the IO buffer. */
644#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
645/** Number of bits to shift right to get the address sizes. */
646#define SVM_IOIO_ADDR_SIZE_SHIFT 7
647/** Mask of all the IO address sizes. */
648#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
649/** Number of bits to shift right to get the IO port number. */
650#define SVM_IOIO_PORT_SHIFT 16
651/** IO write. */
652#define SVM_IOIO_WRITE 0
653/** IO read. */
654#define SVM_IOIO_READ 1
655/**
656 * SVM IOIO transfer type.
657 */
658typedef enum
659{
660 SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
661 SVMIOIOTYPE_IN = SVM_IOIO_READ
662} SVMIOIOTYPE;
663
664/**
665 * SVM AVIC.
666 */
667typedef union
668{
669 struct
670 {
671 RT_GCC_EXTENSION uint64_t u12Reserved0 : 12;
672 RT_GCC_EXTENSION uint64_t u40Addr : 40;
673 RT_GCC_EXTENSION uint64_t u12Reserved1 : 12;
674 } n;
675 uint64_t u;
676} SVMAVIC;
677AssertCompileSize(SVMAVIC, 8);
678
679/**
680 * SVM AVIC PHYSICAL_TABLE pointer.
681 */
682typedef union
683{
684 struct
685 {
686 RT_GCC_EXTENSION uint64_t u8LastGuestCoreId : 8;
687 RT_GCC_EXTENSION uint64_t u4Reserved : 4;
688 RT_GCC_EXTENSION uint64_t u40Addr : 40;
689 RT_GCC_EXTENSION uint64_t u12Reserved : 12;
690 } n;
691 uint64_t u;
692} SVMAVICPHYS;
693AssertCompileSize(SVMAVICPHYS, 8);
694
695/**
696 * SVM Nested Paging struct.
697 */
698typedef union
699{
700 struct
701 {
702 uint32_t u1NestedPaging : 1;
703 uint32_t u1Sev : 1;
704 uint32_t u1SevEs : 1;
705 uint32_t u29Reserved : 29;
706 } n;
707 uint64_t u;
708} SVMNP;
709AssertCompileSize(SVMNP, 8);
710
711/**
712 * SVM Interrupt shadow struct.
713 */
714typedef union
715{
716 struct
717 {
718 uint32_t u1IntShadow : 1;
719 uint32_t u1GuestIntMask : 1;
720 uint32_t u30Reserved : 30;
721 } n;
722 uint64_t u;
723} SVMINTSHADOW;
724AssertCompileSize(SVMINTSHADOW, 8);
725
726/**
727 * SVM LBR virtualization struct.
728 */
729typedef union
730{
731 struct
732 {
733 uint32_t u1LbrVirt : 1;
734 uint32_t u1VirtVmsaveVmload : 1;
735 uint32_t u30Reserved : 30;
736 } n;
737 uint64_t u;
738} SVMLBRVIRT;
739AssertCompileSize(SVMLBRVIRT, 8);
740
741/** Maximum number of bytes in the Guest-instruction bytes field. */
742#define SVM_CTRL_GUEST_INSTR_BYTES_MAX 15
743
744/**
745 * SVM VMCB control area.
746 */
747#pragma pack(1)
748typedef struct
749{
750 /** Offset 0x00 - Intercept reads of CR0-CR15. */
751 uint16_t u16InterceptRdCRx;
752 /** Offset 0x02 - Intercept writes to CR0-CR15. */
753 uint16_t u16InterceptWrCRx;
754 /** Offset 0x04 - Intercept reads of DR0-DR15. */
755 uint16_t u16InterceptRdDRx;
756 /** Offset 0x06 - Intercept writes to DR0-DR15. */
757 uint16_t u16InterceptWrDRx;
758 /** Offset 0x08 - Intercept exception vectors 0-31. */
759 uint32_t u32InterceptXcpt;
760 /** Offset 0x0c - Intercept control. */
761 uint64_t u64InterceptCtrl;
762 /** Offset 0x14-0x3f - Reserved. */
763 uint8_t u8Reserved0[0x3c - 0x14];
764 /** Offset 0x3c - PAUSE filter threshold. */
765 uint16_t u16PauseFilterThreshold;
766 /** Offset 0x3e - PAUSE intercept filter count. */
767 uint16_t u16PauseFilterCount;
768 /** Offset 0x40 - Physical address of IOPM. */
769 uint64_t u64IOPMPhysAddr;
770 /** Offset 0x48 - Physical address of MSRPM. */
771 uint64_t u64MSRPMPhysAddr;
772 /** Offset 0x50 - TSC Offset. */
773 uint64_t u64TSCOffset;
774 /** Offset 0x58 - TLB control field. */
775 SVMTLBCTRL TLBCtrl;
776 /** Offset 0x60 - Interrupt control field. */
777 SVMINTCTRL IntCtrl;
778 /** Offset 0x68 - Interrupt shadow. */
779 SVMINTSHADOW IntShadow;
780 /** Offset 0x70 - Exit code. */
781 uint64_t u64ExitCode;
782 /** Offset 0x78 - Exit info 1. */
783 uint64_t u64ExitInfo1;
784 /** Offset 0x80 - Exit info 2. */
785 uint64_t u64ExitInfo2;
786 /** Offset 0x88 - Exit Interrupt info. */
787 SVMEVENT ExitIntInfo;
788 /** Offset 0x90 - Nested Paging control. */
789 SVMNP NestedPagingCtrl;
790 /** Offset 0x98 - AVIC APIC BAR. */
791 SVMAVIC AvicBar;
792 /** Offset 0xa0-0xa7 - Reserved. */
793 uint8_t u8Reserved1[0xa8 - 0xa0];
794 /** Offset 0xa8 - Event injection. */
795 SVMEVENT EventInject;
796 /** Offset 0xb0 - Host CR3 for nested paging. */
797 uint64_t u64NestedPagingCR3;
798 /** Offset 0xb8 - LBR Virtualization. */
799 SVMLBRVIRT LbrVirt;
800 /** Offset 0xc0 - VMCB Clean Bits. */
801 uint32_t u32VmcbCleanBits;
802 uint32_t u32Reserved0;
803 /** Offset 0xc8 - Next sequential instruction pointer. */
804 uint64_t u64NextRIP;
805 /** Offset 0xd0 - Number of bytes fetched. */
806 uint8_t cbInstrFetched;
807 /** Offset 0xd1 - Guest instruction bytes. */
808 uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
809 /** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
810 SVMAVIC AvicBackingPagePtr;
811 /** Offset 0xe8-0xef - Reserved. */
812 uint8_t u8Reserved2[0xf0 - 0xe8];
813 /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
814 SVMAVIC AvicLogicalTablePtr;
815 /** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
816 SVMAVICPHYS AvicPhysicalTablePtr;
817} SVMVMCBCTRL;
818#pragma pack()
819/** Pointer to the SVMVMCBSTATESAVE structure. */
820typedef SVMVMCBCTRL *PSVMVMCBCTRL;
821/** Pointer to a const SVMVMCBSTATESAVE structure. */
822typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
823AssertCompileSize(SVMVMCBCTRL, 0x100);
824AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
825AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
826AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
827AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
828AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
829AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
830AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved0, 0x14);
831AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
832AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
833AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
834AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
835AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
836AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
837AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
838AssertCompileMemberOffset(SVMVMCBCTRL, IntShadow, 0x68);
839AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
840AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
841AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
842AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
843AssertCompileMemberOffset(SVMVMCBCTRL, NestedPagingCtrl, 0x90);
844AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
845AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved1, 0xa0);
846AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
847AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
848AssertCompileMemberOffset(SVMVMCBCTRL, LbrVirt, 0xb8);
849AssertCompileMemberOffset(SVMVMCBCTRL, u32VmcbCleanBits, 0xc0);
850AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
851AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
852AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
853AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
854AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xe8);
855AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
856AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
857AssertCompileMemberSize(SVMVMCBCTRL, abInstr, 0x0f);
858
859/**
860 * SVM VMCB state save area.
861 */
862#pragma pack(1)
863typedef struct
864{
865 /** Offset 0x400 - Guest ES register + hidden parts. */
866 SVMSELREG ES;
867 /** Offset 0x410 - Guest CS register + hidden parts. */
868 SVMSELREG CS;
869 /** Offset 0x420 - Guest SS register + hidden parts. */
870 SVMSELREG SS;
871 /** Offset 0x430 - Guest DS register + hidden parts. */
872 SVMSELREG DS;
873 /** Offset 0x440 - Guest FS register + hidden parts. */
874 SVMSELREG FS;
875 /** Offset 0x450 - Guest GS register + hidden parts. */
876 SVMSELREG GS;
877 /** Offset 0x460 - Guest GDTR register. */
878 SVMGDTR GDTR;
879 /** Offset 0x470 - Guest LDTR register + hidden parts. */
880 SVMSELREG LDTR;
881 /** Offset 0x480 - Guest IDTR register. */
882 SVMIDTR IDTR;
883 /** Offset 0x490 - Guest TR register + hidden parts. */
884 SVMSELREG TR;
885 /** Offset 0x4A0-0x4CA - Reserved. */
886 uint8_t u8Reserved0[0x4cb - 0x4a0];
887 /** Offset 0x4CB - CPL. */
888 uint8_t u8CPL;
889 /** Offset 0x4CC-0x4CF - Reserved. */
890 uint8_t u8Reserved1[0x4d0 - 0x4cc];
891 /** Offset 0x4D0 - EFER. */
892 uint64_t u64EFER;
893 /** Offset 0x4D8-0x547 - Reserved. */
894 uint8_t u8Reserved2[0x548 - 0x4d8];
895 /** Offset 0x548 - CR4. */
896 uint64_t u64CR4;
897 /** Offset 0x550 - CR3. */
898 uint64_t u64CR3;
899 /** Offset 0x558 - CR0. */
900 uint64_t u64CR0;
901 /** Offset 0x560 - DR7. */
902 uint64_t u64DR7;
903 /** Offset 0x568 - DR6. */
904 uint64_t u64DR6;
905 /** Offset 0x570 - RFLAGS. */
906 uint64_t u64RFlags;
907 /** Offset 0x578 - RIP. */
908 uint64_t u64RIP;
909 /** Offset 0x580-0x5D7 - Reserved. */
910 uint8_t u8Reserved3[0x5d8 - 0x580];
911 /** Offset 0x5D8 - RSP. */
912 uint64_t u64RSP;
913 /** Offset 0x5E0-0x5F7 - Reserved. */
914 uint8_t u8Reserved4[0x5f8 - 0x5e0];
915 /** Offset 0x5F8 - RAX. */
916 uint64_t u64RAX;
917 /** Offset 0x600 - STAR. */
918 uint64_t u64STAR;
919 /** Offset 0x608 - LSTAR. */
920 uint64_t u64LSTAR;
921 /** Offset 0x610 - CSTAR. */
922 uint64_t u64CSTAR;
923 /** Offset 0x618 - SFMASK. */
924 uint64_t u64SFMASK;
925 /** Offset 0x620 - KernelGSBase. */
926 uint64_t u64KernelGSBase;
927 /** Offset 0x628 - SYSENTER_CS. */
928 uint64_t u64SysEnterCS;
929 /** Offset 0x630 - SYSENTER_ESP. */
930 uint64_t u64SysEnterESP;
931 /** Offset 0x638 - SYSENTER_EIP. */
932 uint64_t u64SysEnterEIP;
933 /** Offset 0x640 - CR2. */
934 uint64_t u64CR2;
935 /** Offset 0x648-0x667 - Reserved. */
936 uint8_t u8Reserved5[0x668 - 0x648];
937 /** Offset 0x668 - PAT (Page Attribute Table) MSR. */
938 uint64_t u64PAT;
939 /** Offset 0x670 - DBGCTL. */
940 uint64_t u64DBGCTL;
941 /** Offset 0x678 - BR_FROM. */
942 uint64_t u64BR_FROM;
943 /** Offset 0x680 - BR_TO. */
944 uint64_t u64BR_TO;
945 /** Offset 0x688 - LASTEXCPFROM. */
946 uint64_t u64LASTEXCPFROM;
947 /** Offset 0x690 - LASTEXCPTO. */
948 uint64_t u64LASTEXCPTO;
949} SVMVMCBSTATESAVE;
950#pragma pack()
951/** Pointer to the SVMVMCBSTATESAVE structure. */
952typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
953/** Pointer to a const SVMVMCBSTATESAVE structure. */
954typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
955AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
956AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
957AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
958AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
959AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
960AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
961AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
962AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
963AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
964AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
965AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
966AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved0, 0x4a0 - 0x400);
967AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
968AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved1, 0x4cc - 0x400);
969AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
970AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved2, 0x4d8 - 0x400);
971AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
972AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
973AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
974AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
975AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
976AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
977AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
978AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved3, 0x580 - 0x400);
979AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
980AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x5e0 - 0x400);
981AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
982AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
983AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
984AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
985AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
986AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
987AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
988AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
989AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
990AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
991AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x648 - 0x400);
992AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64PAT, 0x668 - 0x400);
993AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
994AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
995AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
996AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
997AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
998
999/**
1000 * SVM VM Control Block. (VMCB)
1001 */
1002#pragma pack(1)
1003typedef struct SVMVMCB
1004{
1005 /** Offset 0x00 - Control area. */
1006 SVMVMCBCTRL ctrl;
1007 /** Offset 0x100-0x3FF - Reserved. */
1008 uint8_t u8Reserved0[0x400 - 0x100];
1009 /** Offset 0x400 - State save area. */
1010 SVMVMCBSTATESAVE guest;
1011 /** Offset 0x698-0xFFF- Reserved. */
1012 uint8_t u8Reserved1[0x1000 - 0x698];
1013} SVMVMCB;
1014#pragma pack()
1015/** Pointer to the SVMVMCB structure. */
1016typedef SVMVMCB *PSVMVMCB;
1017/** Pointer to a const SVMVMCB structure. */
1018typedef const SVMVMCB *PCSVMVMCB;
1019AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
1020AssertCompileMemberOffset(SVMVMCB, u8Reserved0, 0x100);
1021AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
1022AssertCompileMemberOffset(SVMVMCB, u8Reserved1, 0x698);
1023AssertCompileSize(SVMVMCB, 0x1000);
1024
1025/**
1026 * SVM MSRs.
1027 */
1028typedef struct SVMMSRS
1029{
1030 /** HWCR MSR. */
1031 uint64_t u64MsrHwcr;
1032 /** Reserved for future. */
1033 uint64_t u64Padding[27];
1034} SVMMSRS;
1035AssertCompileSizeAlignment(SVMMSRS, 8);
1036AssertCompileSize(SVMMSRS, 224);
1037/** Pointer to a SVMMSRS struct. */
1038typedef SVMMSRS *PSVMMSRS;
1039/** Pointer to a const SVMMSRS struct. */
1040typedef const SVMMSRS *PCSVMMSRS;
1041
1042/**
1043 * SVM nested-guest VMCB cache.
1044 *
1045 * Contains VMCB fields from the nested-guest VMCB before they're modified by
1046 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
1047 *
1048 * A VMCB field needs to be cached when it needs to be modified for execution using
1049 * hardware-assisted SVM and any of the following are true:
1050 * - If the original field needs to be inspected during execution of the
1051 * nested-guest or \#VMEXIT processing.
1052 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
1053 *
1054 * A VMCB field needs to be restored only when the field is written back to
1055 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
1056 * guest.
1057 *
1058 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
1059 * this structure.
1060 */
1061#pragma pack(1)
1062typedef struct SVMNESTEDVMCBCACHE
1063{
1064 /** Cache of CRX read intercepts. */
1065 uint16_t u16InterceptRdCRx;
1066 /** Cache of CRX write intercepts. */
1067 uint16_t u16InterceptWrCRx;
1068 /** Cache of DRX read intercepts. */
1069 uint16_t u16InterceptRdDRx;
1070 /** Cache of DRX write intercepts. */
1071 uint16_t u16InterceptWrDRx;
1072
1073 /** Cache of the pause-filter threshold. */
1074 uint16_t u16PauseFilterThreshold;
1075 /** Cache of the pause-filter count. */
1076 uint16_t u16PauseFilterCount;
1077
1078 /** Cache of exception intercepts. */
1079 uint32_t u32InterceptXcpt;
1080 /** Cache of control intercepts. */
1081 uint64_t u64InterceptCtrl;
1082
1083 /** Cache of the TSC offset. */
1084 uint64_t u64TSCOffset;
1085
1086 /** Cache of V_INTR_MASKING bit. */
1087 bool fVIntrMasking;
1088 /** Cache of the nested-paging bit. */
1089 bool fNestedPaging;
1090 /** Cache of the LBR virtualization bit. */
1091 bool fLbrVirt;
1092 /** Whether the VMCB is cached by HM. */
1093 bool fCacheValid;
1094 /** Alignment. */
1095 bool afPadding0[4];
1096} SVMNESTEDVMCBCACHE;
1097#pragma pack()
1098/** Pointer to the SVMNESTEDVMCBCACHE structure. */
1099typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
1100/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
1101typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
1102AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
1103
1104/**
1105 * Segment attribute conversion between CPU and AMD-V VMCB format.
1106 *
1107 * The CPU format of the segment attribute is described in X86DESCATTRBITS
1108 * which is 16-bits (i.e. includes 4 bits of the segment limit).
1109 *
1110 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1111 * only the attribute bits and nothing else). Upper 4-bits are unused.
1112 */
1113#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
1114#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
1115
1116/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1117 * Copies the specified segment register to a VMCB from a virtual CPU context.
1118 *
1119 * @param a_pCtx The virtual-CPU context.
1120 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1121 * @param a_REG The segment register in the VMCB state-save
1122 * struct (ES/CS/SS/DS).
1123 * @param a_reg The segment register in the virtual CPU struct
1124 * (es/cs/ss/ds).
1125 */
1126#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1127 do \
1128 { \
1129 Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1130 Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1131 (a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1132 (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1133 (a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1134 (a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1135 } while (0)
1136
1137/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1138 * Copies the specified segment register from the VMCB to a virtual CPU
1139 * context.
1140 *
1141 * @param a_pCtx The virtual-CPU context.
1142 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1143 * @param a_REG The segment register in the VMCB state-save
1144 * struct (ES/CS/SS/DS).
1145 * @param a_reg The segment register in the virtual CPU struct
1146 * (es/ds/ss/ds).
1147 */
1148#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1149 do \
1150 { \
1151 (a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1152 (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1153 (a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1154 (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1155 (a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1156 (a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1157 } while (0)
1158
1159
1160/** @defgroup grp_hm_svm_hwexec SVM Hardware-assisted execution Helpers
1161 *
1162 * These functions are only here because the inline functions in cpum.h calls them.
1163 * Don't add any more functions here unless there is no other option.
1164 * @{
1165 */
1166VMM_INT_DECL(bool) HMGetGuestSvmCtrlIntercepts(PCVMCPU pVCpu, uint64_t *pu64Intercepts);
1167VMM_INT_DECL(bool) HMGetGuestSvmReadCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1168VMM_INT_DECL(bool) HMGetGuestSvmWriteCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1169VMM_INT_DECL(bool) HMGetGuestSvmReadDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1170VMM_INT_DECL(bool) HMGetGuestSvmWriteDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1171VMM_INT_DECL(bool) HMGetGuestSvmXcptIntercepts(PCVMCPU pVCpu, uint32_t *pu32Intercepts);
1172VMM_INT_DECL(bool) HMGetGuestSvmVirtIntrMasking(PCVMCPU pVCpu, bool *pfVIntrMasking);
1173VMM_INT_DECL(bool) HMGetGuestSvmNestedPaging(PCVMCPU pVCpu, bool *pfNestedPagingCtrl);
1174VMM_INT_DECL(bool) HMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, uint16_t *pu16PauseFilterCount);
1175VMM_INT_DECL(bool) HMGetGuestSvmTscOffset(PCVMCPU pVCpu, uint64_t *pu64TscOffset);
1176/** @} */
1177
1178
1179/** @} */
1180
1181#endif /* !VBOX_INCLUDED_vmm_hm_svm_h */
1182
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