gic.h

最後變更在這個檔案是 108427,由 vboxsync 提交於 11 天前
VMM/GIC: bugref:10404 Extend the interrupt lines to the full extent supported by the GIC spec. Added range-selector support while broadcasting SGIs. Added highest priority interrupt calculation (still not complete, binary-point support is still a todo) Other miscellaneous changes related to the above.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
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1	/** @file
2	* ARMv8 Generic Interrupt Controller Architecture (GIC) definitions.
3	*/
4
5	/*
6	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.alldomusa.eu.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_gic_h
37	#define VBOX_INCLUDED_gic_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/types.h>
43	#include <iprt/armv8.h>
44
45	/** @name INTIDs - Interrupt identifier ranges.
46	* @{ */
47	/** Start of the SGI (Software Generated Interrupts) range. */
48	#define GIC_INTID_RANGE_SGI_START 0
49	/** Last valid SGI (Software Generated Interrupts) identifier. */
50	#define GIC_INTID_RANGE_SGI_LAST 15
51	/** Number of SGIs. */
52	#define GIC_INTID_SGI_RANGE_SIZE (GIC_INTID_RANGE_SGI_LAST - GIC_INTID_RANGE_SGI_START + 1)
53
54	/** Start of the PPI (Private Peripheral Interrupts) range. */
55	#define GIC_INTID_RANGE_PPI_START 16
56	/** Last valid PPI (Private Peripheral Interrupts) identifier. */
57	#define GIC_INTID_RANGE_PPI_LAST 31
58	/** Number of PPIs. */
59	#define GIC_INTID_PPI_RANGE_SIZE (GIC_INTID_RANGE_PPI_LAST - GIC_INTID_RANGE_PPI_START + 1)
60
61	/** Start of the SPI (Shared Peripheral Interrupts) range. */
62	#define GIC_INTID_RANGE_SPI_START 32
63	/** Last valid SPI (Shared Peripheral Interrupts) identifier. */
64	#define GIC_INTID_RANGE_SPI_LAST 1019
65	/** The size of the SPI range. */
66	#define GIC_INTID_SPI_RANGE_SIZE (GIC_INTID_RANGE_SPI_LAST - GIC_INTID_RANGE_SPI_START + 1)
67
68	/** Start of the special interrupt range. */
69	#define GIC_INTID_RANGE_SPECIAL_START 1020
70	/** Last valid special interrupt identifier. */
71	#define GIC_INTID_RANGE_SPECIAL_LAST 1023
72	/** Value for an interrupt acknowledge if no pending interrupt with sufficient
73	* priority, security state or interrupt group. */
74	# define GIC_INTID_RANGE_SPECIAL_NO_INTERRUPT 1023
75	/** The size of the extended PPI range. */
76	#define GIC_INTID_SPECIAL_RANGE_SIZE (GIC_INTID_RANGE_SPECIAL_NO_INTERRUPT - GIC_INTID_RANGE_SPECIAL_START + 1)
77
78	/** Start of the extended PPI (Private Peripheral Interrupts) range. */
79	#define GIC_INTID_RANGE_EXT_PPI_START 1056
80	/** Last valid extended PPI (Private Peripheral Interrupts) identifier. */
81	#define GIC_INTID_RANGE_EXT_PPI_LAST 1119
82	/** The size of the extended PPI range. */
83	#define GIC_INTID_EXT_PPI_RANGE_SIZE (GIC_INTID_RANGE_EXT_PPI_LAST - GIC_INTID_RANGE_EXT_PPI_START + 1)
84
85	/** Start of the extended SPI (Shared Peripheral Interrupts) range. */
86	#define GIC_INTID_RANGE_EXT_SPI_START 4096
87	/** Last valid extended SPI (Shared Peripheral Interrupts) identifier. */
88	#define GIC_INTID_RANGE_EXT_SPI_LAST 5119
89	/** The size of the extended SPI range. */
90	#define GIC_INTID_EXT_SPI_RANGE_SIZE (GIC_INTID_RANGE_EXT_SPI_LAST - GIC_INTID_RANGE_EXT_SPI_START + 1)
91
92	/** Start of the LPI (Locality-specific Peripheral Interrupts) range. */
93	#define GIC_INTID_RANGE_LPI_START 8192
94	/** @} */
95
96
97	/** @name GICD - GIC Distributor registers.
98	* @{ */
99	/** Size of the distributor register frame. */
100	#define GIC_DIST_REG_FRAME_SIZE _64K
101
102	/** Distributor Control Register - RW. */
103	#define GIC_DIST_REG_CTLR_OFF 0x0000
104	/** Bit 0 - Enable Group 0 interrupts. */
105	# define GIC_DIST_REG_CTRL_ENABLE_GRP0 RT_BIT_32(0)
106	# define GIC_DIST_REG_CTRL_ENABLE_GRP0_BIT 0
107	/** Bit 1 - Enable Non-secure Group 1 interrupts. */
108	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS RT_BIT_32(1)
109	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS_BIT 1
110	/** Bit 2 - Enable Secure Group 1 interrupts. */
111	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S RT_BIT_32(2)
112	# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S_BIT 2
113	/** Bit 4 - Affinity Routing Enable, Secure state. */
114	# define GIC_DIST_REG_CTRL_ARE_S RT_BIT_32(4)
115	# define GIC_DIST_REG_CTRL_ARE_S_BIT 4
116	/** Bit 5 - Affinity Routing Enable, Non-secure state. */
117	# define GIC_DIST_REG_CTRL_ARE_NS RT_BIT_32(5)
118	# define GIC_DIST_REG_CTRL_ARE_NS_BIT 5
119	/** Bit 6 - Disable Security. */
120	# define GIC_DIST_REG_CTRL_DS RT_BIT_32(6)
121	# define GIC_DIST_REG_CTRL_DS_BIT 6
122	/** Bit 7 - Enable 1 of N Wakeup Functionality. */
123	# define GIC_DIST_REG_CTRL_E1NWF RT_BIT_32(7)
124	# define GIC_DIST_REG_CTRL_E1NWF_BIT 7
125	/** Bit 31 - Register Write Pending. */
126	# define GIC_DIST_REG_CTRL_RWP RT_BIT_32(31)
127	# define GIC_DIST_REG_CTRL_RWP_BIT 31
128
129	/** Interrupt Controller Type Register - RO. */
130	#define GIC_DIST_REG_TYPER_OFF 0x0004
131	/** Bit 0 - 4 - Maximum number of SPIs supported. */
132	# define GIC_DIST_REG_TYPER_NUM_ITLINES ( RT_BIT_32(0) \| RT_BIT_32(1) \| RT_BIT(2) \
133	\| RT_BIT_32(3) \| RT_BIT_32(4))
134	# define GIC_DIST_REG_TYPER_NUM_ITLINES_SET(a_NumSpis) ((a_NumSpis) & GIC_DIST_REG_TYPER_NUM_ITLINES)
135	/** Bit 5 - 7 - Reports number of PEs that can be used when affinity routing is not enabled, minus 1. */
136	# define GIC_DIST_REG_TYPER_NUM_PES (RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT(7))
137	# define GIC_DIST_REG_TYPER_NUM_PES_SET(a_Pes) (((a_Pes) << 5) & GIC_DIST_REG_TYPER_NUM_PES)
138	/** Bit 8 - Extended SPI range implemented. */
139	# define GIC_DIST_REG_TYPER_ESPI RT_BIT_32(8)
140	# define GIC_DIST_REG_TYPER_ESPI_BIT 8
141	/** Bit 9 - Non-maskable interrupt priority supported. */
142	# define GIC_DIST_REG_TYPER_NMI RT_BIT_32(9)
143	# define GIC_DIST_REG_TYPER_NMI_BIT 9
144	/** Bit 10 - Indicates whether the implementation supports two security states. */
145	# define GIC_DIST_REG_TYPER_SECURITY_EXTN RT_BIT_32(10)
146	# define GIC_DIST_REG_TYPER_SECURITY_EXTN_BIT 10
147	/** Bit 11 - 15 - The number of supported LPIs. */
148	# define GIC_DIST_REG_TYPER_NUM_LPIS ( RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT(13) \
149	\| RT_BIT_32(14) \| RT_BIT_32(15))
150	# define GIC_DIST_REG_TYPER_NUM_LPIS_SET(a_Lpis) (((a_Lpis) << 11) & GIC_DIST_REG_TYPER_NUM_LPIS)
151	/** Bit 16 - Indicates whether the implementation supports message based interrupts by writing to Distributor registers. */
152	# define GIC_DIST_REG_TYPER_MBIS RT_BIT_32(16)
153	# define GIC_DIST_REG_TYPER_MBIS_BIT 16
154	/** Bit 17 - Indicates whether the implementation supports LPIs. */
155	# define GIC_DIST_REG_TYPER_LPIS RT_BIT_32(17)
156	# define GIC_DIST_REG_TYPER_LPIS_BIT 17
157	/** Bit 18 - Indicates whether the implementation supports Direct Virtual LPI injection (FEAT_GICv4). */
158	# define GIC_DIST_REG_TYPER_DVIS RT_BIT_32(18)
159	# define GIC_DIST_REG_TYPER_DVIS_BIT 18
160	/** Bit 19 - 23 - The number of interrupt identifer bits supported, minus one. */
161	# define GIC_DIST_REG_TYPER_IDBITS ( RT_BIT_32(19) \| RT_BIT_32(20) \| RT_BIT(21) \
162	\| RT_BIT_32(22) \| RT_BIT_32(23))
163	# define GIC_DIST_REG_TYPER_IDBITS_SET(a_Bits) (((a_Bits) << 19) & GIC_DIST_REG_TYPER_IDBITS)
164	/** Bit 24 - Affinity 3 valid. Indicates whether the Distributor supports nonzero values of Affinity level 3. */
165	# define GIC_DIST_REG_TYPER_A3V RT_BIT_32(24)
166	# define GIC_DIST_REG_TYPER_A3V_BIT 24
167	/** Bit 25 - Indicates whether 1 of N SPI interrupts are supported. */
168	# define GIC_DIST_REG_TYPER_NO1N RT_BIT_32(25)
169	# define GIC_DIST_REG_TYPER_NO1N_BIT 25
170	/** Bit 26 - Range Selector Support. */
171	# define GIC_DIST_REG_TYPER_RSS RT_BIT_32(26)
172	# define GIC_DIST_REG_TYPER_RSS_BIT 26
173	/** Bit 27 - 31 - Indicates maximum INTID in the Extended SPI range. */
174	# define GIC_DIST_REG_TYPER_ESPI_RANGE ( RT_BIT_32(27) \| RT_BIT_32(28) \| RT_BIT(29) \
175	\| RT_BIT_32(30) \| RT_BIT_32(31))
176	# define GIC_DIST_REG_TYPER_ESPI_RANGE_BIT 27
177	# define GIC_DIST_REG_TYPER_ESPI_RANGE_SET(a_Range) (((a_Range) << 27) & GIC_DIST_REG_TYPER_ESPI_RANGE)
178
179	/** Distributor Implementer Identification Register - RO. */
180	#define GIC_DIST_REG_IIDR_OFF 0x0008
181	/** Interrupt Controller Type Register 2 - RO. */
182	#define GIC_DIST_REG_TYPER2_OFF 0x000c
183	/** Error Reporting Status Register (optional) - RW. */
184	#define GIC_DIST_REG_STATUSR_OFF 0x0010
185	/** Set SPI Register - WO. */
186	#define GIC_DIST_REG_SETSPI_NSR_OFF 0x0040
187	/** Clear SPI Register - WO. */
188	#define GIC_DIST_REG_CLRSPI_NSR_OFF 0x0048
189	/** Set SPI, Secure Register - WO. */
190	#define GIC_DIST_REG_SETSPI_SR_OFF 0x0050
191	/** Clear SPI, Secure Register - WO. */
192	#define GIC_DIST_REG_CLRSPI_SR_OFF 0x0058
193
194	/** Interrupt Group Registers, start offset - RW. */
195	#define GIC_DIST_REG_IGROUPRn_OFF_START 0x0080
196	/** Interrupt Group Registers, last offset - RW. */
197	#define GIC_DIST_REG_IGROUPRn_OFF_LAST 0x00fc
198	/** Interrupt Group Registers, range in bytes. */
199	#define GIC_DIST_REG_IGROUPRn_RANGE_SIZE (GIC_DIST_REG_IGROUPRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IGROUPRn_OFF_START)
200
201	/** Interrupt Set Enable Registers, start offset - RW. */
202	#define GIC_DIST_REG_ISENABLERn_OFF_START 0x0100
203	/** Interrupt Set Enable Registers, last offset - RW. */
204	#define GIC_DIST_REG_ISENABLERn_OFF_LAST 0x017c
205	/** Interrupt Set Enable Registers, range in bytes. */
206	#define GIC_DIST_REG_ISENABLERn_RANGE_SIZE (GIC_DIST_REG_ISENABLERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISENABLERn_OFF_START)
207
208	/** Interrupt Clear Enable Registers, start offset - RW. */
209	#define GIC_DIST_REG_ICENABLERn_OFF_START 0x0180
210	/** Interrupt Clear Enable Registers, last offset - RW. */
211	#define GIC_DIST_REG_ICENABLERn_OFF_LAST 0x01fc
212	/** Interrupt Clear Enable Registers, range in bytes. */
213	#define GIC_DIST_REG_ICENABLERn_RANGE_SIZE (GIC_DIST_REG_ICENABLERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICENABLERn_OFF_START)
214
215	/** Interrupt Set Pending Registers, start offset - RW. */
216	#define GIC_DIST_REG_ISPENDRn_OFF_START 0x0200
217	/** Interrupt Set Pending Registers, last offset - RW. */
218	#define GIC_DIST_REG_ISPENDRn_OFF_LAST 0x027c
219	/** Interrupt Set Pending Registers, range in bytes. */
220	#define GIC_DIST_REG_ISPENDRn_RANGE_SIZE (GIC_DIST_REG_ISPENDRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISPENDRn_OFF_START)
221
222	/** Interrupt Clear Pending Registers, start offset - RW. */
223	#define GIC_DIST_REG_ICPENDRn_OFF_START 0x0280
224	/** Interrupt Clear Pending Registers, last offset - RW. */
225	#define GIC_DIST_REG_ICPENDRn_OFF_LAST 0x02fc
226	/** Interrupt Clear Pending Registers, range in bytes. */
227	#define GIC_DIST_REG_ICPENDRn_RANGE_SIZE (GIC_DIST_REG_ICPENDRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICPENDRn_OFF_START)
228
229	/** Interrupt Set Active Registers, start offset - RW. */
230	#define GIC_DIST_REG_ISACTIVERn_OFF_START 0x0300
231	/** Interrupt Set Active Registers, last offset - RW. */
232	#define GIC_DIST_REG_ISACTIVERn_OFF_LAST 0x037c
233	/** Interrupt Set Active Registers, range in bytes. */
234	#define GIC_DIST_REG_ISACTIVERn_RANGE_SIZE (GIC_DIST_REG_ISACTIVERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISACTIVERn_OFF_START)
235
236	/** Interrupt Clear Active Registers, start offset - RW. */
237	#define GIC_DIST_REG_ICACTIVERn_OFF_START 0x0380
238	/** Interrupt Clear Active Registers, last offset - RW. */
239	#define GIC_DIST_REG_ICACTIVERn_OFF_LAST 0x03fc
240	/** Interrupt Clear Active Registers, range in bytes. */
241	#define GIC_DIST_REG_ICACTIVERn_RANGE_SIZE (GIC_DIST_REG_ICACTIVERn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICACTIVERn_OFF_START)
242
243	/** Interrupt Priority Registers, start offset - RW. */
244	#define GIC_DIST_REG_IPRIORITYRn_OFF_START 0x0400
245	/** Interrupt Priority Registers, last offset - RW. */
246	#define GIC_DIST_REG_IPRIORITYRn_OFF_LAST 0x07f8
247	/** Interrupt Priority Registers, range in bytes. */
248	#define GIC_DIST_REG_IPRIORITYRn_RANGE_SIZE (GIC_DIST_REG_IPRIORITYRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IPRIORITYRn_OFF_START)
249
250	/** Interrupt Processor Targets Registers, start offset - RO/RW. */
251	#define GIC_DIST_REG_ITARGETSRn_OFF_START 0x0800
252	/** Interrupt Processor Targets Registers, last offset - RO/RW. */
253	#define GIC_DIST_REG_ITARGETSRn_OFF_LAST 0x0bf8
254
255	/** Interrupt Configuration Registers, start offset - RW. */
256	#define GIC_DIST_REG_ICFGRn_OFF_START 0x0c00
257	/** Interrupt Configuration Registers, last offset - RW. */
258	#define GIC_DIST_REG_ICFGRn_OFF_LAST 0x0cfc
259	/** Interrupt Configuration Registers, range in bytes. */
260	#define GIC_DIST_REG_ICFGRn_RANGE_SIZE (GIC_DIST_REG_ICFGRn_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICFGRn_OFF_START)
261
262	/** Interrupt Group Modifier Registers, start offset - RW. */
263	#define GIC_DIST_REG_IGRPMODRn_OFF_START 0x0d00
264	/** Interrupt Group Modifier Registers, last offset - RW. */
265	#define GIC_DIST_REG_IGRPMODRn_OFF_LAST 0x0d7c
266
267	/** Non-secure Access Control Registers, start offset - RW. */
268	#define GIC_DIST_REG_NSACRn_OFF_START 0x0e00
269	/** Non-secure Access Control Registers, last offset - RW. */
270	#define GIC_DIST_REG_NSACRn_OFF_LAST 0x0efc
271
272	/** Software Generated Interrupt Register - RW. */
273	#define GIC_DIST_REG_SGIR_OFF 0x0f00
274
275	/** SGI Clear Pending Registers, start offset - RW. */
276	#define GIC_DIST_REG_CPENDSGIRn_OFF_START 0x0f10
277	/** SGI Clear Pending Registers, last offset - RW. */
278	#define GIC_DIST_REG_CPENDSGIRn_OFF_LAST 0x0f1c
279	/** SGI Set Pending Registers, start offset - RW. */
280	#define GIC_DIST_REG_SPENDSGIRn_OFF_START 0x0f20
281	/** SGI Set Pending Registers, last offset - RW. */
282	#define GIC_DIST_REG_SPENDSGIRn_OFF_LAST 0x0f2c
283
284	/** Non-maskable Interrupt Registers, start offset - RW. */
285	#define GIC_DIST_REG_INMIn_OFF_START 0x0f80
286	/** Non-maskable Interrupt Registers, last offset - RW. */
287	#define GIC_DIST_REG_INMIn_OFF_LAST 0x0ffc
288
289	/** Interrupt Group Registers for extended SPI range, start offset - RW. */
290	#define GIC_DIST_REG_IGROUPRnE_OFF_START 0x1000
291	/** Interrupt Group Registers for extended SPI range, last offset - RW. */
292	#define GIC_DIST_REG_IGROUPRnE_OFF_LAST 0x107c
293	/** Interrupt Group Registers for extended SPI range, range in bytes. */
294	#define GIC_DIST_REG_IGROUPRnE_RANGE_SIZE (GIC_DIST_REG_IGROUPRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IGROUPRnE_OFF_START)
295
296	/** Interrupt Set Enable Registers for extended SPI range, start offset - RW. */
297	#define GIC_DIST_REG_ISENABLERnE_OFF_START 0x1200
298	/** Interrupt Set Enable Registers for extended SPI range, last offset - RW. */
299	#define GIC_DIST_REG_ISENABLERnE_OFF_LAST 0x127c
300	/** Interrupt Set Enable Registers for extended SPI range, range in bytes. */
301	#define GIC_DIST_REG_ISENABLERnE_RANGE_SIZE (GIC_DIST_REG_ISENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISENABLERnE_OFF_START)
302
303	/** Interrupt Clear Enable Registers for extended SPI range, start offset - RW. */
304	#define GIC_DIST_REG_ICENABLERnE_OFF_START 0x1400
305	/** Interrupt Clear Enable Registers for extended SPI range, last offset - RW. */
306	#define GIC_DIST_REG_ICENABLERnE_OFF_LAST 0x147c
307	/** Interrupt Clear Enable Registers for extended SPI range, range in bytes. */
308	#define GIC_DIST_REG_ICENABLERnE_RANGE_SIZE (GIC_DIST_REG_ICENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICENABLERnE_OFF_START)
309
310	/** Interrupt Set Pending Registers for extended SPI range, start offset - RW. */
311	#define GIC_DIST_REG_ISPENDRnE_OFF_START 0x1600
312	/** Interrupt Set Pending Registers for extended SPI range, last offset - RW. */
313	#define GIC_DIST_REG_ISPENDRnE_OFF_LAST 0x167c
314	/** Interrupt Set Pending Registers for extended SPI range, range in bytes. */
315	#define GIC_DIST_REG_ISPENDRnE_RANGE_SIZE (GIC_DIST_REG_ISPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISPENDRnE_OFF_START)
316
317	/** Interrupt Clear Pending Registers for extended SPI range, start offset - RW. */
318	#define GIC_DIST_REG_ICPENDRnE_OFF_START 0x1800
319	/** Interrupt Clear Pending Registers for extended SPI range, last offset - RW. */
320	#define GIC_DIST_REG_ICPENDRnE_OFF_LAST 0x187c
321	/** Interrupt Clear Pending Registers for extended SPI range, range in bytes. */
322	#define GIC_DIST_REG_ICPENDRnE_RANGE_SIZE (GIC_DIST_REG_ICPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICPENDRnE_OFF_START)
323
324	/** Interrupt Set Active Registers for extended SPI range, start offset - RW. */
325	#define GIC_DIST_REG_ISACTIVERnE_OFF_START 0x1a00
326	/** Interrupt Set Active Registers for extended SPI range, last offset - RW. */
327	#define GIC_DIST_REG_ISACTIVERnE_OFF_LAST 0x1a7c
328	/** Interrupt Set Active Registers for extended SPI range, range in bytes. */
329	#define GIC_DIST_REG_ISACTIVERnE_RANGE_SIZE (GIC_DIST_REG_ISACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ISACTIVERnE_OFF_START)
330
331	/** Interrupt Clear Active Registers for extended SPI range, start offset - RW. */
332	#define GIC_DIST_REG_ICACTIVERnE_OFF_START 0x1c00
333	/** Interrupt Clear Active Registers for extended SPI range, last offset - RW. */
334	#define GIC_DIST_REG_ICACTIVERnE_OFF_LAST 0x1c7c
335	/** Interrupt Clear Active Registers for extended SPI range, range in bytes. */
336	#define GIC_DIST_REG_ICACTIVERnE_RANGE_SIZE (GIC_DIST_REG_ICACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICACTIVERnE_OFF_START)
337
338	/** Interrupt Priority Registers for extended SPI range, start offset - RW. */
339	#define GIC_DIST_REG_IPRIORITYRnE_OFF_START 0x2000
340	/** Interrupt Priority Registers for extended SPI range, last offset - RW. */
341	#define GIC_DIST_REG_IPRIORITYRnE_OFF_LAST 0x23fc
342	/** Interrupt Priority Registers for extended SPI range, range in bytes. */
343	#define GIC_DIST_REG_IPRIORITYRnE_RANGE_SIZE (GIC_DIST_REG_IPRIORITYRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_IPRIORITYRnE_OFF_START)
344
345	/** Interrupt Configuration Registers for extended SPI range, start offset - RW. */
346	#define GIC_DIST_REG_ICFGRnE_OFF_START 0x3000
347	/** Interrupt Configuration Registers for extended SPI range, last offset - RW. */
348	#define GIC_DIST_REG_ICFGRnE_OFF_LAST 0x30fc
349	/** Interrupt Configuration Registers for extended SPI range, range in bytes. */
350	#define GIC_DIST_REG_ICFGRnE_RANGE_SIZE (GIC_DIST_REG_ICFGRnE_OFF_LAST + sizeof(uint32_t) - GIC_DIST_REG_ICFGRnE_OFF_START)
351
352	/** Interrupt Group Modifier Registers for extended SPI range, start offset - RW. */
353	#define GIC_DIST_REG_IGRPMODRnE_OFF_START 0x3400
354	/** Interrupt Group Modifier Registers for extended SPI range, last offset - RW. */
355	#define GIC_DIST_REG_IGRPMODRnE_OFF_LAST 0x347c
356
357	/** Non-secure Access Control Registers for extended SPI range, start offset - RW. */
358	#define GIC_DIST_REG_NSACRnE_OFF_START 0x3600
359	/** Non-secure Access Control Registers for extended SPI range, last offset - RW. */
360	#define GIC_DIST_REG_NSACRnE_OFF_LAST 0x367c
361
362	/** Non-maskable Interrupt Registers for extended SPIs, start offset - RW. */
363	#define GIC_DIST_REG_INMInE_OFF_START 0x3b00
364	/** Non-maskable Interrupt Registers for extended SPIs, last offset - RW. */
365	#define GIC_DIST_REG_INMInE_OFF_LAST 0x3b7c
366
367	/** Interrupt Routing Registers, start offset - RW. */
368	#define GIC_DIST_REG_IROUTERn_OFF_START 0x6100
369	/** Interrupt Routing Registers, last offset - RW. */
370	#define GIC_DIST_REG_IROUTERn_OFF_LAST 0x7fd8
371	/** Interrupt Routing Registers range in bytes. */
372	#define GIC_DIST_REG_IROUTERn_RANGE_SIZE (GIC_DIST_REG_IROUTERn_OFF_LAST + sizeof(uint64_t) - GIC_DIST_REG_IROUTERn_OFF_START)
373
374	/** Interrupt Routing Registers for extended SPI range, start offset - RW. */
375	#define GIC_DIST_REG_IROUTERnE_OFF_START 0x8000
376	/** Interrupt Routing Registers for extended SPI range, last offset - RW. */
377	#define GIC_DIST_REG_IROUTERnE_OFF_LAST 0x9ffc
378	/** Interrupt Routing Registers for extended SPI range, range in bytes. */
379	#define GIC_DIST_REG_IROUTERnE_RANGE_SIZE (GIC_DIST_REG_IROUTERnE_OFF_LAST + sizeof(uint64_t) - GIC_DIST_REG_IROUTERnE_OFF_START)
380
381	#define GIC_DIST_REG_IROUTERn_IRM_BIT 31
382	#define GIC_DIST_REG_IROUTERn_MASK (RT_BIT_32(GIC_DIST_REG_IROUTERn_IRM_BIT) \| 0xffffff)
383	#define GIC_DIST_REG_IROUTERnE_MASK 0xff
384
385	#define GIC_DIST_REG_IROUTERn_IRM_GET(a_Reg) (((a_Reg) >> GIC_DIST_REG_IROUTERn_IRM_BIT) & 1)
386	#define GIC_DIST_REG_IROUTERn_SET(a_fIrm, a_Reg) ((((a_fIrm) << GIC_DIST_REG_IROUTERn_IRM_BIT) \| (a_Reg)) & GIC_DIST_REG_IROUTERn_MASK)
387
388	/** Distributor Peripheral ID2 Register - RO. */
389	#define GIC_DIST_REG_PIDR2_OFF 0xffe8
390	/** Bit 4 - 7 - GIC architecture revision */
391	# define GIC_DIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) \| RT_BIT_32(5) \| RT_BIT_32(6) \
392	\| RT_BIT_32(7))
393	# define GIC_DIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
394	/** GICv1 architecture revision. */
395	# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV1 0x1
396	/** GICv2 architecture revision. */
397	# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV2 0x2
398	/** GICv3 architecture revision. */
399	# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV3 0x3
400	/** GICv4 architecture revision. */
401	# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV4 0x4
402	/** @} */
403
404
405	/** @name GICD - GIC Redistributor registers.
406	* @{ */
407	/** Size of the redistributor register frame. */
408	#define GIC_REDIST_REG_FRAME_SIZE _64K
409	/** Redistributor Control Register - RW. */
410	#define GIC_REDIST_REG_CTLR_OFF 0x0000
411	/** Implementer Identification Register - RO. */
412	#define GIC_REDIST_REG_IIDR_OFF 0x0004
413
414	/** Redistributor Type Register - RO. */
415	#define GIC_REDIST_REG_TYPER_OFF 0x0008
416	/** Bit 0 - Indicates whether the GIC implementation supports physical LPIs. */
417	# define GIC_REDIST_REG_TYPER_PLPIS RT_BIT_32(0)
418	# define GIC_REDIST_REG_TYPER_PLPIS_BIT 0
419	/** Bit 1 - Indicates whether the GIC implementation supports virtual LPIs and the direct injection of those. */
420	# define GIC_REDIST_REG_TYPER_VLPIS RT_BIT_32(1)
421	# define GIC_REDIST_REG_TYPER_VLPIS_BIT 1
422	/** Bit 2 - Controls the functionality of GICR_VPENDBASER.Dirty. */
423	# define GIC_REDIST_REG_TYPER_DIRTY RT_BIT_32(2)
424	# define GIC_REDIST_REG_TYPER_DIRTY_BIT 2
425	/** Bit 3 - Indicates whether the redistributor supports direct injection of LPIs. */
426	# define GIC_REDIST_REG_TYPER_DIRECT_LPI RT_BIT_32(3)
427	# define GIC_REDIST_REG_TYPER_DIRECT_LPI_BIT 3
428	/** Bit 4 - Indicates whether this redistributor is the highest numbered Redistributor in a series. */
429	# define GIC_REDIST_REG_TYPER_LAST RT_BIT_32(4)
430	# define GIC_REDIST_REG_TYPER_LAST_BIT 4
431	/** Bit 5 - Sets support for GICR_CTLR.DPG* bits. */
432	# define GIC_REDIST_REG_TYPER_DPGS RT_BIT_32(5)
433	# define GIC_REDIST_REG_TYPER_DPGS_BIT 5
434	/** Bit 6 - Indicates whether MPAM is supported. */
435	# define GIC_REDIST_REG_TYPER_MPAM RT_BIT_32(6)
436	# define GIC_REDIST_REG_TYPER_MPAM_BIT 6
437	/** Bit 7 - Indicates how the resident vPE is specified. */
438	# define GIC_REDIST_REG_TYPER_RVPEID RT_BIT_32(7)
439	# define GIC_REDIST_REG_TYPER_RVPEID_BIT 7
440	/** Bit 8 - 23 - A unique identifier for the PE. */
441	# define GIC_REDIST_REG_TYPER_CPU_NUMBER UINT32_C(0x00ffff00)
442	# define GIC_REDIST_REG_TYPER_CPU_NUMBER_SET(a_CpuNum) (((a_CpuNum) << 8) & GIC_REDIST_REG_TYPER_CPU_NUMBER)
443	/** Bit 24 - 25 - The affinity level at Redistributorsshare an LPI Configuration table. */
444	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF (RT_BIT_32(24) \| RT_BIT_32(25))
445	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_SET(a_LpiAff) (((a_LpiAff) << 24) & GIC_REDIST_REG_TYPER_CMN_LPI_AFF)
446	/** All Redistributors must share an LPI Configuration table. */
447	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_ALL 0
448	/** All Redistributors with the same affinity 3 value must share an LPI Configuration table. */
449	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3 1
450	/** All Redistributors with the same affinity 3.2 value must share an LPI Configuration table. */
451	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3_2 2
452	/** All Redistributors with the same affinity 3.2.1 value must share an LPI Configuration table. */
453	# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3_2_1 3
454	/** Bit 26 - Indicates whether vSGIs are supported. */
455	# define GIC_REDIST_REG_TYPER_VSGI RT_BIT_32(26)
456	# define GIC_REDIST_REG_TYPER_VSGI_BIT 26
457	/** Bit 27 - 31 - Indicates the maximum PPI INTID that a GIC implementation can support. */
458	# define GIC_REDIST_REG_TYPER_PPI_NUM ( RT_BIT_32(27) \| RT_BIT_32(28) \| RT_BIT_32(29) \
459	\| RT_BIT_32(30) \| RT_BIT_32(31))
460	# define GIC_REDIST_REG_TYPER_PPI_NUM_SET(a_PpiNum) (((a_PpiNum) << 27) & GIC_REDIST_REG_TYPER_PPI_NUM)
461	/** Maximum PPI INTID is 31. */
462	# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_31 0
463	/** Maximum PPI INTID is 1087. */
464	# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 1
465	/** Maximum PPI INTID is 1119. */
466	# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119 2
467
468	/** Redistributor Type Register (the affinity value of the 64-bit register) - RO. */
469	#define GIC_REDIST_REG_TYPER_AFFINITY_OFF 0x000c
470	/** Bit 0 - 31 - The identity of the PE associated with this Redistributor. */
471	# define GIC_REDIST_REG_TYPER_AFFINITY_VALUE UINT32_C(0xffffffff)
472	# define GIC_REDIST_REG_TYPER_AFFINITY_VALUE_SET(a_Aff) ((a_Aff) & GIC_REDIST_REG_TYPER_AFFINITY_VALUE)
473
474
475	/** Redistributor Error Reporting Status Register (optional) - RW. */
476	#define GIC_REDIST_REG_STATUSR_OFF 0x0010
477	/** Redistributor Wake Register - RW. */
478	#define GIC_REDIST_REG_WAKER_OFF 0x0014
479	/** Redistributor Report maximum PARTID and PMG Register - RO. */
480	#define GIC_REDIST_REG_MPAMIDR_OFF 0x0018
481	/** Redistributor Set PARTID and PMG Register - RW. */
482	#define GIC_REDIST_REG_PARTIDR_OFF 0x001c
483	/** Redistributor Set LPI Pending Register - WO. */
484	#define GIC_REDIST_REG_SETLPIR_OFF 0x0040
485	/** Redistributor Clear LPI Pending Register - WO. */
486	#define GIC_REDIST_REG_CLRLPIR_OFF 0x0048
487	/** Redistributor Properties Base Address Register - RW. */
488	#define GIC_REDIST_REG_PROPBASER_OFF 0x0070
489	/** Redistributor LPI Pending Table Base Address Register - RW. */
490	#define GIC_REDIST_REG_PENDBASER_OFF 0x0078
491	/** Redistributor Invalidate LPI Register - WO. */
492	#define GIC_REDIST_REG_INVLPIR_OFF 0x00a0
493	/** Redistributor Invalidate All Register - WO. */
494	#define GIC_REDIST_REG_INVALLR_OFF 0x00b0
495	/** Redistributor Synchronize Register - RO. */
496	#define GIC_REDIST_REG_SYNCR_OFF 0x00c0
497
498	/** Redistributor Peripheral ID2 Register - RO. */
499	#define GIC_REDIST_REG_PIDR2_OFF 0xffe8
500	/** Bit 4 - 7 - GIC architecture revision */
501	# define GIC_REDIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) \| RT_BIT_32(5) \| RT_BIT_32(6) \
502	\| RT_BIT_32(7))
503	# define GIC_REDIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
504	/** GICv1 architecture revision. */
505	# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV1 0x1
506	/** GICv2 architecture revision. */
507	# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV2 0x2
508	/** GICv3 architecture revision. */
509	# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3 0x3
510	/** GICv4 architecture revision. */
511	# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV4 0x4
512	/** @} */
513
514
515	/** @name GICD - GIC SGI and PPI Redistributor registers (Adjacent to the GIC Redistributor register space).
516	* @{ */
517	/** Size of the SGI and PPI redistributor register frame. */
518	#define GIC_REDIST_SGI_PPI_REG_FRAME_SIZE _64K
519
520	/** Interrupt Group Register 0 - RW. */
521	#define GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF 0x0080
522	/** Interrupt Group Register 2 for extended PPI range - RW, last offset. */
523	#define GIC_REDIST_SGI_PPI_REG_IGROUPRnE_OFF_LAST 0x0088
524	/** Interrupt Group Register, range in bytes. */
525	#define GIC_REDIST_SGI_PPI_REG_IGROUPRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_IGROUPRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF)
526
527	/** Interrupt Set Enable Register 0 - RW. */
528	#define GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF 0x0100
529	/** Interrupt Set Enable Register 1 for extended PPI range - RW. */
530	#define GIC_REDIST_SGI_PPI_REG_ISENABLER1E_OFF 0x0104
531	/** Interrupt Set Enable Register 2 for extended PPI range - RW. */
532	#define GIC_REDIST_SGI_PPI_REG_ISENABLER2E_OFF 0x0108
533	#define GIC_REDIST_SGI_PPI_REG_ISENABLERnE_OFF_LAST GIC_REDIST_SGI_PPI_REG_ISENABLER2E_OFF
534	/** Interrupt Set Enable Register, range in bytes. */
535	#define GIC_REDIST_SGI_PPI_REG_ISENABLERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ISENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF)
536
537	/** Interrupt Clear Enable Register 0 - RW. */
538	#define GIC_REDIST_SGI_PPI_REG_ICENABLER0_OFF 0x0180
539	/** Interrupt Clear Enable Register for extended PPI range, start offset - RW. */
540	#define GIC_REDIST_SGI_PPI_REG_ICENABLERnE_OFF_START 0x0184
541	/** Interrupt Clear Enable Register for extended PPI range, last offset - RW. */
542	#define GIC_REDIST_SGI_PPI_REG_ICENABLERnE_OFF_LAST 0x0188
543	/** Interrupt Clear Enable Register, range in bytes. */
544	#define GIC_REDIST_SGI_PPI_REG_ICENABLERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICENABLERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICENABLER0_OFF)
545
546	/** Interrupt Set Pending Register 0 - RW. */
547	#define GIC_REDIST_SGI_PPI_REG_ISPENDR0_OFF 0x0200
548	/** Interrupt Set Pending Registers for extended PPI range, last offset - RW. */
549	#define GIC_REDIST_SGI_PPI_REG_ISPENDRnE_OFF_LAST 0x0208
550	/** Interrupt Set Pending Registers for extended PPI range, range in bytes. */
551	#define GIC_REDIST_SGI_PPI_REG_ISPENDRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ISPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ISPENDR0_OFF)
552
553	/** Interrupt Clear Pending Register 0 - RW. */
554	#define GIC_REDIST_SGI_PPI_REG_ICPENDR0_OFF 0x0280
555	/** Interrupt Clear Pending Registers for extended PPI range, last offset - RW. */
556	#define GIC_REDIST_SGI_PPI_REG_ICPENDRnE_OFF_LAST 0x0288
557	/** Interrupt Clear Pending Register for extended PPI range, range in bytes. */
558	#define GIC_REDIST_SGI_PPI_REG_ICPENDRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICPENDRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICPENDR0_OFF)
559
560	/** Interrupt Set Active Register 0 - RW. */
561	#define GIC_REDIST_SGI_PPI_REG_ISACTIVER0_OFF 0x0300
562	/** Interrupt Set Active Registers for extended PPI range, last offset - RW. */
563	#define GIC_REDIST_SGI_PPI_REG_ISACTIVERnE_OFF_LAST 0x0308
564	/** Interrupt Set Active Registers for extended PPI range, range in bytes. */
565	#define GIC_REDIST_SGI_PPI_REG_ISACTIVERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ISACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ISACTIVER0_OFF)
566
567	/** Interrupt Clear Active Register 0 - RW. */
568	#define GIC_REDIST_SGI_PPI_REG_ICACTIVER0_OFF 0x0380
569	/** Interrupt Clear Active Registers for extended PPI range, last offset - RW. */
570	#define GIC_REDIST_SGI_PPI_REG_ICACTIVERnE_OFF_LAST 0x0388
571	/** Interrupt Clear Active Register for extended PPI range, range in bytes. */
572	#define GIC_REDIST_SGI_PPI_REG_ICACTIVERnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICACTIVERnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICACTIVER0_OFF)
573
574	/** Interrupt Priority Registers, start offset - RW. */
575	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START 0x0400
576	/** Interrupt Priority Registers, last offset - RW. */
577	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_LAST 0x041c
578	/** Interrupt Priority Registers for extended PPI range, start offset - RW. */
579	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_START 0x0420
580	/** Interrupt Priority Registers for extended PPI range, last offset - RW. */
581	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_LAST 0x045c
582	/** Interrupt Priority Registers for extended PPI range, range in bytes. */
583	#define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_START)
584
585	/** SGI Configuration Register - RW. */
586	#define GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF 0x0c00
587	/** PPI Configuration Register - RW. */
588	#define GIC_REDIST_SGI_PPI_REG_ICFGR1_OFF 0x0c04
589	/** Extended PPI Configuration Register, start offset - RW. */
590	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_START 0x0c08
591	/** Extended PPI Configuration Register, last offset - RW. */
592	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_LAST 0x0c14
593	/** SGI Configure Register, range in bytes. */
594	#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_RANGE_SIZE (GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_LAST + sizeof(uint32_t) - GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF)
595
596	/** Interrupt Group Modifier Register 0 - RW. */
597	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR0_OFF 0x0d00
598	/** Interrupt Group Modifier Register 1 for extended PPI range - RW. */
599	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR1E_OFF 0x0d04
600	/** Interrupt Group Modifier Register 2 for extended PPI range - RW. */
601	#define GIC_REDIST_SGI_PPI_REG_IGRPMODR2E_OFF 0x0d08
602
603	/** Non Secure Access Control Register - RW. */
604	#define GIC_REDIST_SGI_PPI_REG_NSACR_OFF 0x0e00
605
606	/** Non maskable Interrupt Register for PPIs - RW. */
607	#define GIC_REDIST_SGI_PPI_REG_INMIR0_OFF 0x0f80
608	/** Non maskable Interrupt Register for Extended PPIs, start offset - RW. */
609	#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_START 0x0f84
610	/** Non maskable Interrupt Register for Extended PPIs, last offset - RW. */
611	#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_LAST 0x0ffc
612	/** @} */
613
614
615	#endif /* !VBOX_INCLUDED_gic_h */
616

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source: vbox/trunk/include/VBox/gic.h

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