VirtualBox

source: vbox/trunk/include/VBox/disopcode.h@ 96014

最後變更 在這個檔案從96014是 96006,由 vboxsync 提交於 3 年 前

Disassembler: Add OP_VPMINSD and fix disassembler table, bugref:9898

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1/** @file
2 * Disassembler - Opcodes
3 */
4
5/*
6 * Copyright (C) 2006-2022 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.alldomusa.eu.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_disopcode_h
27#define VBOX_INCLUDED_disopcode_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assert.h>
33
34#define MODRM_MOD(a) (a>>6)
35#define MODRM_REG(a) ((a>>3)&0x7)
36#define MODRM_RM(a) (a&0x7)
37#define MAKE_MODRM(mod, reg, rm) (((mod&3) << 6) | ((reg&7) << 3) | (rm&7))
38
39#define SIB_SCALE(a) (a>>6)
40#define SIB_INDEX(a) ((a>>3)&0x7)
41#define SIB_BASE(a) (a&0x7)
42
43
44/** @defgroup grp_dis_opcodes Opcodes (DISOPCODE::uOpCode)
45 * @ingroup grp_dis
46 * @{
47 */
48enum OPCODES
49{
50/** @name Full Intel X86 opcode list
51 * @{ */
52 OP_INVALID = 0,
53 OP_OPSIZE,
54 OP_ADDRSIZE,
55 OP_SEG,
56 OP_REPNE,
57 OP_REPE,
58 OP_REX,
59 OP_LOCK,
60#ifndef IN_SLICKEDIT
61 OP_LAST_PREFIX = OP_LOCK, /**< Last prefix for disassembler. */
62#else
63 OP_LAST_PREFIX = 7, /**< Last prefix for disassembler. */
64#endif
65 OP_AND,
66 OP_OR,
67 OP_DAA,
68 OP_SUB,
69 OP_DAS,
70 OP_XOR,
71 OP_AAA,
72 OP_CMP,
73 OP_IMM_GRP1,
74 OP_AAS,
75 OP_INC,
76 OP_DEC,
77 OP_PUSHA,
78 OP_POPA,
79 OP_BOUND,
80 OP_ARPL,
81 OP_PUSH,
82 OP_POP,
83 OP_IMUL,
84 OP_INSB,
85 OP_INSWD,
86 OP_OUTSB,
87 OP_OUTSWD,
88 OP_JO,
89 OP_JNO,
90 OP_JC,
91 OP_JNC,
92 OP_JE,
93 OP_JNE,
94 OP_JBE,
95 OP_JNBE,
96 OP_JS,
97 OP_JNS,
98 OP_JP,
99 OP_JNP,
100 OP_JL,
101 OP_JNL,
102 OP_JLE,
103 OP_JNLE,
104 OP_ADD,
105 OP_TEST,
106 OP_XCHG,
107 OP_MOV,
108 OP_LEA,
109 OP_NOP,
110 OP_CBW,
111 OP_CWD,
112 OP_CALL,
113 OP_WAIT,
114 OP_PUSHF,
115 OP_POPF,
116 OP_SAHF,
117 OP_LAHF,
118 OP_MOVSB,
119 OP_MOVSWD,
120 OP_CMPSB,
121 OP_CMPWD,
122 OP_STOSB,
123 OP_STOSWD,
124 OP_LODSB,
125 OP_LODSWD,
126 OP_SCASB,
127 OP_SCASWD,
128 OP_SHIFT_GRP2,
129 OP_RETN,
130 OP_LES,
131 OP_LDS,
132 OP_ENTER,
133 OP_LEAVE,
134 OP_RETF,
135 OP_INT1,
136 OP_INT3,
137 OP_INT,
138 OP_INTO,
139 OP_IRET,
140 OP_AAM,
141 OP_AAD,
142 OP_XLAT,
143 OP_ESCF0,
144 OP_ESCF1,
145 OP_ESCF2,
146 OP_ESCF3,
147 OP_ESCF4,
148 OP_ESCF5,
149 OP_ESCF6,
150 OP_ESCF7,
151 OP_LOOPNE,
152 OP_LOOPE,
153 OP_LOOP,
154 OP_JECXZ,
155 OP_IN,
156 OP_OUT,
157 OP_JMP,
158 OP_2B_ESC,
159 OP_ADC,
160 OP_SBB,
161 OP_HLT,
162 OP_CMC,
163 OP_UNARY_GRP3,
164 OP_CLC,
165 OP_STC,
166 OP_CLI,
167 OP_STI,
168 OP_CLD,
169 OP_STD,
170 OP_INC_GRP4,
171 OP_IND_GRP5,
172 OP_GRP6,
173 OP_GRP7,
174 OP_LAR,
175 OP_LSL,
176 OP_SYSCALL,
177 OP_CLTS,
178 OP_SYSRET,
179 OP_INVD,
180 OP_WBINVD,
181 OP_ILLUD2,
182 OP_FEMMS,
183 OP_3DNOW,
184 OP_MOVUPS,
185 OP_MOVLPS,
186 OP_MOVHLPS = OP_MOVLPS, /**< @todo OP_MOVHLPS */
187 OP_UNPCKLPS,
188 OP_MOVHPS,
189 OP_MOVLHPS = OP_MOVHPS, /**< @todo OP_MOVLHPS */
190 OP_UNPCKHPS,
191 OP_PREFETCH_GRP16,
192 OP_MOV_CR,
193 OP_MOVAPS,
194 OP_CVTPI2PS,
195 OP_MOVNTPS,
196 OP_CVTTPS2PI,
197 OP_CVTPS2PI,
198 OP_UCOMISS,
199 OP_COMISS,
200 OP_WRMSR,
201 OP_RDTSC,
202 OP_RDMSR,
203 OP_RDPMC,
204 OP_SYSENTER,
205 OP_SYSEXIT,
206 OP_GETSEC,
207 OP_PAUSE,
208 OP_CMOVO,
209 OP_CMOVNO,
210 OP_CMOVC,
211 OP_CMOVNC,
212 OP_CMOVZ,
213 OP_CMOVNZ,
214 OP_CMOVBE,
215 OP_CMOVNBE,
216 OP_CMOVS,
217 OP_CMOVNS,
218 OP_CMOVP,
219 OP_CMOVNP,
220 OP_CMOVL,
221 OP_CMOVNL,
222 OP_CMOVLE,
223 OP_CMOVNLE,
224 OP_MOVMSKPS,
225 OP_SQRTPS,
226 OP_RSQRTPS,
227 OP_RCPPS,
228 OP_ANDPS,
229 OP_ANDNPS,
230 OP_ORPS,
231 OP_XORPS,
232 OP_ADDPS,
233 OP_MULPS,
234 OP_CVTPS2PD,
235 OP_CVTDQ2PS,
236 OP_SUBPS,
237 OP_MINPS,
238 OP_DIVPS,
239 OP_MAXPS,
240 OP_PUNPCKLBW,
241 OP_PUNPCKLWD,
242 OP_PUNPCKLDQ,
243 OP_PACKSSWB,
244 OP_PCMPGTB,
245 OP_PCMPGTW,
246 OP_PCMPGTD,
247 OP_PCMPGTQ,
248 OP_PACKUSWB,
249 OP_PUNPCKHBW,
250 OP_PUNPCKHWD,
251 OP_PUNPCKHDQ,
252 OP_PACKSSDW,
253 OP_MOVD,
254 OP_MOVQ,
255 OP_PSHUFW,
256 OP_3B_ESC4,
257 OP_3B_ESC5,
258 OP_PCMPEQB,
259 OP_PCMPEQW,
260 OP_PCMPEQD,
261 OP_PCMPEQQ,
262 OP_SETO,
263 OP_SETNO,
264 OP_SETC,
265 OP_SETNC,
266 OP_SETE,
267 OP_SETNE,
268 OP_SETBE,
269 OP_SETNBE,
270 OP_SETS,
271 OP_SETNS,
272 OP_SETP,
273 OP_SETNP,
274 OP_SETL,
275 OP_SETNL,
276 OP_SETLE,
277 OP_SETNLE,
278 OP_CPUID,
279 OP_BT,
280 OP_SHLD,
281 OP_RSM,
282 OP_BTS,
283 OP_SHRD,
284 OP_GRP15,
285 OP_CMPXCHG,
286 OP_LSS,
287 OP_BTR,
288 OP_LFS,
289 OP_LGS,
290 OP_MOVZX,
291 OP_GRP10_INV,
292 OP_GRP8,
293 OP_BTC,
294 OP_BSF,
295 OP_BSR,
296 OP_MOVSX,
297 OP_XADD,
298 OP_CMPPS,
299 OP_MOVNTI,
300 OP_PINSRW,
301 OP_PEXTRW,
302 OP_SHUFPS,
303 OP_GRP9,
304 OP_BSWAP,
305 OP_ADDSUBPS,
306 OP_ADDSUBPD,
307 OP_PSRLW,
308 OP_PSRLD,
309 OP_PSRLQ,
310 OP_PADDQ,
311 OP_PMULLW,
312 OP_PMOVMSKB,
313 OP_PSUBUSB,
314 OP_PSUBUSW,
315 OP_PMINUB,
316 OP_PAND,
317 OP_PADDUSB,
318 OP_PADDUSW,
319 OP_PMAXUB,
320 OP_PANDN,
321 OP_PAVGB,
322 OP_PSRAW,
323 OP_PSRAD,
324 OP_PAVGW,
325 OP_PMULHUW,
326 OP_PMULHW,
327 OP_MOVNTQ,
328 OP_PSUBSB,
329 OP_PSUBSW,
330 OP_PMINSW,
331 OP_POR,
332 OP_PADDSB,
333 OP_PADDSW,
334 OP_PMAXSW,
335 OP_PXOR,
336 OP_LDDQU,
337 OP_PSLLW,
338 OP_PSLLD,
339 OP_PSSQ,
340 OP_PMULUDQ,
341 OP_PMADDWD,
342 OP_PSADBW,
343 OP_MASKMOVQ,
344 OP_PSUBB,
345 OP_PSUBW,
346 OP_PSUBD,
347 OP_PSUBQ,
348 OP_PADDB,
349 OP_PADDW,
350 OP_PADDD,
351 OP_MOVUPD,
352 OP_MOVLPD,
353 OP_UNPCKLPD,
354 OP_UNPCKHPD,
355 OP_MOVHPD,
356 OP_MOVAPD,
357 OP_CVTPI2PD,
358 OP_MOVNTPD,
359 OP_CVTTPD2PI,
360 OP_CVTPD2PI,
361 OP_UCOMISD,
362 OP_COMISD,
363 OP_MOVMSKPD,
364 OP_SQRTPD,
365 OP_ANDPD,
366 OP_ANDNPD,
367 OP_ORPD,
368 OP_XORPD,
369 OP_ADDPD,
370 OP_MULPD,
371 OP_CVTPD2PS,
372 OP_CVTPS2DQ,
373 OP_SUBPD,
374 OP_MINPD,
375 OP_DIVPD,
376 OP_MAXPD,
377 OP_GRP12,
378 OP_GRP13,
379 OP_GRP14,
380 OP_GRP17,
381 OP_EMMS,
382 OP_MMX_UD78,
383 OP_MMX_UD79,
384 OP_MMX_UD7A,
385 OP_MMX_UD7B,
386 OP_MMX_UD7C,
387 OP_MMX_UD7D,
388 OP_PUNPCKLQDQ,
389 OP_PUNPCKHQDQ,
390 OP_MOVDQA,
391 OP_PSHUFD,
392 OP_CMPPD,
393 OP_SHUFPD,
394 OP_CVTTPD2DQ,
395 OP_MOVNTDQ,
396 OP_MOVNTDQA,
397 OP_PACKUSDW,
398 OP_PSHUFB,
399 OP_PHADDW,
400 OP_PHADDD,
401 OP_PHADDSW,
402 OP_HADDPS,
403 OP_HADDPD,
404 OP_PMADDUBSW,
405 OP_PHSUBW,
406 OP_PHSUBD,
407 OP_PHSUBSW,
408 OP_HSUBPS,
409 OP_HSUBPD,
410 OP_PSIGNB,
411 OP_PSIGNW,
412 OP_PSIGND,
413 OP_PMULHRSW,
414 OP_PERMILPS,
415 OP_PERMILPD,
416 OP_TESTPS,
417 OP_TESTPD,
418 OP_PBLENDVB,
419 OP_CVTPH2PS,
420 OP_BLENDVPS,
421 OP_BLENDVPD,
422 OP_PERMPS,
423 OP_PERMD,
424 OP_PTEST,
425 OP_BROADCASTSS,
426 OP_BROADCASTSD,
427 OP_BROADCASTF128,
428 OP_PABSB,
429 OP_PABSW,
430 OP_PABSD,
431 OP_PMOVSX,
432 OP_PMOVZX,
433 OP_PMULDQ,
434 OP_PMINSB,
435 OP_PMINSD,
436 OP_PMINUW,
437 OP_PMINUD,
438 OP_PMAXSB,
439 OP_PMAXSD,
440 OP_PMAXUW,
441 OP_PMAXUD,
442 OP_PMULLD,
443 OP_PHMINPOSUW,
444 OP_PSRLVD,
445 OP_PSRAVD,
446 OP_PSLLVD,
447 OP_PBROADCASTD,
448 OP_PBROADCASTQ,
449 OP_PBROADCASTI128,
450 OP_PBROADCASTB,
451 OP_PBROADCASTW,
452 OP_PMASKMOVD,
453 OP_GATHER,
454 OP_FMADDSUB132PS,
455 OP_FMSUBADD132PS,
456 OP_FMADD132PS,
457 OP_FMADD132SS,
458 OP_FMSUB132PS,
459 OP_FMSUB132SS,
460 OP_FNMADD132PS,
461 OP_FNMADD132SS,
462 OP_FNMSUB132PS,
463 OP_FNMSUB132SS,
464 OP_FMADDSUB213PS,
465 OP_FMSUBADD213PS,
466 OP_FMADD213PS,
467 OP_FMADD213SS,
468 OP_FMSUB213PS,
469 OP_FMSUB213SS,
470 OP_FNMADD213PS,
471 OP_FNMADD213SS,
472 OP_FNMSUB213PS,
473 OP_FNMSUB213SS,
474 OP_FMADDSUB231PS,
475 OP_FMSUBADD231PS,
476 OP_FMADD231PS,
477 OP_FMADD231SS,
478 OP_FMSUB231PS,
479 OP_FMSUB231SS,
480 OP_FNMADD231PS,
481 OP_FNMADD231SS,
482 OP_FNMSUB231PS,
483 OP_FNMSUB231SS,
484 OP_AESIMC,
485 OP_AESENC,
486 OP_AESENCLAST,
487 OP_AESDEC,
488 OP_AESDECLAST,
489 OP_MOVBEGM,
490 OP_MOVBEMG,
491 OP_CRC32,
492 OP_POPCNT,
493 OP_TZCNT,
494 OP_LZCNT,
495 OP_ADCX,
496 OP_ADOX,
497 OP_ANDN,
498 OP_BZHI,
499 OP_BEXTR,
500 OP_BLSR,
501 OP_BLSMSK,
502 OP_BLSI,
503 OP_PEXT,
504 OP_PDEP,
505 OP_SHLX,
506 OP_SHRX,
507 OP_SARX,
508 OP_MULX,
509 OP_MASKMOVDQU,
510 OP_MASKMOVPS,
511 OP_MASKMOVPD,
512 OP_MOVSD,
513 OP_CVTSI2SD,
514 OP_CVTTSD2SI,
515 OP_CVTSD2SI,
516 OP_SQRTSD,
517 OP_ADDSD,
518 OP_MULSD,
519 OP_CVTSD2SS,
520 OP_SUBSD,
521 OP_MINSD,
522 OP_DIVSD,
523 OP_MAXSD,
524 OP_PSHUFLW,
525 OP_CMPSD,
526 OP_MOVDQ2Q,
527 OP_CVTPD2DQ,
528 OP_MOVSS,
529 OP_MOVSLDUP,
530 OP_MOVDDUP,
531 OP_MOVSHDUP,
532 OP_CVTSI2SS,
533 OP_CVTTSS2SI,
534 OP_CVTSS2SI,
535 OP_CVTSS2SD,
536 OP_SQRTSS,
537 OP_RSQRTSS,
538 OP_RCPSS,
539 OP_ADDSS,
540 OP_MULSS,
541 OP_CVTTPS2DQ,
542 OP_SUBSS,
543 OP_MINSS,
544 OP_DIVSS,
545 OP_MAXSS,
546 OP_MOVDQU,
547 OP_PSHUFHW,
548 OP_CMPSS,
549 OP_MOVQ2DQ,
550 OP_CVTDQ2PD,
551 OP_PERMQ,
552 OP_PERMPD,
553 OP_PBLENDD,
554 OP_PERM2F128,
555 OP_ROUNDPS,
556 OP_ROUNDPD,
557 OP_ROUNDSS,
558 OP_ROUNDSD,
559 OP_BLENDPS,
560 OP_BLENDPD,
561 OP_PBLENDW,
562 OP_PALIGNR,
563 OP_PEXTRB,
564 OP_PEXTRD,
565 OP_EXTRACTPS,
566 OP_INSERTF128,
567 OP_EXTRACTF128,
568 OP_CVTPS2PH,
569 OP_PINSRB,
570 OP_PINSRD,
571 OP_INSERTPS,
572 OP_INSERTI128,
573 OP_EXTRACTI128,
574 OP_DPPS,
575 OP_DPPD,
576 OP_MPSADBW,
577 OP_PCLMULQDQ,
578 OP_PERM2I128,
579 OP_PCMPESTRM,
580 OP_PCMPESTRI,
581 OP_PCMPISTRM,
582 OP_PCMPISTRI,
583 OP_AESKEYGEN,
584 OP_RORX,
585 OP_VEX3B,
586 OP_VEX2B,
587/** @} */
588
589/** @name Floating point ops
590 * @{ */
591 OP_FADD,
592 OP_FMUL,
593 OP_FCOM,
594 OP_FCOMP,
595 OP_FSUB,
596 OP_FSUBR,
597 OP_FDIV,
598 OP_FDIVR,
599 OP_FLD,
600 OP_FST,
601 OP_FSTP,
602 OP_FLDENV,
603 OP_FSTENV,
604 OP_FSTCW,
605 OP_FXCH,
606 OP_FNOP,
607 OP_FCHS,
608 OP_FABS,
609 OP_FLD1,
610 OP_FLDL2T,
611 OP_FLDL2E,
612 OP_FLDPI,
613 OP_FLDLG2,
614 OP_FLDLN2,
615 OP_FLDZ,
616 OP_F2XM1,
617 OP_FYL2X,
618 OP_FPTAN,
619 OP_FPATAN,
620 OP_FXTRACT,
621 OP_FREM1,
622 OP_FDECSTP,
623 OP_FINCSTP,
624 OP_FPREM,
625 OP_FYL2XP1,
626 OP_FSQRT,
627 OP_FSINCOS,
628 OP_FRNDINT,
629 OP_FSCALE,
630 OP_FSIN,
631 OP_FCOS,
632 OP_FIADD,
633 OP_FIMUL,
634 OP_FISUB,
635 OP_FISUBR,
636 OP_FIDIV,
637 OP_FIDIVR,
638 OP_FCMOVB,
639 OP_FCMOVE,
640 OP_FCMOVBE,
641 OP_FCMOVU,
642 OP_FUCOMPP,
643 OP_FILD,
644 OP_FIST,
645 OP_FISTP,
646 OP_FCMOVNB,
647 OP_FCMOVNE,
648 OP_FCMOVNBE,
649 OP_FCMOVNU,
650 OP_FCLEX,
651 OP_FINIT,
652 OP_FUCOMI,
653 OP_FCOMI,
654 OP_FRSTOR,
655 OP_FSAVE,
656 OP_FNSTSW,
657 OP_FFREE,
658 OP_FUCOM,
659 OP_FUCOMP,
660 OP_FICOM,
661 OP_FICOMP,
662 OP_FADDP,
663 OP_FMULP,
664 OP_FCOMPP,
665 OP_FSUBRP,
666 OP_FSUBP,
667 OP_FDIVRP,
668 OP_FDIVP,
669 OP_FBLD,
670 OP_FBSTP,
671 OP_FCOMIP,
672 OP_FUCOMIP,
673/** @} */
674
675/** @name 3DNow!
676 * @{ */
677 OP_PI2FW,
678 OP_PI2FD,
679 OP_PF2IW,
680 OP_PF2ID,
681 OP_PFPNACC,
682 OP_PFCMPGE,
683 OP_PFMIN,
684 OP_PFRCP,
685 OP_PFRSQRT,
686 OP_PFSUB,
687 OP_PFADD,
688 OP_PFCMPGT,
689 OP_PFMAX,
690 OP_PFRCPIT1,
691 OP_PFRSQRTIT1,
692 OP_PFSUBR,
693 OP_PFACC,
694 OP_PFCMPEQ,
695 OP_PFMUL,
696 OP_PFRCPIT2,
697 OP_PFMULHRW,
698 OP_PFSWAPD,
699 OP_PAVGUSB,
700 OP_PFNACC,
701/** @} */
702 OP_ROL,
703 OP_ROR,
704 OP_RCL,
705 OP_RCR,
706 OP_SHL,
707 OP_SHR,
708 OP_SAR,
709 OP_NOT,
710 OP_NEG,
711 OP_MUL,
712 OP_DIV,
713 OP_IDIV,
714 OP_SLDT,
715 OP_STR,
716 OP_LLDT,
717 OP_LTR,
718 OP_VERR,
719 OP_VERW,
720 OP_SGDT,
721 OP_LGDT,
722 OP_SIDT,
723 OP_LIDT,
724 OP_SMSW,
725 OP_LMSW,
726 OP_INVLPG,
727 OP_CMPXCHG8B,
728 OP_PSLLQ,
729 OP_PSRLDQ,
730 OP_PSLLDQ,
731 OP_FXSAVE,
732 OP_FXRSTOR,
733 OP_LDMXCSR,
734 OP_STMXCSR,
735 OP_XSAVE,
736 OP_XSAVEOPT,
737 OP_XRSTOR,
738 OP_XGETBV,
739 OP_XSETBV,
740 OP_RDFSBASE,
741 OP_RDGSBASE,
742 OP_WRFSBASE,
743 OP_WRGSBASE,
744 OP_LFENCE,
745 OP_MFENCE,
746 OP_SFENCE,
747 OP_PREFETCH,
748 OP_MONITOR,
749 OP_MWAIT,
750 OP_CLFLUSH,
751 OP_CLFLUSHOPT,
752 OP_MOV_DR,
753 OP_MOV_TR,
754 OP_SWAPGS,
755 OP_UD1,
756 OP_UD2,
757/** @name VT-x instructions
758 * @{ */
759 OP_VMREAD,
760 OP_VMWRITE,
761 OP_VMCALL,
762 OP_VMXON,
763 OP_VMXOFF,
764 OP_VMCLEAR,
765 OP_VMLAUNCH,
766 OP_VMRESUME,
767 OP_VMPTRLD,
768 OP_VMPTRST,
769 OP_INVEPT,
770 OP_INVVPID,
771 OP_INVPCID,
772 OP_VMFUNC,
773/** @} */
774/** @name AMD-V instructions
775 * @{ */
776 OP_VMMCALL,
777 OP_VMRUN,
778 OP_VMLOAD,
779 OP_VMSAVE,
780 OP_CLGI,
781 OP_STGI,
782 OP_INVLPGA,
783 OP_SKINIT,
784/** @} */
785/** @name 64 bits instruction
786 * @{ */
787 OP_MOVSXD,
788/** @} */
789/** @name AVX instructions
790 * @{ */
791 /* Manual */
792 OP_VSTMXCSR,
793 OP_VLDMXCSR,
794 OP_VPACKUSDW,
795
796 /* Generated from tables: */
797 OP_VADDPD,
798 OP_VADDPS,
799 OP_VADDSD,
800 OP_VADDSS,
801 OP_VADDSUBPD,
802 OP_VADDSUBPS,
803 OP_VAESDEC,
804 OP_VAESDECLAST,
805 OP_VAESENC,
806 OP_VAESENCLAST,
807 OP_VAESIMC,
808 OP_VAESKEYGEN,
809 OP_VANDNPD,
810 OP_VANDNPS,
811 OP_VANDPD,
812 OP_VANDPS,
813 OP_VBLENDPD,
814 OP_VBLENDPS,
815 OP_VBLENDVPD,
816 OP_VBLENDVPS,
817 OP_VBROADCASTF128,
818 OP_VBROADCASTSD,
819 OP_VBROADCASTSS,
820 OP_VCMPSD,
821 OP_VCMPSS,
822 OP_VCOMISD,
823 OP_VCOMISS,
824 OP_VCVTDQ2PD,
825 OP_VCVTDQ2PS,
826 OP_VCVTPD2DQ,
827 OP_VCVTPD2PS,
828 OP_VCVTPH2PS,
829 OP_VCVTPS2DQ,
830 OP_VCVTPS2PD,
831 OP_VCVTPS2PH,
832 OP_VCVTSD2SS,
833 OP_VCVTSI2SS,
834 OP_VCVTSS2SD,
835 OP_VCVTSS2SI,
836 OP_VCVTTPD2DQ,
837 OP_VCVTTPS2DQ,
838 OP_VCVTTSS2SI,
839 OP_VDIVPD,
840 OP_VDIVPS,
841 OP_VDIVSD,
842 OP_VDIVSS,
843 OP_VDPPD,
844 OP_VDPPS,
845 OP_VEXTRACTF128,
846 OP_VEXTRACTI128,
847 OP_VEXTRACTPS,
848 OP_VFMADD132PS,
849 OP_VFMADD132SS,
850 OP_VFMADD213PS,
851 OP_VFMADD213SS,
852 OP_VFMADD231PS,
853 OP_VFMADD231SS,
854 OP_VFMADDSUB132PS,
855 OP_VFMADDSUB213PS,
856 OP_VFMADDSUB231PS,
857 OP_VFMSUB132PS,
858 OP_VFMSUB132SS,
859 OP_VFMSUB213PS,
860 OP_VFMSUB213SS,
861 OP_VFMSUB231PS,
862 OP_VFMSUB231SS,
863 OP_VFMSUBADD132PS,
864 OP_VFMSUBADD213PS,
865 OP_VFMSUBADD231PS,
866 OP_VFNMADD132PS,
867 OP_VFNMADD132SS,
868 OP_VFNMADD213PS,
869 OP_VFNMADD213SS,
870 OP_VFNMADD231PS,
871 OP_VFNMADD231SS,
872 OP_VFNMSUB132PS,
873 OP_VFNMSUB132SS,
874 OP_VFNMSUB213PS,
875 OP_VFNMSUB213SS,
876 OP_VFNMSUB231PS,
877 OP_VFNMSUB231SS,
878 OP_VGATHER,
879 OP_VHADDPD,
880 OP_VHADDPS,
881 OP_VHSUBPD,
882 OP_VHSUBPS,
883 OP_VINSERTF128,
884 OP_VINSERTI128,
885 OP_VINSERTPS,
886 OP_VLDDQU,
887 OP_VMASKMOVDQU,
888 OP_VMASKMOVPD,
889 OP_VMASKMOVPS,
890 OP_VMAXPD,
891 OP_VMAXPS,
892 OP_VMAXSD,
893 OP_VMAXSS,
894 OP_VMINPD,
895 OP_VMINPS,
896 OP_VMINSD,
897 OP_VMINSS,
898 OP_VMOVAPD,
899 OP_VMOVAPS,
900 OP_VMOVD,
901 OP_VMOVDDUP,
902 OP_VMOVDQA,
903 OP_VMOVDQU,
904 OP_VMOVHPD,
905 OP_VMOVHPS,
906 OP_VMOVLHPS = OP_VMOVHPS, /**< @todo OP_VMOVHPS */
907 OP_VMOVLPD,
908 OP_VMOVLPS,
909 OP_VMOVHLPS = OP_VMOVLPS, /**< @todo OP_VMOVLPS */
910 OP_VMOVMSKPD,
911 OP_VMOVMSKPS,
912 OP_VMOVNTDQ,
913 OP_VMOVNTDQA,
914 OP_VMOVNTPD,
915 OP_VMOVNTPS,
916 OP_VMOVQ,
917 OP_VMOVSD,
918 OP_VMOVSHDUP,
919 OP_VMOVSLDUP,
920 OP_VMOVSS,
921 OP_VMOVUPD,
922 OP_VMOVUPS,
923 OP_VMPSADBW,
924 OP_VMULPD,
925 OP_VMULPS,
926 OP_VMULSD,
927 OP_VMULSS,
928 OP_VORPD,
929 OP_VORPS,
930 OP_VPABSB,
931 OP_VPABSD,
932 OP_VPABSW,
933 OP_VPACKSSDW,
934 OP_VPACKSSWB,
935 OP_VPACKUSWB,
936 OP_VPADDB,
937 OP_VPADDD,
938 OP_VPADDQ,
939 OP_VPADDSB,
940 OP_VPADDSW,
941 OP_VPADDUSB,
942 OP_VPADDUSW,
943 OP_VPADDW,
944 OP_VPALIGNR,
945 OP_VPAND,
946 OP_VPANDN,
947 OP_VPAVGB,
948 OP_VPAVGW,
949 OP_VPBLENDD,
950 OP_VPBLENDVB,
951 OP_VPBLENDW,
952 OP_VPBROADCASTB,
953 OP_VPBROADCASTD,
954 OP_VPBROADCASTI128,
955 OP_VPBROADCASTQ,
956 OP_VPBROADCASTW,
957 OP_VPCLMULQDQ,
958 OP_VPCMPEQB,
959 OP_VPCMPEQD,
960 OP_VPCMPEQQ,
961 OP_VPCMPEQW,
962 OP_VPCMPESTRI,
963 OP_VPCMPESTRM,
964 OP_VPCMPGTB,
965 OP_VPCMPGTD,
966 OP_VPCMPGTQ,
967 OP_VPCMPGTW,
968 OP_VPCMPISTRI,
969 OP_VPCMPISTRM,
970 OP_VPERM2F128,
971 OP_VPERM2I128,
972 OP_VPERMD,
973 OP_VPERMILPD,
974 OP_VPERMILPS,
975 OP_VPERMPD,
976 OP_VPERMPS,
977 OP_VPERMQ,
978 OP_VPEXTRB,
979 OP_VPEXTRD,
980 OP_VPEXTRW,
981 OP_VPHADDD,
982 OP_VPHADDSW,
983 OP_VPHADDW,
984 OP_VPHMINPOSUW,
985 OP_VPHSUBD,
986 OP_VPHSUBSW,
987 OP_VPHSUBW,
988 OP_VPINSRB,
989 OP_VPINSRD,
990 OP_VPINSRW,
991 OP_VPMADDUBSW,
992 OP_VPMADDWD,
993 OP_VPMASKMOVD,
994 OP_VPMAXSB,
995 OP_VPMAXSD,
996 OP_VPMAXSW,
997 OP_VPMAXUB,
998 OP_VPMAXUD,
999 OP_VPMAXUW,
1000 OP_VPMINSB,
1001 OP_VPMINSD,
1002 OP_VPMINSW,
1003 OP_VPMINUB,
1004 OP_VPMINUD,
1005 OP_VPMINUW,
1006 OP_VPMOVMSKB,
1007 OP_VPMOVSX,
1008 OP_VPMOVZX,
1009 OP_VPMULDQ,
1010 OP_VPMULHRSW,
1011 OP_VPMULHUW,
1012 OP_VPMULHW,
1013 OP_VPMULLD,
1014 OP_VPMULLW,
1015 OP_VPMULUDQ,
1016 OP_VPOR,
1017 OP_VPSADBW,
1018 OP_VPSHUFB,
1019 OP_VPSHUFD,
1020 OP_VPSHUFHW,
1021 OP_VPSHUFLW,
1022 OP_VPSIGNB,
1023 OP_VPSIGND,
1024 OP_VPSIGNW,
1025 OP_VPSLLD,
1026 OP_VPSLLQ,
1027 OP_VPSLLVD,
1028 OP_VPSLLW,
1029 OP_VPSRAD,
1030 OP_VPSRAVD,
1031 OP_VPSRAW,
1032 OP_VPSRLD,
1033 OP_VPSRLQ,
1034 OP_VPSRLVD,
1035 OP_VPSRLW,
1036 OP_VPSUBB,
1037 OP_VPSUBD,
1038 OP_VPSUBQ,
1039 OP_VPSUBSB,
1040 OP_VPSUBSW,
1041 OP_VPSUBUSB,
1042 OP_VPSUBUSW,
1043 OP_VPSUBW,
1044 OP_VPTEST,
1045 OP_VPUNPCKHBW,
1046 OP_VPUNPCKHDQ,
1047 OP_VPUNPCKHQDQ,
1048 OP_VPUNPCKHWD,
1049 OP_VPUNPCKLBW,
1050 OP_VPUNPCKLDQ,
1051 OP_VPUNPCKLQDQ,
1052 OP_VPUNPCKLWD,
1053 OP_VPXOR,
1054 OP_VRCPPS,
1055 OP_VRCPSS,
1056 OP_VROUNDPD,
1057 OP_VROUNDPS,
1058 OP_VROUNDSD,
1059 OP_VROUNDSS,
1060 OP_VRSQRTPS,
1061 OP_VRSQRTSS,
1062 OP_VSHUFPD,
1063 OP_VSHUFPS,
1064 OP_VSQRTPD,
1065 OP_VSQRTPS,
1066 OP_VSQRTSD,
1067 OP_VSQRTSS,
1068 OP_VSUBPD,
1069 OP_VSUBPS,
1070 OP_VSUBSD,
1071 OP_VSUBSS,
1072 OP_VTESTPD,
1073 OP_VTESTPS,
1074 OP_VUCOMISD,
1075 OP_VUCOMISS,
1076 OP_VUNPCKHPD,
1077 OP_VUNPCKHPS,
1078 OP_VUNPCKLPD,
1079 OP_VUNPCKLPS,
1080 OP_VVPACKUSDW,
1081 OP_VXORPD,
1082 OP_VXORPS,
1083 OP_VZEROALL,
1084
1085/** @} */
1086 OP_END_OF_OPCODES
1087};
1088AssertCompile(OP_LOCK == 7);
1089AssertCompile(OP_END_OF_OPCODES < 1024 /* see 15 byte DISOPCODE variant */);
1090/** @} */
1091
1092
1093/** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1,
1094 * DISOPCODE::fParam2, DISOPCODE::fParam3)
1095 * @ingroup grp_dis
1096 * @{
1097 */
1098
1099/**
1100 * @remarks Register order is important for translations!!
1101 */
1102enum OP_PARM
1103{
1104 OP_PARM_NONE,
1105
1106 OP_PARM_REG_EAX,
1107 OP_PARM_REG_GEN32_START = OP_PARM_REG_EAX,
1108 OP_PARM_REG_ECX,
1109 OP_PARM_REG_EDX,
1110 OP_PARM_REG_EBX,
1111 OP_PARM_REG_ESP,
1112 OP_PARM_REG_EBP,
1113 OP_PARM_REG_ESI,
1114 OP_PARM_REG_EDI,
1115 OP_PARM_REG_GEN32_END = OP_PARM_REG_EDI,
1116
1117 OP_PARM_REG_ES,
1118 OP_PARM_REG_SEG_START = OP_PARM_REG_ES,
1119 OP_PARM_REG_CS,
1120 OP_PARM_REG_SS,
1121 OP_PARM_REG_DS,
1122 OP_PARM_REG_FS,
1123 OP_PARM_REG_GS,
1124 OP_PARM_REG_SEG_END = OP_PARM_REG_GS,
1125
1126 OP_PARM_REG_AX,
1127 OP_PARM_REG_GEN16_START = OP_PARM_REG_AX,
1128 OP_PARM_REG_CX,
1129 OP_PARM_REG_DX,
1130 OP_PARM_REG_BX,
1131 OP_PARM_REG_SP,
1132 OP_PARM_REG_BP,
1133 OP_PARM_REG_SI,
1134 OP_PARM_REG_DI,
1135 OP_PARM_REG_GEN16_END = OP_PARM_REG_DI,
1136
1137 OP_PARM_REG_AL,
1138 OP_PARM_REG_GEN8_START = OP_PARM_REG_AL,
1139 OP_PARM_REG_CL,
1140 OP_PARM_REG_DL,
1141 OP_PARM_REG_BL,
1142 OP_PARM_REG_AH,
1143 OP_PARM_REG_CH,
1144 OP_PARM_REG_DH,
1145 OP_PARM_REG_BH,
1146 OP_PARM_REG_GEN8_END = OP_PARM_REG_BH,
1147
1148 OP_PARM_REGFP_0,
1149 OP_PARM_REG_FP_START = OP_PARM_REGFP_0,
1150 OP_PARM_REGFP_1,
1151 OP_PARM_REGFP_2,
1152 OP_PARM_REGFP_3,
1153 OP_PARM_REGFP_4,
1154 OP_PARM_REGFP_5,
1155 OP_PARM_REGFP_6,
1156 OP_PARM_REGFP_7,
1157 OP_PARM_REG_FP_END = OP_PARM_REGFP_7,
1158
1159 OP_PARM_NTA,
1160 OP_PARM_T0,
1161 OP_PARM_T1,
1162 OP_PARM_T2,
1163 OP_PARM_1,
1164
1165 OP_PARM_REX,
1166 OP_PARM_REX_START = OP_PARM_REX,
1167 OP_PARM_REX_B,
1168 OP_PARM_REX_X,
1169 OP_PARM_REX_XB,
1170 OP_PARM_REX_R,
1171 OP_PARM_REX_RB,
1172 OP_PARM_REX_RX,
1173 OP_PARM_REX_RXB,
1174 OP_PARM_REX_W,
1175 OP_PARM_REX_WB,
1176 OP_PARM_REX_WX,
1177 OP_PARM_REX_WXB,
1178 OP_PARM_REX_WR,
1179 OP_PARM_REX_WRB,
1180 OP_PARM_REX_WRX,
1181 OP_PARM_REX_WRXB,
1182
1183 OP_PARM_REG_RAX,
1184 OP_PARM_REG_GEN64_START = OP_PARM_REG_RAX,
1185 OP_PARM_REG_RCX,
1186 OP_PARM_REG_RDX,
1187 OP_PARM_REG_RBX,
1188 OP_PARM_REG_RSP,
1189 OP_PARM_REG_RBP,
1190 OP_PARM_REG_RSI,
1191 OP_PARM_REG_RDI,
1192 OP_PARM_REG_R8,
1193 OP_PARM_REG_R9,
1194 OP_PARM_REG_R10,
1195 OP_PARM_REG_R11,
1196 OP_PARM_REG_R12,
1197 OP_PARM_REG_R13,
1198 OP_PARM_REG_R14,
1199 OP_PARM_REG_R15,
1200 OP_PARM_REG_GEN64_END = OP_PARM_REG_R15
1201};
1202
1203
1204/* 8-bit GRP aliases (for IEM). */
1205#define OP_PARM_AL OP_PARM_REG_AL
1206
1207/* GPR aliases for op-size specified register sizes (for IEM). */
1208#define OP_PARM_rAX OP_PARM_REG_EAX
1209#define OP_PARM_rCX OP_PARM_REG_ECX
1210#define OP_PARM_rDX OP_PARM_REG_EDX
1211#define OP_PARM_rBX OP_PARM_REG_EBX
1212#define OP_PARM_rSP OP_PARM_REG_ESP
1213#define OP_PARM_rBP OP_PARM_REG_EBP
1214#define OP_PARM_rSI OP_PARM_REG_ESI
1215#define OP_PARM_rDI OP_PARM_REG_EDI
1216
1217/* SREG aliases (for IEM). */
1218#define OP_PARM_ES OP_PARM_REG_ES
1219#define OP_PARM_CS OP_PARM_REG_CS
1220#define OP_PARM_SS OP_PARM_REG_SS
1221#define OP_PARM_DS OP_PARM_REG_DS
1222#define OP_PARM_FS OP_PARM_REG_FS
1223#define OP_PARM_GS OP_PARM_REG_GS
1224
1225/*
1226 * Note! We don't document anything here if we can help it, because it we love
1227 * wasting other peoples time figuring out crypting crap. The new VEX
1228 * stuff of course uphelds this vexing tradition. Aaaaaaaaaaaaaaaaaaarg!
1229 */
1230
1231#define OP_PARM_VTYPE(a) ((unsigned)a & 0xFE0)
1232#define OP_PARM_VSUBTYPE(a) ((unsigned)a & 0x01F)
1233
1234#define OP_PARM_A 0x100
1235#define OP_PARM_VARIABLE OP_PARM_A
1236#define OP_PARM_E 0x120
1237#define OP_PARM_F 0x140
1238#define OP_PARM_G 0x160
1239#define OP_PARM_I 0x180
1240#define OP_PARM_J 0x1A0
1241#define OP_PARM_M 0x1C0
1242#define OP_PARM_O 0x1E0
1243#define OP_PARM_R 0x200
1244#define OP_PARM_X 0x220
1245#define OP_PARM_Y 0x240
1246
1247/* Grouped rare parameters for optimization purposes */
1248#define IS_OP_PARM_RARE(a) ((a & 0xF00) >= 0x300)
1249#define OP_PARM_C 0x300 /* control register */
1250#define OP_PARM_D 0x320 /* debug register */
1251#define OP_PARM_S 0x340 /* segment register */
1252#define OP_PARM_T 0x360 /* test register */
1253#define OP_PARM_Q 0x380
1254#define OP_PARM_P 0x3A0 /* mmx register */
1255#define OP_PARM_W 0x3C0 /* xmm register */
1256#define OP_PARM_V 0x3E0
1257#define OP_PARM_U 0x400 /* The R/M field of the ModR/M byte selects XMM/YMM register. */
1258#define OP_PARM_B 0x420 /* VEX.vvvv field select general purpose register. */
1259#define OP_PARM_H 0x440
1260#define OP_PARM_L 0x460
1261
1262#define OP_PARM_NONE 0
1263#define OP_PARM_a 0x1 /**< Operand to bound instruction. */
1264#define OP_PARM_b 0x2 /**< Byte (always). */
1265#define OP_PARM_d 0x3 /**< Double word (always). */
1266#define OP_PARM_dq 0x4 /**< Double quad word (always). */
1267#define OP_PARM_p 0x5 /**< Far pointer (subject to opsize). */
1268#define OP_PARM_pd 0x6 /**< 128-bit or 256-bit double precision floating point data. */
1269#define OP_PARM_pi 0x7 /**< Quad word MMX register. */
1270#define OP_PARM_ps 0x8 /**< 128-bit or 256-bit single precision floating point data. */
1271#define OP_PARM_q 0xA /**< Quad word (always). */
1272#define OP_PARM_s 0xB /**< Descriptor table size (SIDT/LIDT/SGDT/LGDT). */
1273#define OP_PARM_sd 0xC /**< Scalar element of 128-bit double precision floating point data. */
1274#define OP_PARM_ss 0xD /**< Scalar element of 128-bit single precision floating point data. */
1275#define OP_PARM_v 0xE /**< Word, double word, or quad word depending on opsize. */
1276#define OP_PARM_w 0xF /**< Word (always). */
1277#define OP_PARM_x 0x10 /**< Double quad word (dq) or quad quad word (qq) depending on opsize. */
1278#define OP_PARM_y 0x11 /**< Double word or quad word depending on opsize. */
1279#define OP_PARM_z 0x12 /**< Word (16-bit opsize) or double word (32-bit/64-bit opsize). */
1280#define OP_PARM_qq 0x13 /**< Quad quad word. */
1281
1282
1283#define OP_PARM_Ap (OP_PARM_A+OP_PARM_p)
1284#define OP_PARM_By (OP_PARM_B+OP_PARM_y)
1285#define OP_PARM_Cd (OP_PARM_C+OP_PARM_d)
1286#define OP_PARM_Dd (OP_PARM_D+OP_PARM_d)
1287#define OP_PARM_Eb (OP_PARM_E+OP_PARM_b)
1288#define OP_PARM_Ed (OP_PARM_E+OP_PARM_d)
1289#define OP_PARM_Ep (OP_PARM_E+OP_PARM_p)
1290#define OP_PARM_Ev (OP_PARM_E+OP_PARM_v)
1291#define OP_PARM_Ew (OP_PARM_E+OP_PARM_w)
1292#define OP_PARM_Ey (OP_PARM_E+OP_PARM_y)
1293#define OP_PARM_Fv (OP_PARM_F+OP_PARM_v)
1294#define OP_PARM_Gb (OP_PARM_G+OP_PARM_b)
1295#define OP_PARM_Gd (OP_PARM_G+OP_PARM_d)
1296#define OP_PARM_Gv (OP_PARM_G+OP_PARM_v)
1297#define OP_PARM_Gw (OP_PARM_G+OP_PARM_w)
1298#define OP_PARM_Gy (OP_PARM_G+OP_PARM_y)
1299#define OP_PARM_Hq (OP_PARM_H+OP_PARM_q)
1300#define OP_PARM_Hps (OP_PARM_H+OP_PARM_ps)
1301#define OP_PARM_Hpd (OP_PARM_H+OP_PARM_pd)
1302#define OP_PARM_Hdq (OP_PARM_H+OP_PARM_dq)
1303#define OP_PARM_Hqq (OP_PARM_H+OP_PARM_qq)
1304#define OP_PARM_Hsd (OP_PARM_H+OP_PARM_sd)
1305#define OP_PARM_Hss (OP_PARM_H+OP_PARM_ss)
1306#define OP_PARM_Hx (OP_PARM_H+OP_PARM_x)
1307#define OP_PARM_Ib (OP_PARM_I+OP_PARM_b)
1308#define OP_PARM_Id (OP_PARM_I+OP_PARM_d)
1309#define OP_PARM_Iq (OP_PARM_I+OP_PARM_q)
1310#define OP_PARM_Iw (OP_PARM_I+OP_PARM_w)
1311#define OP_PARM_Iv (OP_PARM_I+OP_PARM_v)
1312#define OP_PARM_Iz (OP_PARM_I+OP_PARM_z)
1313#define OP_PARM_Jb (OP_PARM_J+OP_PARM_b)
1314#define OP_PARM_Jv (OP_PARM_J+OP_PARM_v)
1315#define OP_PARM_Ma (OP_PARM_M+OP_PARM_a)
1316#define OP_PARM_Mb (OP_PARM_M+OP_PARM_b)
1317#define OP_PARM_Mw (OP_PARM_M+OP_PARM_w)
1318#define OP_PARM_Md (OP_PARM_M+OP_PARM_d)
1319#define OP_PARM_Mp (OP_PARM_M+OP_PARM_p)
1320#define OP_PARM_Mq (OP_PARM_M+OP_PARM_q)
1321#define OP_PARM_Mdq (OP_PARM_M+OP_PARM_dq)
1322#define OP_PARM_Ms (OP_PARM_M+OP_PARM_s)
1323#define OP_PARM_Mx (OP_PARM_M+OP_PARM_x)
1324#define OP_PARM_My (OP_PARM_M+OP_PARM_y)
1325#define OP_PARM_Mps (OP_PARM_M+OP_PARM_ps)
1326#define OP_PARM_Mpd (OP_PARM_M+OP_PARM_pd)
1327#define OP_PARM_Ob (OP_PARM_O+OP_PARM_b)
1328#define OP_PARM_Ov (OP_PARM_O+OP_PARM_v)
1329#define OP_PARM_Pq (OP_PARM_P+OP_PARM_q)
1330#define OP_PARM_Pd (OP_PARM_P+OP_PARM_d)
1331#define OP_PARM_Qd (OP_PARM_Q+OP_PARM_d)
1332#define OP_PARM_Qq (OP_PARM_Q+OP_PARM_q)
1333#define OP_PARM_Rd (OP_PARM_R+OP_PARM_d)
1334#define OP_PARM_Rw (OP_PARM_R+OP_PARM_w)
1335#define OP_PARM_Ry (OP_PARM_R+OP_PARM_y)
1336#define OP_PARM_Sw (OP_PARM_S+OP_PARM_w)
1337#define OP_PARM_Td (OP_PARM_T+OP_PARM_d)
1338#define OP_PARM_Ux (OP_PARM_U+OP_PARM_x)
1339#define OP_PARM_Vq (OP_PARM_V+OP_PARM_q)
1340#define OP_PARM_Vx (OP_PARM_V+OP_PARM_x)
1341#define OP_PARM_Vy (OP_PARM_V+OP_PARM_y)
1342#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1343/*#define OP_PARM_Ws (OP_PARM_W+OP_PARM_s) - wtf? Same as lgdt (OP_PARM_Ms)?*/
1344#define OP_PARM_Wx (OP_PARM_W+OP_PARM_x)
1345#define OP_PARM_Xb (OP_PARM_X+OP_PARM_b)
1346#define OP_PARM_Xv (OP_PARM_X+OP_PARM_v)
1347#define OP_PARM_Yb (OP_PARM_Y+OP_PARM_b)
1348#define OP_PARM_Yv (OP_PARM_Y+OP_PARM_v)
1349
1350#define OP_PARM_Vps (OP_PARM_V+OP_PARM_ps)
1351#define OP_PARM_Vss (OP_PARM_V+OP_PARM_ss)
1352#define OP_PARM_Vpd (OP_PARM_V+OP_PARM_pd)
1353#define OP_PARM_Vdq (OP_PARM_V+OP_PARM_dq)
1354#define OP_PARM_Wps (OP_PARM_W+OP_PARM_ps)
1355#define OP_PARM_Wpd (OP_PARM_W+OP_PARM_pd)
1356#define OP_PARM_Wss (OP_PARM_W+OP_PARM_ss)
1357#define OP_PARM_Ww (OP_PARM_W+OP_PARM_w)
1358#define OP_PARM_Wd (OP_PARM_W+OP_PARM_d)
1359#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1360#define OP_PARM_Wdq (OP_PARM_W+OP_PARM_dq)
1361#define OP_PARM_Wqq (OP_PARM_W+OP_PARM_qq)
1362#define OP_PARM_Ppi (OP_PARM_P+OP_PARM_pi)
1363#define OP_PARM_Qpi (OP_PARM_Q+OP_PARM_pi)
1364#define OP_PARM_Qdq (OP_PARM_Q+OP_PARM_dq)
1365#define OP_PARM_Vsd (OP_PARM_V+OP_PARM_sd)
1366#define OP_PARM_Wsd (OP_PARM_W+OP_PARM_sd)
1367#define OP_PARM_Vqq (OP_PARM_V+OP_PARM_qq)
1368#define OP_PARM_Pdq (OP_PARM_P+OP_PARM_dq)
1369#define OP_PARM_Ups (OP_PARM_U+OP_PARM_ps)
1370#define OP_PARM_Upd (OP_PARM_U+OP_PARM_pd)
1371#define OP_PARM_Udq (OP_PARM_U+OP_PARM_dq)
1372#define OP_PARM_Lx (OP_PARM_L+OP_PARM_x)
1373
1374/* For making IEM / bs3-cpu-generated-1 happy: */
1375#define OP_PARM_Ed_WO OP_PARM_Ed /**< Annotates write only operand. */
1376#define OP_PARM_Eq (OP_PARM_E+OP_PARM_q)
1377#define OP_PARM_Eq_WO OP_PARM_Eq /**< Annotates write only operand. */
1378#define OP_PARM_Gv_RO OP_PARM_Gv /**< Annotates read only first operand (default is readwrite). */
1379#define OP_PARM_HssHi OP_PARM_Hx /**< Register referenced by VEX.vvvv, bits [127:32]. */
1380#define OP_PARM_HsdHi OP_PARM_Hx /**< Register referenced by VEX.vvvv, bits [127:64]. */
1381#define OP_PARM_HqHi OP_PARM_Hx /**< Register referenced by VEX.vvvv, bits [127:64]. */
1382#define OP_PARM_M_RO OP_PARM_M /**< Annotates read only memory of variable operand size (xrstor). */
1383#define OP_PARM_M_RW OP_PARM_M /**< Annotates read-write memory of variable operand size (xsave). */
1384#define OP_PARM_Mb_RO OP_PARM_Mb /**< Annotates read only memory byte operand. */
1385#define OP_PARM_Md_RO OP_PARM_Md /**< Annotates read only memory operand. */
1386#define OP_PARM_Md_WO OP_PARM_Md /**< Annotates write only memory operand. */
1387#define OP_PARM_Mdq_WO OP_PARM_Mdq /**< Annotates write only memory operand. */
1388#define OP_PARM_Mq_WO OP_PARM_Mq /**< Annotates write only memory quad word operand. */
1389#define OP_PARM_Mps_WO OP_PARM_Mps /**< Annotates write only memory operand. */
1390#define OP_PARM_Mpd_WO OP_PARM_Mpd /**< Annotates write only memory operand. */
1391#define OP_PARM_Mx_WO OP_PARM_Mx /**< Annotates write only memory operand. */
1392#define OP_PARM_PdZx_WO OP_PARM_Pd /**< Annotates write only operand and zero extends to 64-bit. */
1393#define OP_PARM_Pq_WO OP_PARM_Pq /**< Annotates write only operand. */
1394#define OP_PARM_Qq_WO OP_PARM_Qq /**< Annotates write only operand. */
1395#define OP_PARM_Nq OP_PARM_Qq /**< Missing 'N' class (MMX reg selected by modrm.mem) in disasm. */
1396#define OP_PARM_Uq (OP_PARM_U+OP_PARM_q)
1397#define OP_PARM_UqHi (OP_PARM_U+OP_PARM_dq)
1398#define OP_PARM_Uss (OP_PARM_U+OP_PARM_ss)
1399#define OP_PARM_Uss_WO OP_PARM_Uss /**< Annotates write only operand. */
1400#define OP_PARM_Usd (OP_PARM_U+OP_PARM_sd)
1401#define OP_PARM_Usd_WO OP_PARM_Usd /**< Annotates write only operand. */
1402#define OP_PARM_Vd (OP_PARM_V+OP_PARM_d)
1403#define OP_PARM_Vd_WO OP_PARM_Vd /**< Annotates write only operand. */
1404#define OP_PARM_VdZx_WO OP_PARM_Vd /**< Annotates that the registers get their upper bits cleared */
1405#define OP_PARM_Vdq_WO OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are accessed. */
1406#define OP_PARM_Vpd_WO OP_PARM_Vpd /**< Annotates write only operand. */
1407#define OP_PARM_Vps_WO OP_PARM_Vps /**< Annotates write only operand. */
1408#define OP_PARM_Vq_WO OP_PARM_Vq /**< Annotates write only operand. */
1409#define OP_PARM_VqHi OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are accessed. */
1410#define OP_PARM_VqHi_WO OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are written. */
1411#define OP_PARM_VqZx_WO OP_PARM_Vq /**< Annotates that the registers get their upper bits cleared */
1412#define OP_PARM_VsdZx_WO OP_PARM_Vsd /**< Annotates that the registers get their upper bits cleared. */
1413#define OP_PARM_VssZx_WO OP_PARM_Vss /**< Annotates that the registers get their upper bits cleared. */
1414#define OP_PARM_Vss_WO OP_PARM_Vss /**< Annotates write only operand. */
1415#define OP_PARM_Vsd_WO OP_PARM_Vsd /**< Annotates write only operand. */
1416#define OP_PARM_Vx_WO OP_PARM_Vx /**< Annotates write only operand. */
1417#define OP_PARM_Wpd_WO OP_PARM_Wpd /**< Annotates write only operand. */
1418#define OP_PARM_Wps_WO OP_PARM_Wps /**< Annotates write only operand. */
1419#define OP_PARM_Wq_WO OP_PARM_Wq /**< Annotates write only operand. */
1420#define OP_PARM_WqZxReg_WO OP_PARM_Wq /**< Annotates that register targets get their upper bits cleared. */
1421#define OP_PARM_Wss_WO OP_PARM_Wss /**< Annotates write only operand. */
1422#define OP_PARM_Wsd_WO OP_PARM_Wsd /**< Annotates write only operand. */
1423#define OP_PARM_Wx_WO OP_PARM_Wx /**< Annotates write only operand. */
1424
1425/** @} */
1426
1427#endif /* !VBOX_INCLUDED_disopcode_h */
1428
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