| 1 | <?xml version='1.0' encoding='UTF-8'?>
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| 2 | <!DOCTYPE topic PUBLIC "-//OASIS//DTD DITA Topic//EN" "topic.dtd">
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| 3 | <topic xml:lang="en-us" id="nestedpaging">
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| 4 | <title><?oxy_comment_start author="Mhari Duncan" timestamp="20250115T154133+0000" comment="Put this in context of configuring VM"?>Nested Paging and VPIDs<?oxy_comment_end?></title>
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| 5 |
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| 6 | <body>
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| 7 | <p>
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| 8 | In addition to normal hardware virtualization, your processor may
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| 9 | also support the following additional sophisticated techniques:
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| 10 | </p>
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| 11 | <ul>
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| 12 | <li>
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| 13 | <p>
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| 14 | Nested paging implements some memory management in hardware,
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| 15 | which can greatly accelerate hardware virtualization since
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| 16 | these tasks no longer need to be performed by the
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| 17 | virtualization software.
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| 18 | </p>
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| 19 | <p>
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| 20 | With nested paging, the hardware provides another level of
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| 21 | indirection when translating linear to physical addresses.
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| 22 | Page tables function as before, but linear addresses are now
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| 23 | translated to "guest physical" addresses first and not
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| 24 | physical addresses directly. A new set of paging registers now
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| 25 | exists under the traditional paging mechanism and translates
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| 26 | from guest physical addresses to host physical addresses,
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| 27 | which are used to access memory.
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| 28 | </p>
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| 29 | <p>
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| 30 | Nested paging eliminates the overhead caused by VM exits and
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| 31 | page table accesses. In essence, with nested page tables the
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| 32 | guest can handle paging without intervention from the
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| 33 | hypervisor. Nested paging thus significantly improves
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| 34 | virtualization performance.
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| 35 | </p>
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| 36 | <p>
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| 37 | On AMD processors, nested paging has been available starting
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| 38 | with the Barcelona (K10) architecture. They now call it rapid
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| 39 | virtualization indexing (RVI). Intel added support for nested
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| 40 | paging, which they call extended page tables (EPT), with their
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| 41 | Core i7 (Nehalem) processors.
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| 42 | </p>
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| 43 | <p> If nested paging is enabled, the <ph conkeyref="vbox-conkeyref-phrases/product-name"/> hypervisor can also use <i>large pages</i> to reduce TLB usage and overhead. This can yield a performance improvement of up to 5%. To enable this feature for a VM, you use the <userinput>VBoxManage modifyvm --large-pages</userinput> command. See <xref href="../cli_topics/vboxmanage-modifyvm.dita"/>.</p>
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| 44 | <p>
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| 45 | If you have an Intel CPU with EPT, please consult
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| 46 | <xref href="sec-rec-cve-2018-3646.dita#sec-rec-cve-2018-3646"/> for security concerns
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| 47 | regarding EPT.
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| 48 | </p>
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| 49 | </li>
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| 50 | <li>
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| 51 | <p>
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| 52 | On Intel CPUs, a hardware feature called Virtual Processor
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| 53 | Identifiers (VPIDs) can greatly accelerate context switching
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| 54 | by reducing the need for expensive flushing of the processor's
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| 55 | Translation Lookaside Buffers (TLBs).
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| 56 | </p>
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| 57 | <p> To enable these features for a VM, you use the <userinput>VBoxManage modifyvm --vtx-vpid</userinput> and <userinput>VBoxManage modifyvm --large-pages</userinput> commands. See <xref href="../cli_topics/vboxmanage-modifyvm.dita"/>.</p>
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| 58 | </li>
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| 59 | </ul>
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| 60 | </body>
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| 61 |
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| 62 | </topic>
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